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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
b907abc9 RC |
2 | /* |
3 | * Xilinx ML510 Reference Design support | |
4 | * | |
5 | * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design. | |
6 | * The reference design contains a bug which prevent PCI DMA from working | |
7 | * properly. A description of the bug is given in the plbv46_pci section. It | |
8 | * needs to be fixed by the user until Xilinx updates their reference design. | |
9 | * | |
10 | * Copyright 2009, Roderick Colenbrander | |
11 | */ | |
12 | ||
13 | /dts-v1/; | |
14 | / { | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | compatible = "xlnx,ml510-ref-design", "xlnx,virtex440"; | |
18 | dcr-parent = <&ppc440_0>; | |
19 | DDR2_SDRAM_DIMM0: memory@0 { | |
20 | device_type = "memory"; | |
21 | reg = < 0x0 0x20000000 >; | |
22 | } ; | |
23 | alias { | |
24 | ethernet0 = &Hard_Ethernet_MAC; | |
25 | serial0 = &RS232_Uart_1; | |
26 | } ; | |
27 | chosen { | |
28 | bootargs = "console=ttyS0 root=/dev/ram"; | |
29 | linux,stdout-path = "/plb@0/serial@83e00000"; | |
30 | } ; | |
31 | cpus { | |
32 | #address-cells = <1>; | |
33 | #cpus = <0x1>; | |
34 | #size-cells = <0>; | |
35 | ppc440_0: cpu@0 { | |
36 | #address-cells = <1>; | |
37 | #size-cells = <1>; | |
38 | clock-frequency = <300000000>; | |
39 | compatible = "PowerPC,440", "ibm,ppc440"; | |
40 | d-cache-line-size = <0x20>; | |
41 | d-cache-size = <0x8000>; | |
42 | dcr-access-method = "native"; | |
43 | dcr-controller ; | |
44 | device_type = "cpu"; | |
45 | i-cache-line-size = <0x20>; | |
46 | i-cache-size = <0x8000>; | |
47 | model = "PowerPC,440"; | |
48 | reg = <0>; | |
49 | timebase-frequency = <300000000>; | |
50 | xlnx,apu-control = <0x2000>; | |
51 | xlnx,apu-udi-0 = <0x0>; | |
52 | xlnx,apu-udi-1 = <0x0>; | |
53 | xlnx,apu-udi-10 = <0x0>; | |
54 | xlnx,apu-udi-11 = <0x0>; | |
55 | xlnx,apu-udi-12 = <0x0>; | |
56 | xlnx,apu-udi-13 = <0x0>; | |
57 | xlnx,apu-udi-14 = <0x0>; | |
58 | xlnx,apu-udi-15 = <0x0>; | |
59 | xlnx,apu-udi-2 = <0x0>; | |
60 | xlnx,apu-udi-3 = <0x0>; | |
61 | xlnx,apu-udi-4 = <0x0>; | |
62 | xlnx,apu-udi-5 = <0x0>; | |
63 | xlnx,apu-udi-6 = <0x0>; | |
64 | xlnx,apu-udi-7 = <0x0>; | |
65 | xlnx,apu-udi-8 = <0x0>; | |
66 | xlnx,apu-udi-9 = <0x0>; | |
67 | xlnx,dcr-autolock-enable = <0x1>; | |
68 | xlnx,dcu-rd-ld-cache-plb-prio = <0x0>; | |
69 | xlnx,dcu-rd-noncache-plb-prio = <0x0>; | |
70 | xlnx,dcu-rd-touch-plb-prio = <0x0>; | |
71 | xlnx,dcu-rd-urgent-plb-prio = <0x0>; | |
72 | xlnx,dcu-wr-flush-plb-prio = <0x0>; | |
73 | xlnx,dcu-wr-store-plb-prio = <0x0>; | |
74 | xlnx,dcu-wr-urgent-plb-prio = <0x0>; | |
75 | xlnx,dma0-control = <0x0>; | |
76 | xlnx,dma0-plb-prio = <0x0>; | |
77 | xlnx,dma0-rxchannelctrl = <0x1010000>; | |
78 | xlnx,dma0-rxirqtimer = <0x3ff>; | |
79 | xlnx,dma0-txchannelctrl = <0x1010000>; | |
80 | xlnx,dma0-txirqtimer = <0x3ff>; | |
81 | xlnx,dma1-control = <0x0>; | |
82 | xlnx,dma1-plb-prio = <0x0>; | |
83 | xlnx,dma1-rxchannelctrl = <0x1010000>; | |
84 | xlnx,dma1-rxirqtimer = <0x3ff>; | |
85 | xlnx,dma1-txchannelctrl = <0x1010000>; | |
86 | xlnx,dma1-txirqtimer = <0x3ff>; | |
87 | xlnx,dma2-control = <0x0>; | |
88 | xlnx,dma2-plb-prio = <0x0>; | |
89 | xlnx,dma2-rxchannelctrl = <0x1010000>; | |
90 | xlnx,dma2-rxirqtimer = <0x3ff>; | |
91 | xlnx,dma2-txchannelctrl = <0x1010000>; | |
92 | xlnx,dma2-txirqtimer = <0x3ff>; | |
93 | xlnx,dma3-control = <0x0>; | |
94 | xlnx,dma3-plb-prio = <0x0>; | |
95 | xlnx,dma3-rxchannelctrl = <0x1010000>; | |
96 | xlnx,dma3-rxirqtimer = <0x3ff>; | |
97 | xlnx,dma3-txchannelctrl = <0x1010000>; | |
98 | xlnx,dma3-txirqtimer = <0x3ff>; | |
99 | xlnx,endian-reset = <0x0>; | |
100 | xlnx,generate-plb-timespecs = <0x1>; | |
101 | xlnx,icu-rd-fetch-plb-prio = <0x0>; | |
102 | xlnx,icu-rd-spec-plb-prio = <0x0>; | |
103 | xlnx,icu-rd-touch-plb-prio = <0x0>; | |
104 | xlnx,interconnect-imask = <0xffffffff>; | |
105 | xlnx,mplb-allow-lock-xfer = <0x1>; | |
106 | xlnx,mplb-arb-mode = <0x0>; | |
107 | xlnx,mplb-awidth = <0x20>; | |
108 | xlnx,mplb-counter = <0x500>; | |
109 | xlnx,mplb-dwidth = <0x80>; | |
110 | xlnx,mplb-max-burst = <0x8>; | |
111 | xlnx,mplb-native-dwidth = <0x80>; | |
112 | xlnx,mplb-p2p = <0x0>; | |
113 | xlnx,mplb-prio-dcur = <0x2>; | |
114 | xlnx,mplb-prio-dcuw = <0x3>; | |
115 | xlnx,mplb-prio-icu = <0x4>; | |
116 | xlnx,mplb-prio-splb0 = <0x1>; | |
117 | xlnx,mplb-prio-splb1 = <0x0>; | |
118 | xlnx,mplb-read-pipe-enable = <0x1>; | |
119 | xlnx,mplb-sync-tattribute = <0x0>; | |
120 | xlnx,mplb-wdog-enable = <0x1>; | |
121 | xlnx,mplb-write-pipe-enable = <0x1>; | |
122 | xlnx,mplb-write-post-enable = <0x1>; | |
123 | xlnx,num-dma = <0x0>; | |
124 | xlnx,pir = <0xf>; | |
125 | xlnx,ppc440mc-addr-base = <0x0>; | |
126 | xlnx,ppc440mc-addr-high = <0x1fffffff>; | |
127 | xlnx,ppc440mc-arb-mode = <0x0>; | |
128 | xlnx,ppc440mc-bank-conflict-mask = <0x1800000>; | |
129 | xlnx,ppc440mc-control = <0xf810008f>; | |
130 | xlnx,ppc440mc-max-burst = <0x8>; | |
131 | xlnx,ppc440mc-prio-dcur = <0x2>; | |
132 | xlnx,ppc440mc-prio-dcuw = <0x3>; | |
133 | xlnx,ppc440mc-prio-icu = <0x4>; | |
134 | xlnx,ppc440mc-prio-splb0 = <0x1>; | |
135 | xlnx,ppc440mc-prio-splb1 = <0x0>; | |
136 | xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>; | |
137 | xlnx,ppcdm-asyncmode = <0x0>; | |
138 | xlnx,ppcds-asyncmode = <0x0>; | |
139 | xlnx,user-reset = <0x0>; | |
140 | } ; | |
141 | } ; | |
142 | plb_v46_0: plb@0 { | |
143 | #address-cells = <1>; | |
144 | #size-cells = <1>; | |
145 | compatible = "xlnx,plb-v46-1.03.a", "simple-bus"; | |
146 | ranges ; | |
147 | FLASH: flash@fc000000 { | |
148 | bank-width = <2>; | |
149 | compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; | |
150 | reg = < 0xfc000000 0x2000000 >; | |
151 | xlnx,family = "virtex5"; | |
152 | xlnx,include-datawidth-matching-0 = <0x1>; | |
153 | xlnx,include-datawidth-matching-1 = <0x0>; | |
154 | xlnx,include-datawidth-matching-2 = <0x0>; | |
155 | xlnx,include-datawidth-matching-3 = <0x0>; | |
156 | xlnx,include-negedge-ioregs = <0x0>; | |
157 | xlnx,include-plb-ipif = <0x1>; | |
158 | xlnx,include-wrbuf = <0x1>; | |
159 | xlnx,max-mem-width = <0x10>; | |
160 | xlnx,mch-native-dwidth = <0x20>; | |
161 | xlnx,mch-plb-clk-period-ps = <0x2710>; | |
162 | xlnx,mch-splb-awidth = <0x20>; | |
163 | xlnx,mch0-accessbuf-depth = <0x10>; | |
164 | xlnx,mch0-protocol = <0x0>; | |
165 | xlnx,mch0-rddatabuf-depth = <0x10>; | |
166 | xlnx,mch1-accessbuf-depth = <0x10>; | |
167 | xlnx,mch1-protocol = <0x0>; | |
168 | xlnx,mch1-rddatabuf-depth = <0x10>; | |
169 | xlnx,mch2-accessbuf-depth = <0x10>; | |
170 | xlnx,mch2-protocol = <0x0>; | |
171 | xlnx,mch2-rddatabuf-depth = <0x10>; | |
172 | xlnx,mch3-accessbuf-depth = <0x10>; | |
173 | xlnx,mch3-protocol = <0x0>; | |
174 | xlnx,mch3-rddatabuf-depth = <0x10>; | |
175 | xlnx,mem0-width = <0x10>; | |
176 | xlnx,mem1-width = <0x20>; | |
177 | xlnx,mem2-width = <0x20>; | |
178 | xlnx,mem3-width = <0x20>; | |
179 | xlnx,num-banks-mem = <0x1>; | |
180 | xlnx,num-channels = <0x2>; | |
181 | xlnx,priority-mode = <0x0>; | |
182 | xlnx,synch-mem-0 = <0x0>; | |
183 | xlnx,synch-mem-1 = <0x0>; | |
184 | xlnx,synch-mem-2 = <0x0>; | |
185 | xlnx,synch-mem-3 = <0x0>; | |
186 | xlnx,synch-pipedelay-0 = <0x2>; | |
187 | xlnx,synch-pipedelay-1 = <0x2>; | |
188 | xlnx,synch-pipedelay-2 = <0x2>; | |
189 | xlnx,synch-pipedelay-3 = <0x2>; | |
190 | xlnx,tavdv-ps-mem-0 = <0x1adb0>; | |
191 | xlnx,tavdv-ps-mem-1 = <0x3a98>; | |
192 | xlnx,tavdv-ps-mem-2 = <0x3a98>; | |
193 | xlnx,tavdv-ps-mem-3 = <0x3a98>; | |
194 | xlnx,tcedv-ps-mem-0 = <0x1adb0>; | |
195 | xlnx,tcedv-ps-mem-1 = <0x3a98>; | |
196 | xlnx,tcedv-ps-mem-2 = <0x3a98>; | |
197 | xlnx,tcedv-ps-mem-3 = <0x3a98>; | |
198 | xlnx,thzce-ps-mem-0 = <0x88b8>; | |
199 | xlnx,thzce-ps-mem-1 = <0x1b58>; | |
200 | xlnx,thzce-ps-mem-2 = <0x1b58>; | |
201 | xlnx,thzce-ps-mem-3 = <0x1b58>; | |
202 | xlnx,thzoe-ps-mem-0 = <0x1b58>; | |
203 | xlnx,thzoe-ps-mem-1 = <0x1b58>; | |
204 | xlnx,thzoe-ps-mem-2 = <0x1b58>; | |
205 | xlnx,thzoe-ps-mem-3 = <0x1b58>; | |
206 | xlnx,tlzwe-ps-mem-0 = <0x88b8>; | |
207 | xlnx,tlzwe-ps-mem-1 = <0x0>; | |
208 | xlnx,tlzwe-ps-mem-2 = <0x0>; | |
209 | xlnx,tlzwe-ps-mem-3 = <0x0>; | |
210 | xlnx,twc-ps-mem-0 = <0x1adb0>; | |
211 | xlnx,twc-ps-mem-1 = <0x3a98>; | |
212 | xlnx,twc-ps-mem-2 = <0x3a98>; | |
213 | xlnx,twc-ps-mem-3 = <0x3a98>; | |
214 | xlnx,twp-ps-mem-0 = <0x11170>; | |
215 | xlnx,twp-ps-mem-1 = <0x2ee0>; | |
216 | xlnx,twp-ps-mem-2 = <0x2ee0>; | |
217 | xlnx,twp-ps-mem-3 = <0x2ee0>; | |
218 | xlnx,xcl0-linesize = <0x4>; | |
219 | xlnx,xcl0-writexfer = <0x1>; | |
220 | xlnx,xcl1-linesize = <0x4>; | |
221 | xlnx,xcl1-writexfer = <0x1>; | |
222 | xlnx,xcl2-linesize = <0x4>; | |
223 | xlnx,xcl2-writexfer = <0x1>; | |
224 | xlnx,xcl3-linesize = <0x4>; | |
225 | xlnx,xcl3-writexfer = <0x1>; | |
226 | } ; | |
227 | Hard_Ethernet_MAC: xps-ll-temac@81c00000 { | |
228 | #address-cells = <1>; | |
229 | #size-cells = <1>; | |
230 | compatible = "xlnx,compound"; | |
231 | ethernet@81c00000 { | |
232 | compatible = "xlnx,xps-ll-temac-1.01.b"; | |
233 | device_type = "network"; | |
234 | interrupt-parent = <&xps_intc_0>; | |
235 | interrupts = < 8 2 >; | |
236 | llink-connected = <&Hard_Ethernet_MAC_fifo>; | |
237 | local-mac-address = [ 02 00 00 00 00 00 ]; | |
238 | reg = < 0x81c00000 0x40 >; | |
239 | xlnx,bus2core-clk-ratio = <0x1>; | |
240 | xlnx,phy-type = <0x3>; | |
241 | xlnx,phyaddr = <0x1>; | |
242 | xlnx,rxcsum = <0x0>; | |
243 | xlnx,rxfifo = <0x8000>; | |
244 | xlnx,temac-type = <0x0>; | |
245 | xlnx,txcsum = <0x0>; | |
246 | xlnx,txfifo = <0x8000>; | |
247 | } ; | |
248 | } ; | |
249 | Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 { | |
250 | compatible = "xlnx,xps-ll-fifo-1.01.a"; | |
251 | interrupt-parent = <&xps_intc_0>; | |
252 | interrupts = < 6 2 >; | |
253 | reg = < 0x81a00000 0x10000 >; | |
254 | xlnx,family = "virtex5"; | |
255 | } ; | |
256 | IIC_EEPROM: i2c@81600000 { | |
257 | compatible = "xlnx,xps-iic-2.00.a"; | |
258 | interrupt-parent = <&xps_intc_0>; | |
259 | interrupts = < 9 2 >; | |
260 | reg = < 0x81600000 0x10000 >; | |
261 | xlnx,clk-freq = <0x5f5e100>; | |
262 | xlnx,family = "virtex5"; | |
263 | xlnx,gpo-width = <0x1>; | |
264 | xlnx,iic-freq = <0x186a0>; | |
265 | xlnx,scl-inertial-delay = <0x5>; | |
266 | xlnx,sda-inertial-delay = <0x5>; | |
267 | xlnx,ten-bit-adr = <0x0>; | |
268 | } ; | |
269 | LCD_OPTIONAL: gpio@81420000 { | |
270 | compatible = "xlnx,xps-gpio-1.00.a"; | |
271 | reg = < 0x81420000 0x10000 >; | |
272 | xlnx,all-inputs = <0x0>; | |
273 | xlnx,all-inputs-2 = <0x0>; | |
274 | xlnx,dout-default = <0x0>; | |
275 | xlnx,dout-default-2 = <0x0>; | |
276 | xlnx,family = "virtex5"; | |
277 | xlnx,gpio-width = <0xb>; | |
278 | xlnx,interrupt-present = <0x0>; | |
279 | xlnx,is-bidir = <0x1>; | |
280 | xlnx,is-bidir-2 = <0x1>; | |
281 | xlnx,is-dual = <0x0>; | |
282 | xlnx,tri-default = <0xffffffff>; | |
283 | xlnx,tri-default-2 = <0xffffffff>; | |
284 | } ; | |
285 | LEDs_4Bit: gpio@81400000 { | |
286 | compatible = "xlnx,xps-gpio-1.00.a"; | |
287 | reg = < 0x81400000 0x10000 >; | |
288 | xlnx,all-inputs = <0x0>; | |
289 | xlnx,all-inputs-2 = <0x0>; | |
290 | xlnx,dout-default = <0x0>; | |
291 | xlnx,dout-default-2 = <0x0>; | |
292 | xlnx,family = "virtex5"; | |
293 | xlnx,gpio-width = <0x4>; | |
294 | xlnx,interrupt-present = <0x0>; | |
295 | xlnx,is-bidir = <0x1>; | |
296 | xlnx,is-bidir-2 = <0x1>; | |
297 | xlnx,is-dual = <0x0>; | |
298 | xlnx,tri-default = <0xffffffff>; | |
299 | xlnx,tri-default-2 = <0xffffffff>; | |
300 | } ; | |
301 | RS232_Uart_1: serial@83e00000 { | |
302 | clock-frequency = <100000000>; | |
303 | compatible = "xlnx,xps-uart16550-2.00.b", "ns16550"; | |
304 | current-speed = <9600>; | |
305 | device_type = "serial"; | |
306 | interrupt-parent = <&xps_intc_0>; | |
307 | interrupts = < 11 2 >; | |
308 | reg = < 0x83e00000 0x10000 >; | |
309 | reg-offset = <0x1003>; | |
310 | reg-shift = <2>; | |
311 | xlnx,family = "virtex5"; | |
312 | xlnx,has-external-rclk = <0x0>; | |
313 | xlnx,has-external-xin = <0x0>; | |
314 | xlnx,is-a-16550 = <0x1>; | |
315 | } ; | |
316 | SPI_EEPROM: xps-spi@feff8000 { | |
317 | compatible = "xlnx,xps-spi-2.00.b"; | |
318 | interrupt-parent = <&xps_intc_0>; | |
319 | interrupts = < 10 2 >; | |
320 | reg = < 0xfeff8000 0x80 >; | |
321 | xlnx,family = "virtex5"; | |
322 | xlnx,fifo-exist = <0x1>; | |
323 | xlnx,num-ss-bits = <0x1>; | |
324 | xlnx,num-transfer-bits = <0x8>; | |
325 | xlnx,sck-ratio = <0x80>; | |
326 | } ; | |
327 | SysACE_CompactFlash: sysace@83600000 { | |
328 | compatible = "xlnx,xps-sysace-1.00.a"; | |
329 | interrupt-parent = <&xps_intc_0>; | |
330 | interrupts = < 7 2 >; | |
331 | reg = < 0x83600000 0x10000 >; | |
332 | xlnx,family = "virtex5"; | |
333 | xlnx,mem-width = <0x10>; | |
334 | } ; | |
335 | plbv46_pci_0: plbv46-pci@85e00000 { | |
336 | #size-cells = <2>; | |
337 | #address-cells = <3>; | |
338 | compatible = "xlnx,plbv46-pci-1.03.a"; | |
339 | device_type = "pci"; | |
340 | reg = < 0x85e00000 0x10000 >; | |
341 | ||
342 | /* | |
343 | * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to | |
344 | * 0 which means that a read/write to the memory mapped | |
345 | * i/o region (which starts at 0xa0000000) for pci | |
346 | * bar 0 on the plb side translates to 0. | |
347 | * It is important to set this value to 0xa0000000, so | |
348 | * that inbound and outbound pci transactions work | |
349 | * properly including DMA. | |
350 | */ | |
351 | ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 | |
352 | 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>; | |
353 | ||
354 | #interrupt-cells = <1>; | |
355 | interrupt-parent = <&xps_intc_0>; | |
356 | interrupt-map-mask = <0xff00 0x0 0x0 0x7>; | |
357 | interrupt-map = < | |
358 | /* IRQ mapping for pci slots and ALI M1533 | |
359 | * periperhals. In total there are 5 interrupt | |
360 | * lines connected to a xps_intc controller. | |
361 | * Four of them are PCI IRQ A, B, C, D and | |
362 | * which correspond to respectively xpx_intc | |
363 | * 5, 4, 3 and 2. The fifth interrupt line is | |
364 | * connected to the south bridge and this one | |
365 | * uses irq 1 and is active high instead of | |
366 | * active low. | |
367 | * | |
368 | * The M1533 contains various peripherals | |
369 | * including AC97 audio, a modem, USB, IDE and | |
370 | * some power management stuff. The modem | |
371 | * isn't connected on the ML510 and the power | |
372 | * management core also isn't used. | |
373 | */ | |
374 | ||
375 | /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */ | |
376 | 0x3000 0 0 1 &xps_intc_0 3 2 | |
377 | 0x3000 0 0 2 &xps_intc_0 2 2 | |
378 | 0x3000 0 0 3 &xps_intc_0 5 2 | |
379 | 0x3000 0 0 4 &xps_intc_0 4 2 | |
380 | ||
381 | /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */ | |
382 | /* | |
383 | 0x11800 0 0 1 &xps_intc_0 5 0 2 | |
384 | 0x11800 0 0 2 &xps_intc_0 4 0 2 | |
385 | 0x11800 0 0 3 &xps_intc_0 3 0 2 | |
386 | 0x11800 0 0 4 &xps_intc_0 2 0 2 | |
387 | */ | |
388 | ||
389 | /* According to the datasheet + schematic | |
390 | * ABCD [FPGA] of slot 5 is mapped to DABC. | |
391 | * Testing showed that at least A maps to B, | |
392 | * the mapping of the other pins is a guess | |
393 | * and for that reason the lines have been | |
394 | * commented out. | |
395 | */ | |
396 | /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */ | |
397 | 0x2800 0 0 1 &xps_intc_0 4 2 | |
398 | /* | |
399 | 0x2800 0 0 2 &xps_intc_0 3 2 | |
400 | 0x2800 0 0 3 &xps_intc_0 2 2 | |
401 | 0x2800 0 0 4 &xps_intc_0 5 2 | |
402 | */ | |
403 | ||
404 | /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */ | |
405 | /* | |
406 | 0x11000 0 0 1 &xps_intc_0 4 0 2 | |
407 | 0x11000 0 0 2 &xps_intc_0 3 0 2 | |
408 | 0x11000 0 0 3 &xps_intc_0 2 0 2 | |
409 | 0x11000 0 0 4 &xps_intc_0 5 0 2 | |
410 | */ | |
411 | ||
412 | /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */ | |
413 | 0x0800 0 0 1 &i8259 7 2 | |
414 | ||
415 | /* IDSEL 0x1b / dev=11, bus=0 / IDE */ | |
416 | 0x5800 0 0 1 &i8259 14 2 | |
417 | ||
418 | /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */ | |
419 | 0x7800 0 0 1 &i8259 7 2 | |
420 | >; | |
421 | ali_m1533 { | |
422 | #size-cells = <1>; | |
423 | #address-cells = <2>; | |
424 | i8259: interrupt-controller@20 { | |
425 | reg = <1 0x20 2 | |
426 | 1 0xa0 2 | |
427 | 1 0x4d0 2>; | |
428 | interrupt-controller; | |
429 | device_type = "interrupt-controller"; | |
430 | #address-cells = <0>; | |
431 | #interrupt-cells = <2>; | |
432 | compatible = "chrp,iic"; | |
433 | ||
434 | /* south bridge irq is active high */ | |
435 | interrupts = <1 3>; | |
436 | interrupt-parent = <&xps_intc_0>; | |
437 | }; | |
438 | }; | |
439 | } ; | |
440 | xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 { | |
441 | compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; | |
442 | reg = < 0xffff0000 0x10000 >; | |
443 | xlnx,family = "virtex5"; | |
444 | } ; | |
445 | xps_intc_0: interrupt-controller@81800000 { | |
446 | #interrupt-cells = <0x2>; | |
447 | compatible = "xlnx,xps-intc-1.00.a"; | |
448 | interrupt-controller ; | |
449 | reg = < 0x81800000 0x10000 >; | |
450 | xlnx,num-intr-inputs = <0xc>; | |
451 | } ; | |
452 | xps_tft_0: tft@86e00000 { | |
453 | compatible = "xlnx,xps-tft-1.00.a"; | |
454 | reg = < 0x86e00000 0x10000 >; | |
455 | xlnx,dcr-splb-slave-if = <0x1>; | |
456 | xlnx,default-tft-base-addr = <0x0>; | |
457 | xlnx,family = "virtex5"; | |
458 | xlnx,i2c-slave-addr = <0x76>; | |
459 | xlnx,mplb-awidth = <0x20>; | |
460 | xlnx,mplb-dwidth = <0x80>; | |
461 | xlnx,mplb-native-dwidth = <0x40>; | |
462 | xlnx,mplb-smallest-slave = <0x20>; | |
463 | xlnx,tft-interface = <0x1>; | |
464 | } ; | |
465 | } ; | |
466 | } ; |