]> git.ipfire.org Git - thirdparty/u-boot.git/blame - arch/powerpc/cpu/mpc512x/cpu.c
Add GPL-2.0+ SPDX-License-Identifier to source files
[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc512x / cpu.c
CommitLineData
8993e54b 1/*
57ae8a5c 2 * (C) Copyright 2007-2010 DENX Software Engineering
8993e54b 3 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
8993e54b 4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
8993e54b
RJ
6 */
7
8/*
9 * CPU specific code for the MPC512x family.
10 *
11 * Derived from the MPC83xx code.
12 */
13
14#include <common.h>
15#include <command.h>
76756e41 16#include <net.h>
a0aad08f 17#include <netdev.h>
8993e54b 18#include <asm/processor.h>
57ae8a5c 19#include <asm/io.h>
8993e54b 20
281ff9a4
GB
21#if defined(CONFIG_OF_LIBFDT)
22#include <fdt_support.h>
23#endif
24
8993e54b
RJ
25DECLARE_GLOBAL_DATA_PTR;
26
27int checkcpu (void)
28{
6d0f6bcf 29 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
8993e54b
RJ
30 ulong clock = gd->cpu_clk;
31 u32 pvr = get_pvr ();
57ae8a5c 32 u32 spridr = in_be32(&immr->sysconf.spridr);
08ef89ec 33 char buf1[32], buf2[32];
8993e54b 34
77d19a8b 35 puts ("CPU: ");
8993e54b
RJ
36
37 switch (spridr & 0xffff0000) {
38 case SPR_5121E:
39 puts ("MPC5121e ");
40 break;
41 default:
42 printf ("Unknown part ID %08x ", spridr & 0xffff0000);
43 }
44 printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
45
46 switch (pvr & 0xffff0000) {
47 case PVR_E300C4:
48 puts ("e300c4 ");
49 break;
50 default:
51 puts ("unknown ");
52 }
82826d54 53 printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
08ef89ec 54 strmhz(buf1, clock),
fefb098b 55 strmhz(buf2, gd->arch.csb_clk),
3c4c308c 56 gd->arch.reset_status & 0xffff);
8993e54b
RJ
57 return 0;
58}
59
60
61int
54841ab5 62do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
8993e54b
RJ
63{
64 ulong msr;
6d0f6bcf 65 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
8993e54b
RJ
66
67 /* Interrupts and MMU off */
68 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
69
70 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
71 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
72
73 /*
74 * Enable Reset Control Reg - "RSTE" is the magic word that let us go
75 */
57ae8a5c 76 out_be32(&immap->reset.rpr, 0x52535445);
8993e54b
RJ
77
78 /* Verify Reset Control Reg is enabled */
57ae8a5c 79 while (!(in_be32(&immap->reset.rcer) & RCER_CRE))
8993e54b
RJ
80 ;
81
82 printf ("Resetting the board.\n");
83 udelay(200);
84
85 /* Perform reset */
57ae8a5c 86 out_be32(&immap->reset.rcr, RCR_SWHR);
8993e54b
RJ
87
88 /* Unreached... */
89 return 1;
90}
91
92
93/*
94 * Get timebase clock frequency (like cpu_clk in Hz)
95 */
96unsigned long get_tbclk (void)
97{
98 ulong tbclk;
99
100 tbclk = (gd->bus_clk + 3L) / 4L;
101
102 return tbclk;
103}
104
105
106#if defined(CONFIG_WATCHDOG)
107void watchdog_reset (void)
108{
109 int re_enable = disable_interrupts ();
110
111 /* Reset watchdog */
6d0f6bcf 112 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
57ae8a5c
DZ
113 out_be32(&immr->wdt.swsrr, 0x556c);
114 out_be32(&immr->wdt.swsrr, 0xaa39);
8993e54b
RJ
115
116 if (re_enable)
117 enable_interrupts ();
118}
119#endif
281ff9a4
GB
120
121#ifdef CONFIG_OF_LIBFDT
ef11df6b
JR
122
123#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
124/*
125 * fdt setup for old device trees
126 * fix up
127 * cpu clocks
128 * soc clocks
129 * ethernet addresses
130 */
131static void old_ft_cpu_setup(void *blob, bd_t *bd)
132{
133 /*
134 * avoid fixing up by path because that
135 * produces scary error messages
136 */
6bacfa6a 137 uchar enetaddr[6];
ef11df6b
JR
138
139 /*
140 * old device trees have ethernet nodes with
141 * device_type = "network"
142 */
6bacfa6a 143 eth_getenv_enetaddr("ethaddr", enetaddr);
ef11df6b 144 do_fixup_by_prop(blob, "device_type", "network", 8,
6bacfa6a 145 "local-mac-address", enetaddr, 6, 0);
ef11df6b 146 do_fixup_by_prop(blob, "device_type", "network", 8,
6bacfa6a 147 "address", enetaddr, 6, 0);
ef11df6b
JR
148 /*
149 * old device trees have soc nodes with
150 * device_type = "soc"
151 */
152 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
153 "bus-frequency", bd->bi_ipsfreq, 0);
154}
155#endif
156
157static void ft_clock_setup(void *blob, bd_t *bd)
281ff9a4 158{
f31c49db 159 char *cpu_path = "/cpus/" OF_CPU;
ef11df6b
JR
160
161 /*
162 * fixup cpu clocks using path
163 */
164 do_fixup_by_path_u32(blob, cpu_path,
165 "timebase-frequency", OF_TBCLK, 1);
166 do_fixup_by_path_u32(blob, cpu_path,
167 "bus-frequency", bd->bi_busfreq, 1);
168 do_fixup_by_path_u32(blob, cpu_path,
169 "clock-frequency", bd->bi_intfreq, 1);
170 /*
171 * fixup soc clocks using compatible
172 */
173 do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
174 "bus-frequency", bd->bi_ipsfreq, 1);
175}
176
177void ft_cpu_setup(void *blob, bd_t *bd)
178{
179#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
180 old_ft_cpu_setup(blob, bd);
181#endif
182 ft_clock_setup(blob, bd);
183#ifdef CONFIG_HAS_ETH0
ba37aa03 184 fdt_fixup_ethernet(blob);
ef11df6b 185#endif
00b6d927 186 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
281ff9a4
GB
187}
188#endif
a0aad08f
BW
189
190#ifdef CONFIG_MPC512x_FEC
191/* Default initializations for FEC controllers. To override,
192 * create a board-specific function called:
193 * int board_eth_init(bd_t *bis)
194 */
195
196int cpu_eth_init(bd_t *bis)
197{
198 return mpc512x_fec_initialize(bis);
199}
200#endif