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1 | /* |
2 | * (C) Copyright 2007-2009 DENX Software Engineering | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <command.h> | |
843efb11 | 26 | #include <asm/io.h> |
de26ef99 WD |
27 | #include <asm/processor.h> |
28 | ||
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | #if defined(CONFIG_IDE_RESET) | |
32 | ||
843efb11 WD |
33 | void ide_set_reset (int idereset) |
34 | { | |
35 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; | |
36 | debug ("ide_set_reset(%d)\n", idereset); | |
37 | ||
38 | if (idereset) { | |
39 | out_be32(&im->pata.pata_ata_control, 0); | |
40 | } else { | |
41 | out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B); | |
42 | } | |
43 | udelay(100); | |
44 | } | |
45 | ||
de26ef99 WD |
46 | void init_ide_reset (void) |
47 | { | |
de26ef99 WD |
48 | debug ("init_ide_reset\n"); |
49 | ||
50 | /* | |
51 | * Clear the reset bit to reset the interface | |
52 | * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus | |
53 | */ | |
843efb11 | 54 | ide_set_reset(1); |
de26ef99 | 55 | |
843efb11 WD |
56 | /* Assert the reset bit to enable the interface */ |
57 | ide_set_reset(0); | |
de26ef99 | 58 | |
de26ef99 WD |
59 | } |
60 | ||
61 | #define CALC_TIMING(t) (t + period - 1) / period | |
62 | ||
63 | int ide_preinit (void) | |
64 | { | |
843efb11 | 65 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
de26ef99 WD |
66 | long t; |
67 | const struct { | |
68 | short t0; | |
69 | short t1; | |
70 | short t2_8; | |
71 | short t2_16; | |
72 | short t2i; | |
73 | short t4; | |
74 | short t9; | |
75 | short tA; | |
76 | } pio_specs = { | |
77 | .t0 = 600, | |
78 | .t1 = 70, | |
79 | .t2_8 = 290, | |
80 | .t2_16 = 165, | |
81 | .t2i = 0, | |
82 | .t4 = 30, | |
83 | .t9 = 20, | |
84 | .tA = 50, | |
85 | }; | |
86 | union { | |
87 | u32 config; | |
88 | struct { | |
89 | u8 field1; | |
90 | u8 field2; | |
91 | u8 field3; | |
92 | u8 field4; | |
93 | }bytes; | |
843efb11 | 94 | } cfg; |
de26ef99 WD |
95 | |
96 | debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n", | |
843efb11 | 97 | (u32)&im->pata); |
de26ef99 WD |
98 | |
99 | /* Set the reset bit to 1 to enable the interface */ | |
843efb11 | 100 | ide_set_reset(0); |
de26ef99 WD |
101 | |
102 | /* Init timings : we use PIO mode 0 timings */ | |
103 | t = 1000000000 / gd->ips_clk; /* period in ns */ | |
104 | cfg.bytes.field1 = 3; | |
105 | cfg.bytes.field2 = 3; | |
106 | cfg.bytes.field3 = (pio_specs.t1 + t) / t; | |
107 | cfg.bytes.field4 = (pio_specs.t2_8 + t) / t; | |
108 | ||
843efb11 | 109 | out_be32(&im->pata.pata_time1, cfg.config); |
de26ef99 WD |
110 | |
111 | cfg.bytes.field1 = (pio_specs.t2_8 + t) / t; | |
112 | cfg.bytes.field2 = (pio_specs.tA + t) / t + 2; | |
113 | cfg.bytes.field3 = 1; | |
114 | cfg.bytes.field4 = (pio_specs.t4 + t) / t; | |
115 | ||
843efb11 | 116 | out_be32(&im->pata.pata_time2, cfg.config); |
de26ef99 | 117 | |
843efb11 | 118 | cfg.config = in_be32(&im->pata.pata_time3); |
de26ef99 WD |
119 | cfg.bytes.field1 = (pio_specs.t9 + t) / t; |
120 | ||
843efb11 WD |
121 | out_be32(&im->pata.pata_time3, cfg.config); |
122 | ||
de26ef99 WD |
123 | debug ("PATA preinit complete.\n"); |
124 | ||
125 | return 0; | |
126 | } | |
127 | ||
128 | #endif /* defined(CONFIG_IDE_RESET) */ |