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0db5bca8 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Martin Winistoerfer, martinwinistoerfer@gmx.ch. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0db5bca8 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * File: cpu.c | |
8bde7f77 WD |
10 | * |
11 | * Discription: Some cpu specific function for watchdog, | |
0db5bca8 | 12 | * cpu version test, clock setting ... |
8bde7f77 | 13 | * |
0db5bca8 WD |
14 | */ |
15 | ||
16 | ||
17 | #include <common.h> | |
18 | #include <watchdog.h> | |
19 | #include <command.h> | |
20 | #include <mpc5xx.h> | |
21 | ||
d87080b7 | 22 | DECLARE_GLOBAL_DATA_PTR; |
0db5bca8 WD |
23 | |
24 | #if (defined(CONFIG_MPC555)) | |
25 | # define ID_STR "MPC555/556" | |
26 | ||
27 | /* | |
28 | * Check version of cpu with Processor Version Register (PVR) | |
29 | */ | |
30 | static int check_cpu_version (long clock, uint pvr, uint immr) | |
31 | { | |
32 | char buf[32]; | |
33 | /* The highest 16 bits should be 0x0002 for a MPC555/556 */ | |
34 | if ((pvr >> 16) == 0x0002) { | |
35 | printf (" " ID_STR " Version %x", (pvr >> 16)); | |
36 | printf (" at %s MHz:", strmhz (buf, clock)); | |
37 | } else { | |
38 | printf ("Not supported cpu version"); | |
39 | return -1; | |
40 | } | |
41 | return 0; | |
42 | } | |
43 | #endif /* CONFIG_MPC555 */ | |
44 | ||
45 | ||
46 | /* | |
47 | * Check version of mpc5xx | |
48 | */ | |
49 | int checkcpu (void) | |
50 | { | |
0db5bca8 WD |
51 | ulong clock = gd->cpu_clk; |
52 | uint immr = get_immr (0); /* Return full IMMR contents */ | |
53 | uint pvr = get_pvr (); /* Retrieve PVR register */ | |
54 | ||
55 | puts ("CPU: "); | |
56 | ||
57 | return check_cpu_version (clock, pvr, immr); | |
58 | } | |
59 | ||
60 | /* | |
8bde7f77 | 61 | * Called by macro WATCHDOG_RESET |
0db5bca8 WD |
62 | */ |
63 | #if defined(CONFIG_WATCHDOG) | |
64 | void watchdog_reset (void) | |
65 | { | |
66 | int re_enable = disable_interrupts (); | |
67 | ||
6d0f6bcf | 68 | reset_5xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); |
0db5bca8 WD |
69 | if (re_enable) |
70 | enable_interrupts (); | |
71 | } | |
72 | ||
73 | /* | |
74 | * Will clear software reset | |
75 | */ | |
76 | void reset_5xx_watchdog (volatile immap_t * immr) | |
77 | { | |
78 | /* Use the MPC5xx Internal Watchdog */ | |
79 | immr->im_siu_conf.sc_swsr = 0x556c; /* Prevent SW time-out */ | |
8bde7f77 | 80 | immr->im_siu_conf.sc_swsr = 0xaa39; |
0db5bca8 WD |
81 | } |
82 | ||
83 | #endif /* CONFIG_WATCHDOG */ | |
84 | ||
85 | ||
86 | /* | |
87 | * Get timebase clock frequency | |
88 | */ | |
89 | unsigned long get_tbclk (void) | |
90 | { | |
6d0f6bcf | 91 | volatile immap_t *immr = (volatile immap_t *) CONFIG_SYS_IMMR; |
0db5bca8 WD |
92 | ulong oscclk, factor; |
93 | ||
94 | if (immr->im_clkrst.car_sccr & SCCR_TBS) { | |
95 | return (gd->cpu_clk / 16); | |
96 | } | |
97 | ||
6d0f6bcf | 98 | factor = (((CONFIG_SYS_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; |
0db5bca8 WD |
99 | |
100 | oscclk = gd->cpu_clk / factor; | |
101 | ||
102 | if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { | |
103 | return (oscclk / 4); | |
104 | } | |
105 | return (oscclk / 16); | |
106 | } | |
107 | ||
b6e4c403 WD |
108 | void dcache_enable (void) |
109 | { | |
110 | return; | |
111 | } | |
112 | ||
113 | void dcache_disable (void) | |
114 | { | |
115 | return; | |
116 | } | |
117 | ||
118 | int dcache_status (void) | |
119 | { | |
120 | return 0; /* always off */ | |
121 | } | |
0db5bca8 WD |
122 | |
123 | /* | |
8bde7f77 | 124 | * Reset board |
0db5bca8 | 125 | */ |
54841ab5 | 126 | int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
0db5bca8 | 127 | { |
b6e4c403 | 128 | #if defined(CONFIG_PATI) |
6d0f6bcf | 129 | volatile ulong *addr = (ulong *) CONFIG_SYS_RESET_ADDRESS; |
b6e4c403 WD |
130 | *addr = 1; |
131 | #else | |
0db5bca8 | 132 | ulong addr; |
8bde7f77 | 133 | |
0db5bca8 | 134 | /* Interrupts off, enable reset */ |
8bde7f77 | 135 | __asm__ volatile (" mtspr 81, %r0 \n\t" |
cceb871f WD |
136 | " mfmsr %r3 \n\t" |
137 | " rlwinm %r31,%r3,0,25,23\n\t" | |
138 | " mtmsr %r31 \n\t"); | |
8bde7f77 WD |
139 | /* |
140 | * Trying to execute the next instruction at a non-existing address | |
141 | * should cause a machine check, resulting in reset | |
142 | */ | |
6d0f6bcf JCPV |
143 | #ifdef CONFIG_SYS_RESET_ADDRESS |
144 | addr = CONFIG_SYS_RESET_ADDRESS; | |
0db5bca8 | 145 | #else |
8bde7f77 | 146 | /* |
6d0f6bcf JCPV |
147 | * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address |
148 | * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. | |
8bde7f77 WD |
149 | * "(ulong)-1" used to be a good choice for many systems... |
150 | */ | |
6d0f6bcf | 151 | addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); |
0db5bca8 WD |
152 | #endif |
153 | ((void (*) (void)) addr) (); | |
b6e4c403 | 154 | #endif /* #if defined(CONFIG_PATI) */ |
0db5bca8 WD |
155 | return 1; |
156 | } |