[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc5xxx / cpu_init.c

/*
 * (C) Copyright 2000-2010
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc5xxx.h>
#include <asm/io.h>
#include <watchdog.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers.
 */
void cpu_init_f (void)
{
	volatile struct mpc5xxx_mmap_ctl *mm =
		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	volatile struct mpc5xxx_lpb *lpb =
		(struct mpc5xxx_lpb *) MPC5XXX_LPB;
	volatile struct mpc5xxx_gpio *gpio =
		(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
	volatile struct mpc5xxx_xlb *xlb =
		(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
	volatile struct mpc5xxx_cdm *cdm =
		(struct mpc5xxx_cdm *) MPC5XXX_CDM;
#endif	/* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
#if defined(CONFIG_WATCHDOG)
	volatile struct mpc5xxx_gpt *gpt0 =
		(struct mpc5xxx_gpt *) MPC5XXX_GPT;
#endif /* CONFIG_WATCHDOG */
	unsigned long addecr = (1 << 25); /* Boot_CS */
	/* Pointer is writable since we allocated a register for it */
	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);

	/* Clear initial global data */
	memset ((void *) gd, 0, sizeof (gd_t));

	/*
	 * Memory Controller: configure chip selects and enable them
	 */
#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
	out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
	out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
					  CONFIG_SYS_BOOTCS_SIZE));
#endif
#if defined(CONFIG_SYS_BOOTCS_CFG)
	out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
#endif

#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
	out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
	out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
					 CONFIG_SYS_CS0_SIZE));
	/* CS0 and BOOT_CS cannot be enabled at once. */
	/*	addecr |= (1 << 16); */
#endif
#if defined(CONFIG_SYS_CS0_CFG)
	out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
#endif

#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
	out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
	out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
					 CONFIG_SYS_CS1_SIZE));
	addecr |= (1 << 17);
#endif
#if defined(CONFIG_SYS_CS1_CFG)
	out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
#endif

#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
	out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
	out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
					 CONFIG_SYS_CS2_SIZE));
	addecr |= (1 << 18);
#endif
#if defined(CONFIG_SYS_CS2_CFG)
	out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
#endif

#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
	out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
	out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
					 CONFIG_SYS_CS3_SIZE));
	addecr |= (1 << 19);
#endif
#if defined(CONFIG_SYS_CS3_CFG)
	out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
#endif

#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
	out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
	out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
					  CONFIG_SYS_CS4_SIZE));
	addecr |= (1 << 20);
#endif
#if defined(CONFIG_SYS_CS4_CFG)
	out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
#endif

#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
	out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
	out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
					  CONFIG_SYS_CS5_SIZE));
	addecr |= (1 << 21);
#endif
#if defined(CONFIG_SYS_CS5_CFG)
	out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
#endif

	addecr |= 1;
#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
	out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
	out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
					  CONFIG_SYS_CS6_SIZE));
	addecr |= (1 << 26);
#endif
#if defined(CONFIG_SYS_CS6_CFG)
	out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
#endif

#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
	out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
	out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
					  CONFIG_SYS_CS7_SIZE));
	addecr |= (1 << 27);
#endif
#if defined(CONFIG_SYS_CS7_CFG)
	out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
#endif

#if defined(CONFIG_SYS_CS_BURST)
	out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
#endif
#if defined(CONFIG_SYS_CS_DEADCYCLE)
	out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
#endif

	/* Enable chip selects */
	out_be32(&mm->ipbi_ws_ctrl, addecr);
	out_be32(&lpb->cs_ctrl, (1 << 24));

	/* Setup pin multiplexing */
#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
	out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
#endif

	/* Setup gpios */
#if defined(CONFIG_SYS_GPIO_DATADIR)
	out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR);
#endif
#if defined(CONFIG_SYS_GPIO_OPENDRAIN)
	out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN);
#endif
#if defined(CONFIG_SYS_GPIO_DATAVALUE)
	out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE);
#endif
#if defined(CONFIG_SYS_GPIO_ENABLE)
	out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE);
#endif

	/* enable timebase */
	setbits_be32(&xlb->config, (1 << 13));

	/* Enable snooping for RAM */
	setbits_be32(&xlb->config, (1 << 15));
	out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);

#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
	/* Motorola reports IPB should better run at 133 MHz. */
	setbits_be32(&mm->ipbi_ws_ctrl, 1);
	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
	addecr = in_be32(&cdm->cfg);
	addecr &= ~0x103;
# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
	/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
	addecr |= 0x01;
# else
	/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
	addecr |= 0x02;
# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
	out_be32(&cdm->cfg, addecr);
#endif	/* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
	/* Configure the XLB Arbiter */
	out_be32(&xlb->master_pri_enable, 0xff);
	out_be32(&xlb->master_priority, 0x11111111);

#if defined(CONFIG_SYS_XLB_PIPELINING)
	/* Enable piplining */
	clrbits_be32(&xlb->config, (1 << 31));
#endif

#if defined(CONFIG_WATCHDOG)
	/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
	out_be32(&gpt0->cir, 0x0000ffff);
	out_be32(&gpt0->emsr, 0x9004);	/* wden|ce|timer_ms */

	reset_5xxx_watchdog();
#endif /* CONFIG_WATCHDOG */
}

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
	volatile struct mpc5xxx_intr *intr =
		(struct mpc5xxx_intr *) MPC5XXX_ICTL;

	/* mask all interrupts */
	out_be32(&intr->per_mask, 0xffffff00);
	setbits_be32(&intr->main_mask, 0x0001ffff);
	clrbits_be32(&intr->ctrl, 0x00000f00);
	/* route critical ints to normal ints */
	setbits_be32(&intr->ctrl, 0x00000001);

#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
	/* load FEC microcode */
	loadtask(0, 2);
#endif

	return (0);
}
Commit	Line	Data
945af8d7	1	/*
a21fb981	2	* (C) Copyright 2000-2010
945af8d7 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
945af8d7 WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
945af8d7 WD	6	*/
	7
	8	#include <common.h>
	9	#include <mpc5xxx.h>
0f597bc2	10	#include <asm/io.h>
a21fb981	11	#include <watchdog.h>
945af8d7	12
d87080b7 WD	13	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	14
945af8d7 WD	15	/*
	16	* Breath some life into the CPU...
	17	*
	18	* Set up the memory map,
	19	* initialize a bunch of registers.
	20	*/
	21	void cpu_init_f (void)
	22	{
0f597bc2 DZ	23	volatile struct mpc5xxx_mmap_ctl *mm =
	24	(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	25	volatile struct mpc5xxx_lpb *lpb =
	26	(struct mpc5xxx_lpb *) MPC5XXX_LPB;
0f597bc2 DZ	27	volatile struct mpc5xxx_gpio *gpio =
	28	(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
	29	volatile struct mpc5xxx_xlb *xlb =
	30	(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
9461a939 WD	31	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
	32	volatile struct mpc5xxx_cdm *cdm =
	33	(struct mpc5xxx_cdm *) MPC5XXX_CDM;
	34	#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
13d8bfe2	35	#if defined(CONFIG_WATCHDOG)
a21fb981 DZ	36	volatile struct mpc5xxx_gpt *gpt0 =
a21fb981 DZ	37	(struct mpc5xxx_gpt *) MPC5XXX_GPT;
13d8bfe2	38	#endif /* CONFIG_WATCHDOG */
945af8d7	39	unsigned long addecr = (1 << 25); /* Boot_CS */
945af8d7	40	/* Pointer is writable since we allocated a register for it */
6d0f6bcf	41	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
945af8d7 WD	42
	43	/* Clear initial global data */
	44	memset ((void *) gd, 0, sizeof (gd_t));
	45
	46	/*
	47	* Memory Controller: configure chip selects and enable them
	48	*/
6d0f6bcf	49	#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
0f597bc2 DZ	50	out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
	51	out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
	52	CONFIG_SYS_BOOTCS_SIZE));
945af8d7	53	#endif
6d0f6bcf	54	#if defined(CONFIG_SYS_BOOTCS_CFG)
0f597bc2	55	out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
945af8d7 WD	56	#endif
945af8d7 WD	57
6d0f6bcf	58	#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
0f597bc2 DZ	59	out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
	60	out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
	61	CONFIG_SYS_CS0_SIZE));
945af8d7 WD	62	/* CS0 and BOOT_CS cannot be enabled at once. */
	63	/* addecr \|= (1 << 16); */
	64	#endif
6d0f6bcf	65	#if defined(CONFIG_SYS_CS0_CFG)
0f597bc2	66	out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
945af8d7 WD	67	#endif
945af8d7 WD	68
6d0f6bcf	69	#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
0f597bc2 DZ	70	out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
	71	out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
	72	CONFIG_SYS_CS1_SIZE));
945af8d7 WD	73	addecr \|= (1 << 17);
945af8d7 WD	74	#endif
6d0f6bcf	75	#if defined(CONFIG_SYS_CS1_CFG)
0f597bc2	76	out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
945af8d7 WD	77	#endif
945af8d7 WD	78
6d0f6bcf	79	#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
0f597bc2 DZ	80	out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
	81	out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
	82	CONFIG_SYS_CS2_SIZE));
945af8d7 WD	83	addecr \|= (1 << 18);
945af8d7 WD	84	#endif
6d0f6bcf	85	#if defined(CONFIG_SYS_CS2_CFG)
0f597bc2	86	out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
945af8d7 WD	87	#endif
945af8d7 WD	88
6d0f6bcf	89	#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
0f597bc2 DZ	90	out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
	91	out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
	92	CONFIG_SYS_CS3_SIZE));
945af8d7 WD	93	addecr \|= (1 << 19);
945af8d7 WD	94	#endif
6d0f6bcf	95	#if defined(CONFIG_SYS_CS3_CFG)
0f597bc2	96	out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
945af8d7 WD	97	#endif
945af8d7 WD	98
6d0f6bcf	99	#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
0f597bc2 DZ	100	out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
	101	out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
	102	CONFIG_SYS_CS4_SIZE));
945af8d7 WD	103	addecr \|= (1 << 20);
945af8d7 WD	104	#endif
6d0f6bcf	105	#if defined(CONFIG_SYS_CS4_CFG)
0f597bc2	106	out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
945af8d7 WD	107	#endif
945af8d7 WD	108
6d0f6bcf	109	#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
0f597bc2 DZ	110	out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
	111	out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
	112	CONFIG_SYS_CS5_SIZE));
945af8d7 WD	113	addecr \|= (1 << 21);
945af8d7 WD	114	#endif
6d0f6bcf	115	#if defined(CONFIG_SYS_CS5_CFG)
0f597bc2	116	out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
945af8d7 WD	117	#endif
945af8d7 WD	118
945af8d7	119	addecr \|= 1;
6d0f6bcf	120	#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
0f597bc2 DZ	121	out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
	122	out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
	123	CONFIG_SYS_CS6_SIZE));
945af8d7 WD	124	addecr \|= (1 << 26);
945af8d7 WD	125	#endif
6d0f6bcf	126	#if defined(CONFIG_SYS_CS6_CFG)
0f597bc2	127	out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
945af8d7 WD	128	#endif
945af8d7 WD	129
6d0f6bcf	130	#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
0f597bc2 DZ	131	out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
	132	out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
	133	CONFIG_SYS_CS7_SIZE));
945af8d7 WD	134	addecr \|= (1 << 27);
945af8d7 WD	135	#endif
6d0f6bcf	136	#if defined(CONFIG_SYS_CS7_CFG)
0f597bc2	137	out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
945af8d7 WD	138	#endif
945af8d7 WD	139
6d0f6bcf	140	#if defined(CONFIG_SYS_CS_BURST)
0f597bc2	141	out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
945af8d7	142	#endif
6d0f6bcf	143	#if defined(CONFIG_SYS_CS_DEADCYCLE)
0f597bc2	144	out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
945af8d7	145	#endif
945af8d7 WD	146
945af8d7 WD	147	/* Enable chip selects */
0f597bc2	148	out_be32(&mm->ipbi_ws_ctrl, addecr);
0f597bc2	149	out_be32(&lpb->cs_ctrl, (1 << 24));
945af8d7 WD	150
945af8d7 WD	151	/* Setup pin multiplexing */
6d0f6bcf	152	#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
0f597bc2	153	out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
945af8d7	154	#endif
96dd9af4	155
d7903ae1 AG	156	/* Setup gpios */
	157	#if defined(CONFIG_SYS_GPIO_DATADIR)
	158	out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR);
	159	#endif
	160	#if defined(CONFIG_SYS_GPIO_OPENDRAIN)
	161	out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN);
	162	#endif
	163	#if defined(CONFIG_SYS_GPIO_DATAVALUE)
	164	out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE);
	165	#endif
	166	#if defined(CONFIG_SYS_GPIO_ENABLE)
	167	out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE);
	168	#endif
	169
96dd9af4	170	/* enable timebase */
0f597bc2	171	setbits_be32(&xlb->config, (1 << 13));
7152b1d0	172
8419c013	173	/* Enable snooping for RAM */
0f597bc2 DZ	174	setbits_be32(&xlb->config, (1 << 15));
0f597bc2 DZ	175	out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE \| 0x1d);
8419c013	176
fd428c05	177	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
7152b1d0	178	/* Motorola reports IPB should better run at 133 MHz. */
0f597bc2	179	setbits_be32(&mm->ipbi_ws_ctrl, 1);
7152b1d0	180	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
0f597bc2	181	addecr = in_be32(&cdm->cfg);
7152b1d0	182	addecr &= ~0x103;
fd428c05	183	# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
56523f12 WD	184	/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
56523f12 WD	185	addecr \|= 0x01;
fd428c05	186	# else
56523f12	187	/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
7152b1d0	188	addecr \|= 0x02;
fd428c05	189	# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
0f597bc2	190	out_be32(&cdm->cfg, addecr);
fd428c05	191	#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
4aeb251f	192	/* Configure the XLB Arbiter */
0f597bc2 DZ	193	out_be32(&xlb->master_pri_enable, 0xff);
0f597bc2 DZ	194	out_be32(&xlb->master_priority, 0x11111111);
e1599e83	195
fd428c05	196	#if defined(CONFIG_SYS_XLB_PIPELINING)
e1599e83	197	/* Enable piplining */
0f597bc2	198	clrbits_be32(&xlb->config, (1 << 31));
fd428c05	199	#endif
a21fb981 DZ	200
	201	#if defined(CONFIG_WATCHDOG)
	202	/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
	203	out_be32(&gpt0->cir, 0x0000ffff);
	204	out_be32(&gpt0->emsr, 0x9004); /* wden\|ce\|timer_ms */
	205
	206	reset_5xxx_watchdog();
	207	#endif /* CONFIG_WATCHDOG */
945af8d7 WD	208	}
	209
	210	/*
	211	* initialize higher level parts of CPU like time base and timers
	212	*/
	213	int cpu_init_r (void)
	214	{
0f597bc2 DZ	215	volatile struct mpc5xxx_intr *intr =
	216	(struct mpc5xxx_intr *) MPC5XXX_ICTL;
	217
945af8d7	218	/* mask all interrupts */
0f597bc2	219	out_be32(&intr->per_mask, 0xffffff00);
0f597bc2 DZ	220	setbits_be32(&intr->main_mask, 0x0001ffff);
0f597bc2 DZ	221	clrbits_be32(&intr->ctrl, 0x00000f00);
4aeb251f	222	/* route critical ints to normal ints */
0f597bc2	223	setbits_be32(&intr->ctrl, 0x00000001);
945af8d7	224
4431283c	225	#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
945af8d7 WD	226	/* load FEC microcode */
	227	loadtask(0, 2);
	228	#endif
	229
	230	return (0);
	231	}