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[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc5xxx / usb_ohci.c
CommitLineData
80885a9d
WD		 1/*
2 * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.
3 *
4 * (C) Copyright 2003-2004
792a09eb 5 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
80885a9d
WD		 6 *
7 * (C) Copyright 2004
8 * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
9 *
9d46ea4a
WD		 10 * Note: Much of this code has been derived from Linux 2.4
11 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
12 * (C) Copyright 2000-2002 David Brownell
13 *
1a459660 14 * SPDX-License-Identifier: GPL-2.0+
80885a9d
WD		 15 */
16/*
17 * IMPORTANT NOTES
18 * 1 - this driver is intended for use with USB Mass Storage Devices
19 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
20 */
21
22#include <common.h>
23
24#ifdef CONFIG_USB_OHCI
25
26#include <malloc.h>
27#include <usb.h>
28#include "usb_ohci.h"
29
30#include <mpc5xxx.h>
31
32#define OHCI_USE_NPS /* force NoPowerSwitching mode */
33#undef OHCI_VERBOSE_DEBUG /* not always helpful */
34#undef DEBUG
35#undef SHOW_INFO
36#undef OHCI_FILL_TRACE
37
38/* For initializing controller (mask in an HCFS mode too) */
39#define OHCI_CONTROL_INIT \
40 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
41
d00ce090
WD		 42#define readl(a) (*((volatile u32 *)(a)))
43#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
80885a9d 44
80885a9d
WD		 45#ifdef DEBUG
46#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
47#else
48#define dbg(format, arg...) do {} while(0)
49#endif /* DEBUG */
50#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
51#ifdef SHOW_INFO
52#define info(format, arg...) printf("INFO: " format "\n", ## arg)
53#else
54#define info(format, arg...) do {} while(0)
55#endif
56
57#define m16_swap(x) swap_16(x)
58#define m32_swap(x) swap_32(x)
59
80885a9d
WD		 60#define ohci_cpu_to_le16(x) (x)
61#define ohci_cpu_to_le32(x) (x)
80885a9d
WD		 62
63/* global ohci_t */
64static ohci_t gohci;
65/* this must be aligned to a 256 byte boundary */
66struct ohci_hcca ghcca[1];
67/* a pointer to the aligned storage */
68struct ohci_hcca *phcca;
69/* this allocates EDs for all possible endpoints */
70struct ohci_device ohci_dev;
71/* urb_priv */
72urb_priv_t urb_priv;
73/* RHSC flag */
74int got_rhsc;
75/* device which was disconnected */
76struct usb_device *devgone;
9c998aa8
WD		 77/* flag guarding URB transation */
78int urb_finished = 0;
80885a9d
WD		 79
80/*-------------------------------------------------------------------------*/
81
82/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
83 * The erratum (#4) description is incorrect. AMD's workaround waits
84 * till some bits (mostly reserved) are clear; ok for all revs.
85 */
86#define OHCI_QUIRK_AMD756 0xabcd
87#define read_roothub(hc, register, mask) ({ \
88 u32 temp = readl (&hc->regs->roothub.register); \
89 if (hc->flags & OHCI_QUIRK_AMD756) \
90 while (temp & mask) \
91 temp = readl (&hc->regs->roothub.register); \
92 temp; })
93
94static u32 roothub_a (struct ohci *hc)
95 { return read_roothub (hc, a, 0xfc0fe000); }
96static inline u32 roothub_b (struct ohci *hc)
97 { return readl (&hc->regs->roothub.b); }
98static inline u32 roothub_status (struct ohci *hc)
99 { return readl (&hc->regs->roothub.status); }
100static u32 roothub_portstatus (struct ohci *hc, int i)
101 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
102
103
104/* forward declaration */
105static int hc_interrupt (void);
106static void
107td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
108 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
109
110/*-------------------------------------------------------------------------*
111 * URB support functions
112 *-------------------------------------------------------------------------*/
113
114/* free HCD-private data associated with this URB */
115
116static void urb_free_priv (urb_priv_t * urb)
117{
118 int i;
119 int last;
120 struct td * td;
121
122 last = urb->length - 1;
123 if (last >= 0) {
124 for (i = 0; i <= last; i++) {
125 td = urb->td[i];
126 if (td) {
127 td->usb_dev = NULL;
128 urb->td[i] = NULL;
129 }
130 }
131 }
132}
133
134/*-------------------------------------------------------------------------*/
135
136#ifdef DEBUG
137static int sohci_get_current_frame_number (struct usb_device * dev);
138
139/* debug| print the main components of an URB
140 * small: 0) header + data packets 1) just header */
141
142static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
143 int transfer_len, struct devrequest * setup, char * str, int small)
144{
145 urb_priv_t * purb = &urb_priv;
146
147 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
148 str,
149 sohci_get_current_frame_number (dev),
150 usb_pipedevice (pipe),
151 usb_pipeendpoint (pipe),
152 usb_pipeout (pipe)? 'O': 'I',
153 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
154 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
155 purb->actual_length,
156 transfer_len, dev->status);
157#ifdef OHCI_VERBOSE_DEBUG
158 if (!small) {
159 int i, len;
160
161 if (usb_pipecontrol (pipe)) {
162 printf (__FILE__ ": cmd(8):");
163 for (i = 0; i < 8 ; i++)
164 printf (" %02x", ((__u8 *) setup) [i]);
165 printf ("\n");
166 }
167 if (transfer_len > 0 && buffer) {
168 printf (__FILE__ ": data(%d/%d):",
169 purb->actual_length,
170 transfer_len);
171 len = usb_pipeout (pipe)?
172 transfer_len: purb->actual_length;
173 for (i = 0; i < 16 && i < len; i++)
174 printf (" %02x", ((__u8 *) buffer) [i]);
175 printf ("%s\n", i < len? "...": "");
176 }
177 }
178#endif
179}
180
181/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
182void ep_print_int_eds (ohci_t *ohci, char * str) {
183 int i, j;
184 __u32 * ed_p;
185 for (i= 0; i < 32; i++) {
186 j = 5;
187 ed_p = &(ohci->hcca->int_table [i]);
188 if (*ed_p == 0)
189 continue;
190 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
191 while (*ed_p != 0 && j--) {
192 ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p);
193 printf (" ed: %4x;", ed->hwINFO);
194 ed_p = &ed->hwNextED;
195 }
196 printf ("\n");
197 }
198}
199
200static void ohci_dump_intr_mask (char *label, __u32 mask)
201{
202 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
203 label,
204 mask,
205 (mask & OHCI_INTR_MIE) ? " MIE" : "",
206 (mask & OHCI_INTR_OC) ? " OC" : "",
207 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
208 (mask & OHCI_INTR_FNO) ? " FNO" : "",
209 (mask & OHCI_INTR_UE) ? " UE" : "",
210 (mask & OHCI_INTR_RD) ? " RD" : "",
211 (mask & OHCI_INTR_SF) ? " SF" : "",
212 (mask & OHCI_INTR_WDH) ? " WDH" : "",
213 (mask & OHCI_INTR_SO) ? " SO" : ""
214 );
215}
216
217static void maybe_print_eds (char *label, __u32 value)
218{
219 ed_t *edp = (ed_t *)value;
220
221 if (value) {
222 dbg ("%s %08x", label, value);
223 dbg ("%08x", edp->hwINFO);
224 dbg ("%08x", edp->hwTailP);
225 dbg ("%08x", edp->hwHeadP);
226 dbg ("%08x", edp->hwNextED);
227 }
228}
229
230static char * hcfs2string (int state)
231{
232 switch (state) {
233 case OHCI_USB_RESET: return "reset";
234 case OHCI_USB_RESUME: return "resume";
235 case OHCI_USB_OPER: return "operational";
236 case OHCI_USB_SUSPEND: return "suspend";
237 }
238 return "?";
239}
240
241/* dump control and status registers */
242static void ohci_dump_status (ohci_t *controller)
243{
244 struct ohci_regs *regs = controller->regs;
245 __u32 temp;
246
247 temp = readl (&regs->revision) & 0xff;
248 if (temp != 0x10)
249 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
250
251 temp = readl (&regs->control);
252 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
253 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
254 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
255 (temp & OHCI_CTRL_IR) ? " IR" : "",
256 hcfs2string (temp & OHCI_CTRL_HCFS),
257 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
258 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
259 (temp & OHCI_CTRL_IE) ? " IE" : "",
260 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
261 temp & OHCI_CTRL_CBSR
262 );
263
264 temp = readl (&regs->cmdstatus);
265 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
266 (temp & OHCI_SOC) >> 16,
267 (temp & OHCI_OCR) ? " OCR" : "",
268 (temp & OHCI_BLF) ? " BLF" : "",
269 (temp & OHCI_CLF) ? " CLF" : "",
270 (temp & OHCI_HCR) ? " HCR" : ""
271 );
272
273 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
274 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
275
276 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
277
278 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
279 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
280
281 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
282 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
283
284 maybe_print_eds ("donehead", readl (&regs->donehead));
285}
286
287static void ohci_dump_roothub (ohci_t *controller, int verbose)
288{
289 __u32 temp, ndp, i;
290
291 temp = roothub_a (controller);
292 ndp = (temp & RH_A_NDP);
293
294 if (verbose) {
295 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
296 ((temp & RH_A_POTPGT) >> 24) & 0xff,
297 (temp & RH_A_NOCP) ? " NOCP" : "",
298 (temp & RH_A_OCPM) ? " OCPM" : "",
299 (temp & RH_A_DT) ? " DT" : "",
300 (temp & RH_A_NPS) ? " NPS" : "",
301 (temp & RH_A_PSM) ? " PSM" : "",
302 ndp
303 );
304 temp = roothub_b (controller);
305 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
306 temp,
307 (temp & RH_B_PPCM) >> 16,
308 (temp & RH_B_DR)
309 );
310 temp = roothub_status (controller);
311 dbg ("roothub.status: %08x%s%s%s%s%s%s",
312 temp,
313 (temp & RH_HS_CRWE) ? " CRWE" : "",
314 (temp & RH_HS_OCIC) ? " OCIC" : "",
315 (temp & RH_HS_LPSC) ? " LPSC" : "",
316 (temp & RH_HS_DRWE) ? " DRWE" : "",
317 (temp & RH_HS_OCI) ? " OCI" : "",
318 (temp & RH_HS_LPS) ? " LPS" : ""
319 );
320 }
321
322 for (i = 0; i < ndp; i++) {
323 temp = roothub_portstatus (controller, i);
324 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
325 i,
326 temp,
327 (temp & RH_PS_PRSC) ? " PRSC" : "",
328 (temp & RH_PS_OCIC) ? " OCIC" : "",
329 (temp & RH_PS_PSSC) ? " PSSC" : "",
330 (temp & RH_PS_PESC) ? " PESC" : "",
331 (temp & RH_PS_CSC) ? " CSC" : "",
332
333 (temp & RH_PS_LSDA) ? " LSDA" : "",
334 (temp & RH_PS_PPS) ? " PPS" : "",
335 (temp & RH_PS_PRS) ? " PRS" : "",
336 (temp & RH_PS_POCI) ? " POCI" : "",
337 (temp & RH_PS_PSS) ? " PSS" : "",
338
339 (temp & RH_PS_PES) ? " PES" : "",
340 (temp & RH_PS_CCS) ? " CCS" : ""
341 );
342 }
343}
344
345static void ohci_dump (ohci_t *controller, int verbose)
346{
347 dbg ("OHCI controller usb-%s state", controller->slot_name);
348
349 /* dumps some of the state we know about */
350 ohci_dump_status (controller);
351 if (verbose)
352 ep_print_int_eds (controller, "hcca");
353 dbg ("hcca frame #%04x", controller->hcca->frame_no);
354 ohci_dump_roothub (controller, 1);
355}
356
357
358#endif /* DEBUG */
359
360/*-------------------------------------------------------------------------*
361 * Interface functions (URB)
362 *-------------------------------------------------------------------------*/
363
364/* get a transfer request */
365
366int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
367 int transfer_len, struct devrequest *setup, int interval)
368{
369 ohci_t *ohci;
370 ed_t * ed;
371 urb_priv_t *purb_priv;
372 int i, size = 0;
373
374 ohci = &gohci;
375
376 /* when controller's hung, permit only roothub cleanup attempts
377 * such as powering down ports */
378 if (ohci->disabled) {
379 err("sohci_submit_job: EPIPE");
380 return -1;
381 }
382
9c998aa8
WD		 383 /* if we have an unfinished URB from previous transaction let's
384 * fail and scream as quickly as possible so as not to corrupt
385 * further communication */
386 if (!urb_finished) {
387 err("sohci_submit_job: URB NOT FINISHED");
388 return -1;
389 }
390 /* we're about to begin a new transaction here so mark the URB unfinished */
391 urb_finished = 0;
392
80885a9d
WD		 393 /* every endpoint has a ed, locate and fill it */
394 if (!(ed = ep_add_ed (dev, pipe))) {
395 err("sohci_submit_job: ENOMEM");
396 return -1;
397 }
398
399 /* for the private part of the URB we need the number of TDs (size) */
400 switch (usb_pipetype (pipe)) {
401 case PIPE_BULK: /* one TD for every 4096 Byte */
402 size = (transfer_len - 1) / 4096 + 1;
403 break;
404 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
405 size = (transfer_len == 0)? 2:
406 (transfer_len - 1) / 4096 + 3;
407 break;
408 }
409
410 if (size >= (N_URB_TD - 1)) {
411 err("need %d TDs, only have %d", size, N_URB_TD);
412 return -1;
413 }
414 purb_priv = &urb_priv;
415 purb_priv->pipe = pipe;
416
417 /* fill the private part of the URB */
418 purb_priv->length = size;
419 purb_priv->ed = ed;
420 purb_priv->actual_length = 0;
421
422 /* allocate the TDs */
423 /* note that td[0] was allocated in ep_add_ed */
424 for (i = 0; i < size; i++) {
425 purb_priv->td[i] = td_alloc (dev);
426 if (!purb_priv->td[i]) {
427 purb_priv->length = i;
428 urb_free_priv (purb_priv);
429 err("sohci_submit_job: ENOMEM");
430 return -1;
431 }
432 }
433
434 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
435 urb_free_priv (purb_priv);
436 err("sohci_submit_job: EINVAL");
437 return -1;
438 }
439
440 /* link the ed into a chain if is not already */
441 if (ed->state != ED_OPER)
442 ep_link (ohci, ed);
443
444 /* fill the TDs and link it to the ed */
445 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
446
447 return 0;
448}
449
450/*-------------------------------------------------------------------------*/
451
452#ifdef DEBUG
453/* tell us the current USB frame number */
454
455static int sohci_get_current_frame_number (struct usb_device *usb_dev)
456{
457 ohci_t *ohci = &gohci;
458
459 return ohci_cpu_to_le16 (ohci->hcca->frame_no);
460}
461#endif
462
463/*-------------------------------------------------------------------------*
464 * ED handling functions
465 *-------------------------------------------------------------------------*/
466
467/* link an ed into one of the HC chains */
468
469static int ep_link (ohci_t *ohci, ed_t *edi)
470{
471 volatile ed_t *ed = edi;
472
473 ed->state = ED_OPER;
474
475 switch (ed->type) {
476 case PIPE_CONTROL:
477 ed->hwNextED = 0;
478 if (ohci->ed_controltail == NULL) {
479 writel (ed, &ohci->regs->ed_controlhead);
480 } else {
79d696fc 481 ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
80885a9d
WD		 482 }
483 ed->ed_prev = ohci->ed_controltail;
484 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
485 !ohci->ed_rm_list[1] && !ohci->sleeping) {
486 ohci->hc_control |= OHCI_CTRL_CLE;
487 writel (ohci->hc_control, &ohci->regs->control);
488 }
489 ohci->ed_controltail = edi;
490 break;
491
492 case PIPE_BULK:
493 ed->hwNextED = 0;
494 if (ohci->ed_bulktail == NULL) {
495 writel (ed, &ohci->regs->ed_bulkhead);
496 } else {
79d696fc 497 ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
80885a9d
WD		 498 }
499 ed->ed_prev = ohci->ed_bulktail;
500 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
501 !ohci->ed_rm_list[1] && !ohci->sleeping) {
502 ohci->hc_control |= OHCI_CTRL_BLE;
503 writel (ohci->hc_control, &ohci->regs->control);
504 }
505 ohci->ed_bulktail = edi;
506 break;
507 }
508 return 0;
509}
510
511/*-------------------------------------------------------------------------*/
512
513/* unlink an ed from one of the HC chains.
514 * just the link to the ed is unlinked.
515 * the link from the ed still points to another operational ed or 0
516 * so the HC can eventually finish the processing of the unlinked ed */
517
518static int ep_unlink (ohci_t *ohci, ed_t *edi)
519{
520 volatile ed_t *ed = edi;
521
522 ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP);
523
524 switch (ed->type) {
525 case PIPE_CONTROL:
526 if (ed->ed_prev == NULL) {
527 if (!ed->hwNextED) {
528 ohci->hc_control &= ~OHCI_CTRL_CLE;
529 writel (ohci->hc_control, &ohci->regs->control);
530 }
531 writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
532 } else {
533 ed->ed_prev->hwNextED = ed->hwNextED;
534 }
535 if (ohci->ed_controltail == ed) {
536 ohci->ed_controltail = ed->ed_prev;
537 } else {
538 ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
539 }
540 break;
541
542 case PIPE_BULK:
543 if (ed->ed_prev == NULL) {
544 if (!ed->hwNextED) {
545 ohci->hc_control &= ~OHCI_CTRL_BLE;
546 writel (ohci->hc_control, &ohci->regs->control);
547 }
548 writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
549 } else {
550 ed->ed_prev->hwNextED = ed->hwNextED;
551 }
552 if (ohci->ed_bulktail == ed) {
553 ohci->ed_bulktail = ed->ed_prev;
554 } else {
555 ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
556 }
557 break;
558 }
559 ed->state = ED_UNLINK;
560 return 0;
561}
562
563
564/*-------------------------------------------------------------------------*/
565
566/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
567 * but the USB stack is a little bit stateless so we do it at every transaction
568 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
569 * in all other cases the state is left unchanged
570 * the ed info fields are setted anyway even though most of them should not change */
571
572static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
573{
574 td_t *td;
575 ed_t *ed_ret;
576 volatile ed_t *ed;
577
578 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
579 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
580
581 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
582 err("ep_add_ed: pending delete");
583 /* pending delete request */
584 return NULL;
585 }
586
587 if (ed->state == ED_NEW) {
588 ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
589 /* dummy td; end of td list for ed */
590 td = td_alloc (usb_dev);
79d696fc 591 ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
80885a9d
WD		 592 ed->hwHeadP = ed->hwTailP;
593 ed->state = ED_UNLINK;
594 ed->type = usb_pipetype (pipe);
595 ohci_dev.ed_cnt++;
596 }
597
598 ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
599 | usb_pipeendpoint (pipe) << 7
600 | (usb_pipeisoc (pipe)? 0x8000: 0)
601 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
c60795f4 602 | (usb_dev->speed == USB_SPEED_LOW) << 13
80885a9d
WD		 603 | usb_maxpacket (usb_dev, pipe) << 16);
604
605 return ed_ret;
606}
607
608/*-------------------------------------------------------------------------*
609 * TD handling functions
610 *-------------------------------------------------------------------------*/
611
612/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
613
614static void td_fill (ohci_t *ohci, unsigned int info,
615 void *data, int len,
616 struct usb_device *dev, int index, urb_priv_t *urb_priv)
617{
618 volatile td_t *td, *td_pt;
619#ifdef OHCI_FILL_TRACE
620 int i;
621#endif
622
623 if (index > urb_priv->length) {
624 err("index > length");
625 return;
626 }
627 /* use this td as the next dummy */
628 td_pt = urb_priv->td [index];
629 td_pt->hwNextTD = 0;
630
631 /* fill the old dummy TD */
632 td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
633
634 td->ed = urb_priv->ed;
635 td->next_dl_td = NULL;
636 td->index = index;
637 td->data = (__u32)data;
638#ifdef OHCI_FILL_TRACE
9dbc3667 639 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
80885a9d
WD		 640 for (i = 0; i < len; i++)
641 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
642 printf("\n");
643 }
644#endif
645 if (!len)
646 data = 0;
647
648 td->hwINFO = ohci_cpu_to_le32 (info);
79d696fc 649 td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
80885a9d 650 if (data)
79d696fc 651 td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
80885a9d
WD		 652 else
653 td->hwBE = 0;
79d696fc 654 td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
80885a9d
WD		 655
656 /* append to queue */
657 td->ed->hwTailP = td->hwNextTD;
658}
659
660/*-------------------------------------------------------------------------*/
661
662/* prepare all TDs of a transfer */
80885a9d
WD		 663static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
664 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
665{
666 ohci_t *ohci = &gohci;
667 int data_len = transfer_len;
668 void *data;
669 int cnt = 0;
670 __u32 info = 0;
671 unsigned int toggle = 0;
672
3450a859
VC		 673 /* OHCI handles the DATA-toggles itself, we just use the
674 USB-toggle bits for resetting */
80885a9d
WD		 675 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
676 toggle = TD_T_TOGGLE;
677 } else {
678 toggle = TD_T_DATA0;
679 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
680 }
681 urb->td_cnt = 0;
682 if (data_len)
683 data = buffer;
684 else
685 data = 0;
686
687 switch (usb_pipetype (pipe)) {
688 case PIPE_BULK:
689 info = usb_pipeout (pipe)?
690 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
691 while(data_len > 4096) {
692 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
693 data += 4096; data_len -= 4096; cnt++;
694 }
695 info = usb_pipeout (pipe)?
696 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
697 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
698 cnt++;
699
700 if (!ohci->sleeping)
701 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
702 break;
703
704 case PIPE_CONTROL:
705 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
706 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
707 if (data_len > 0) {
708 info = usb_pipeout (pipe)?
709 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
710 /* NOTE: mishandles transfers >8K, some >4K */
711 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
712 }
713 info = usb_pipeout (pipe)?
714 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
715 td_fill (ohci, info, data, 0, dev, cnt++, urb);
716 if (!ohci->sleeping)
717 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
718 break;
719 }
720 if (urb->length != cnt)
721 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
722}
723
724/*-------------------------------------------------------------------------*
725 * Done List handling functions
726 *-------------------------------------------------------------------------*/
727
728
729/* calculate the transfer length and update the urb */
730
731static void dl_transfer_length(td_t * td)
732{
a4421730 733 __u32 tdBE, tdCBP;
80885a9d
WD		 734 urb_priv_t *lurb_priv = &urb_priv;
735
80885a9d
WD		 736 tdBE = ohci_cpu_to_le32 (td->hwBE);
737 tdCBP = ohci_cpu_to_le32 (td->hwCBP);
738
739
9dbc3667 740 if (!(usb_pipecontrol(lurb_priv->pipe) &&
80885a9d
WD		 741 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
742 if (tdBE != 0) {
743 if (td->hwCBP == 0)
744 lurb_priv->actual_length += tdBE - td->data + 1;
745 else
746 lurb_priv->actual_length += tdCBP - td->data;
747 }
748 }
749}
750
751/*-------------------------------------------------------------------------*/
752
753/* replies to the request have to be on a FIFO basis so
754 * we reverse the reversed done-list */
755
756static td_t * dl_reverse_done_list (ohci_t *ohci)
757{
758 __u32 td_list_hc;
759 td_t *td_rev = NULL;
760 td_t *td_list = NULL;
761 urb_priv_t *lurb_priv = NULL;
762
763 td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
764 ohci->hcca->done_head = 0;
765
766 while (td_list_hc) {
767 td_list = (td_t *)td_list_hc;
768
769 if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
770 lurb_priv = &urb_priv;
771 dbg(" USB-error/status: %x : %p",
772 TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
773 if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
774 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
775 td_list->ed->hwHeadP =
776 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) |
777 (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
778 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
779 } else
780 td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
781 }
80885a9d 782 td_list->hwNextTD = 0;
80885a9d
WD		 783 }
784
785 td_list->next_dl_td = td_rev;
786 td_rev = td_list;
787 td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
788 }
789 return td_list;
790}
791
792/*-------------------------------------------------------------------------*/
793
794/* td done list */
795static int dl_done_list (ohci_t *ohci, td_t *td_list)
796{
797 td_t *td_list_next = NULL;
798 ed_t *ed;
799 int cc = 0;
9c998aa8 800 int stat = 0;
80885a9d
WD		 801 /* urb_t *urb; */
802 urb_priv_t *lurb_priv;
803 __u32 tdINFO, edHeadP, edTailP;
804
805 while (td_list) {
806 td_list_next = td_list->next_dl_td;
807
808 lurb_priv = &urb_priv;
809 tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
810
811 ed = td_list->ed;
812
813 dl_transfer_length(td_list);
814
815 /* error code of transfer */
816 cc = TD_CC_GET (tdINFO);
817 if (++(lurb_priv->td_cnt) == lurb_priv->length) {
818 if ((ed->state & (ED_OPER | ED_UNLINK))
819 && (lurb_priv->state != URB_DEL)) {
820 dbg("ConditionCode %#x", cc);
821 stat = cc_to_error[cc];
9c998aa8 822 urb_finished = 1;
80885a9d
WD		 823 }
824 }
825
826 if (ed->state != ED_NEW) {
827 edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
828 edTailP = ohci_cpu_to_le32 (ed->hwTailP);
829
830 /* unlink eds if they are not busy */
831 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
832 ep_unlink (ohci, ed);
833 }
834
835 td_list = td_list_next;
836 }
837 return stat;
838}
839
840/*-------------------------------------------------------------------------*
841 * Virtual Root Hub
842 *-------------------------------------------------------------------------*/
843
eb838e7d 844#include <usbroothubdes.h>
80885a9d
WD		 845
846/* Hub class-specific descriptor is constructed dynamically */
847
848
849/*-------------------------------------------------------------------------*/
850
851#define OK(x) len = (x); break
852#ifdef DEBUG
853#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
854#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
855#else
856#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
857#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
858#endif
859#define RD_RH_STAT roothub_status(&gohci)
860#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
861
862/* request to virtual root hub */
863
864int rh_check_port_status(ohci_t *controller)
865{
866 __u32 temp, ndp, i;
867 int res;
868
869 res = -1;
870 temp = roothub_a (controller);
871 ndp = (temp & RH_A_NDP);
872 for (i = 0; i < ndp; i++) {
873 temp = roothub_portstatus (controller, i);
874 /* check for a device disconnect */
875 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
876 (RH_PS_PESC | RH_PS_CSC)) &&
877 ((temp & RH_PS_CCS) == 0)) {
878 res = i;
879 break;
880 }
881 }
882 return res;
883}
884
885static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
886 void *buffer, int transfer_len, struct devrequest *cmd)
887{
888 void * data = buffer;
889 int leni = transfer_len;
890 int len = 0;
891 int stat = 0;
892 __u32 datab[4];
893 __u8 *data_buf = (__u8 *)datab;
894 __u16 bmRType_bReq;
895 __u16 wValue;
896 __u16 wIndex;
897 __u16 wLength;
898
899#ifdef DEBUG
900urb_priv.actual_length = 0;
901pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
902#endif
9dbc3667 903 if (usb_pipeint(pipe)) {
80885a9d
WD		 904 info("Root-Hub submit IRQ: NOT implemented");
905 return 0;
906 }
907
908 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
909 wValue = m16_swap (cmd->value);
910 wIndex = m16_swap (cmd->index);
911 wLength = m16_swap (cmd->length);
912
913 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
914 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
915
916 switch (bmRType_bReq) {
917 /* Request Destination:
918 without flags: Device,
919 RH_INTERFACE: interface,
920 RH_ENDPOINT: endpoint,
921 RH_CLASS means HUB here,
922 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
923 */
924
925 case RH_GET_STATUS:
926 *(__u16 *) data_buf = m16_swap (1); OK (2);
927 case RH_GET_STATUS | RH_INTERFACE:
928 *(__u16 *) data_buf = m16_swap (0); OK (2);
929 case RH_GET_STATUS | RH_ENDPOINT:
930 *(__u16 *) data_buf = m16_swap (0); OK (2);
931 case RH_GET_STATUS | RH_CLASS:
932 *(__u32 *) data_buf = m32_swap (
933 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
934 OK (4);
935 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
936 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
937
938 case RH_CLEAR_FEATURE | RH_ENDPOINT:
939 switch (wValue) {
940 case (RH_ENDPOINT_STALL): OK (0);
941 }
942 break;
943
944 case RH_CLEAR_FEATURE | RH_CLASS:
945 switch (wValue) {
946 case RH_C_HUB_LOCAL_POWER:
947 OK(0);
948 case (RH_C_HUB_OVER_CURRENT):
949 WR_RH_STAT(RH_HS_OCIC); OK (0);
950 }
951 break;
952
953 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
954 switch (wValue) {
955 case (RH_PORT_ENABLE):
956 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
957 case (RH_PORT_SUSPEND):
958 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
959 case (RH_PORT_POWER):
960 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
961 case (RH_C_PORT_CONNECTION):
962 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
963 case (RH_C_PORT_ENABLE):
964 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
965 case (RH_C_PORT_SUSPEND):
966 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
967 case (RH_C_PORT_OVER_CURRENT):
968 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
969 case (RH_C_PORT_RESET):
970 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
971 }
972 break;
973
974 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
975 switch (wValue) {
976 case (RH_PORT_SUSPEND):
977 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
978 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
979 if (RD_RH_PORTSTAT & RH_PS_CCS)
980 WR_RH_PORTSTAT (RH_PS_PRS);
981 OK (0);
982 case (RH_PORT_POWER):
983 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
984 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
985 if (RD_RH_PORTSTAT & RH_PS_CCS)
986 WR_RH_PORTSTAT (RH_PS_PES );
987 OK (0);
988 }
989 break;
990
991 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
992
993 case RH_GET_DESCRIPTOR:
994 switch ((wValue & 0xff00) >> 8) {
995 case (0x01): /* device descriptor */
996 len = min_t(unsigned int,
997 leni,
998 min_t(unsigned int,
999 sizeof (root_hub_dev_des),
1000 wLength));
1001 data_buf = root_hub_dev_des; OK(len);
1002 case (0x02): /* configuration descriptor */
1003 len = min_t(unsigned int,
1004 leni,
1005 min_t(unsigned int,
1006 sizeof (root_hub_config_des),
1007 wLength));
1008 data_buf = root_hub_config_des; OK(len);
1009 case (0x03): /* string descriptors */
1010 if(wValue==0x0300) {
1011 len = min_t(unsigned int,
1012 leni,
1013 min_t(unsigned int,
1014 sizeof (root_hub_str_index0),
1015 wLength));
1016 data_buf = root_hub_str_index0;
1017 OK(len);
1018 }
1019 if(wValue==0x0301) {
1020 len = min_t(unsigned int,
1021 leni,
1022 min_t(unsigned int,
1023 sizeof (root_hub_str_index1),
1024 wLength));
1025 data_buf = root_hub_str_index1;
1026 OK(len);
1027 }
1028 default:
1029 stat = USB_ST_STALLED;
1030 }
1031 break;
1032
1033 case RH_GET_DESCRIPTOR | RH_CLASS:
1034 {
1035 __u32 temp = roothub_a (&gohci);
1036
1037 data_buf [0] = 9; /* min length; */
1038 data_buf [1] = 0x29;
1039 data_buf [2] = temp & RH_A_NDP;
1040 data_buf [3] = 0;
1041 if (temp & RH_A_PSM) /* per-port power switching? */
1042 data_buf [3] |= 0x1;
1043 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1044 data_buf [3] |= 0x10;
1045 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1046 data_buf [3] |= 0x8;
1047
1048 /* corresponds to data_buf[4-7] */
1049 datab [1] = 0;
1050 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1051 temp = roothub_b (&gohci);
1052 data_buf [7] = temp & RH_B_DR;
1053 if (data_buf [2] < 7) {
1054 data_buf [8] = 0xff;
1055 } else {
1056 data_buf [0] += 2;
1057 data_buf [8] = (temp & RH_B_DR) >> 8;
1058 data_buf [10] = data_buf [9] = 0xff;
1059 }
1060
1061 len = min_t(unsigned int, leni,
1062 min_t(unsigned int, data_buf [0], wLength));
1063 OK (len);
1064 }
1065
1066 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1067
1068 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1069
1070 default:
1071 dbg ("unsupported root hub command");
1072 stat = USB_ST_STALLED;
1073 }
1074
1075#ifdef DEBUG
1076 ohci_dump_roothub (&gohci, 1);
1077#endif
1078
1079 len = min_t(int, len, leni);
1080 if (data != data_buf)
1081 memcpy (data, data_buf, len);
1082 dev->act_len = len;
1083 dev->status = stat;
1084
1085#ifdef DEBUG
1086 if (transfer_len)
1087 urb_priv.actual_length = transfer_len;
1088 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1089#endif
1090
1091 return stat;
1092}
1093
1094/*-------------------------------------------------------------------------*/
1095
1096/* common code for handling submit messages - used for all but root hub */
1097/* accesses. */
1098int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1099 int transfer_len, struct devrequest *setup, int interval)
1100{
1101 int stat = 0;
1102 int maxsize = usb_maxpacket(dev, pipe);
1103 int timeout;
1104
1105 /* device pulled? Shortcut the action. */
1106 if (devgone == dev) {
1107 dev->status = USB_ST_CRC_ERR;
1108 return 0;
1109 }
1110
1111#ifdef DEBUG
1112 urb_priv.actual_length = 0;
1113 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1114#endif
1115 if (!maxsize) {
1116 err("submit_common_message: pipesize for pipe %lx is zero",
1117 pipe);
1118 return -1;
1119 }
1120
1121 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1122 err("sohci_submit_job failed");
1123 return -1;
1124 }
1125
1126 /* allow more time for a BULK device to react - some are slow */
1127#define BULK_TO 5000 /* timeout in milliseconds */
9dbc3667 1128 if (usb_pipebulk(pipe))
80885a9d
WD		 1129 timeout = BULK_TO;
1130 else
1131 timeout = 100;
1132
1133 /* wait for it to complete */
1134 for (;;) {
1135 /* check whether the controller is done */
1136 stat = hc_interrupt();
1137 if (stat < 0) {
1138 stat = USB_ST_CRC_ERR;
1139 break;
1140 }
095b8a37 1141
9c998aa8
WD		 1142 /* NOTE: since we are not interrupt driven in U-Boot and always
1143 * handle only one URB at a time, we cannot assume the
1144 * transaction finished on the first successful return from
1145 * hc_interrupt().. unless the flag for current URB is set,
1146 * meaning that all TD's to/from device got actually
1147 * transferred and processed. If the current URB is not
1148 * finished we need to re-iterate this loop so as
1149 * hc_interrupt() gets called again as there needs to be some
1150 * more TD's to process still */
1151 if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
80885a9d
WD		 1152 /* 0xff is returned for an SF-interrupt */
1153 break;
1154 }
9c998aa8 1155
80885a9d 1156 if (--timeout) {
5b84dd67 1157 mdelay(1);
9c998aa8
WD		 1158 if (!urb_finished)
1159 dbg("\%");
1160
80885a9d
WD		 1161 } else {
1162 err("CTL:TIMEOUT ");
9c998aa8 1163 dbg("submit_common_msg: TO status %x\n", stat);
80885a9d 1164 stat = USB_ST_CRC_ERR;
9c998aa8 1165 urb_finished = 1;
80885a9d
WD		 1166 break;
1167 }
1168 }
9c998aa8 1169#if 0
80885a9d
WD		 1170 /* we got an Root Hub Status Change interrupt */
1171 if (got_rhsc) {
1172#ifdef DEBUG
1173 ohci_dump_roothub (&gohci, 1);
1174#endif
1175 got_rhsc = 0;
1176 /* abuse timeout */
1177 timeout = rh_check_port_status(&gohci);
1178 if (timeout >= 0) {
1179#if 0 /* this does nothing useful, but leave it here in case that changes */
1180 /* the called routine adds 1 to the passed value */
1181 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1182#endif
1183 /*
1184 * XXX
1185 * This is potentially dangerous because it assumes
1186 * that only one device is ever plugged in!
1187 */
1188 devgone = dev;
1189 }
1190 }
9c998aa8 1191#endif
80885a9d
WD		 1192
1193 dev->status = stat;
1194 dev->act_len = transfer_len;
1195
1196#ifdef DEBUG
1197 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1198#endif
1199
1200 /* free TDs in urb_priv */
1201 urb_free_priv (&urb_priv);
1202 return 0;
1203}
1204
1205/* submit routines called from usb.c */
1206int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1207 int transfer_len)
1208{
1209 info("submit_bulk_msg");
1210 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1211}
1212
1213int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1214 int transfer_len, struct devrequest *setup)
1215{
1216 int maxsize = usb_maxpacket(dev, pipe);
1217
1218 info("submit_control_msg");
1219#ifdef DEBUG
1220 urb_priv.actual_length = 0;
1221 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1222#endif
1223 if (!maxsize) {
1224 err("submit_control_message: pipesize for pipe %lx is zero",
1225 pipe);
1226 return -1;
1227 }
1228 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1229 gohci.rh.dev = dev;
1230 /* root hub - redirect */
1231 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1232 setup);
1233 }
1234
1235 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1236}
1237
1238int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1239 int transfer_len, int interval)
1240{
1241 info("submit_int_msg");
1242 return -1;
1243}
1244
1245/*-------------------------------------------------------------------------*
1246 * HC functions
1247 *-------------------------------------------------------------------------*/
1248
1249/* reset the HC and BUS */
1250
1251static int hc_reset (ohci_t *ohci)
1252{
1253 int timeout = 30;
1254 int smm_timeout = 50; /* 0,5 sec */
1255
1256 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1257 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1258 info("USB HC TakeOver from SMM");
1259 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
5b84dd67 1260 mdelay (10);
80885a9d
WD		 1261 if (--smm_timeout == 0) {
1262 err("USB HC TakeOver failed!");
1263 return -1;
1264 }
1265 }
1266 }
1267
1268 /* Disable HC interrupts */
1269 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1270
1271 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1272 ohci->slot_name,
1273 readl (&ohci->regs->control));
1274
1275 /* Reset USB (needed by some controllers) */
1276 ohci->hc_control = 0;
1277 writel (ohci->hc_control, &ohci->regs->control);
1278
1279 /* HC Reset requires max 10 us delay */
1280 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1281 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1282 if (--timeout == 0) {
1283 err("USB HC reset timed out!");
1284 return -1;
1285 }
1286 udelay (1);
1287 }
1288 return 0;
1289}
1290
1291/*-------------------------------------------------------------------------*/
1292
1293/* Start an OHCI controller, set the BUS operational
1294 * enable interrupts
1295 * connect the virtual root hub */
1296
1297static int hc_start (ohci_t * ohci)
1298{
1299 __u32 mask;
1300 unsigned int fminterval;
1301
1302 ohci->disabled = 1;
1303
1304 /* Tell the controller where the control and bulk lists are
1305 * The lists are empty now. */
1306
1307 writel (0, &ohci->regs->ed_controlhead);
1308 writel (0, &ohci->regs->ed_bulkhead);
1309
1310 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1311
1312 fminterval = 0x2edf;
1313 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1314 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1315 writel (fminterval, &ohci->regs->fminterval);
1316 writel (0x628, &ohci->regs->lsthresh);
1317
1318 /* start controller operations */
1319 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1320 ohci->disabled = 0;
1321 writel (ohci->hc_control, &ohci->regs->control);
1322
1323 /* disable all interrupts */
1324 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1325 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1326 OHCI_INTR_OC | OHCI_INTR_MIE);
1327 writel (mask, &ohci->regs->intrdisable);
1328 /* clear all interrupts */
1329 mask &= ~OHCI_INTR_MIE;
1330 writel (mask, &ohci->regs->intrstatus);
1331 /* Choose the interrupts we care about now - but w/o MIE */
1332 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1333 writel (mask, &ohci->regs->intrenable);
1334
1335#ifdef OHCI_USE_NPS
1336 /* required for AMD-756 and some Mac platforms */
1337 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1338 &ohci->regs->roothub.a);
1339 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1340#endif /* OHCI_USE_NPS */
1341
80885a9d
WD		 1342 /* POTPGT delay is bits 24-31, in 2 ms units. */
1343 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1344
1345 /* connect the virtual root hub */
1346 ohci->rh.devnum = 0;
1347
1348 return 0;
1349}
1350
1351/*-------------------------------------------------------------------------*/
1352
1353/* an interrupt happens */
1354
1355static int
1356hc_interrupt (void)
1357{
1358 ohci_t *ohci = &gohci;
1359 struct ohci_regs *regs = ohci->regs;
1360 int ints;
1361 int stat = -1;
095b8a37 1362
9c998aa8
WD		 1363 if ((ohci->hcca->done_head != 0) &&
1364 !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
80885a9d 1365
9c998aa8
WD		 1366 ints = OHCI_INTR_WDH;
1367
1368 } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
1369 ohci->disabled++;
1370 err ("%s device removed!", ohci->slot_name);
1371 return -1;
095b8a37 1372
9c998aa8
WD		 1373 } else if ((ints &= readl (&regs->intrenable)) == 0) {
1374 dbg("hc_interrupt: returning..\n");
1375 return 0xff;
80885a9d
WD		 1376 }
1377
1378 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1379
1380 if (ints & OHCI_INTR_RHSC) {
1381 got_rhsc = 1;
9c998aa8 1382 stat = 0xff;
80885a9d
WD		 1383 }
1384
1385 if (ints & OHCI_INTR_UE) {
1386 ohci->disabled++;
1387 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1388 ohci->slot_name);
1389 /* e.g. due to PCI Master/Target Abort */
1390
1391#ifdef DEBUG
1392 ohci_dump (ohci, 1);
1393#endif
1394 /* FIXME: be optimistic, hope that bug won't repeat often. */
1395 /* Make some non-interrupt context restart the controller. */
1396 /* Count and limit the retries though; either hardware or */
1397 /* software errors can go forever... */
1398 hc_reset (ohci);
1399 return -1;
1400 }
1401
1402 if (ints & OHCI_INTR_WDH) {
1403 writel (OHCI_INTR_WDH, &regs->intrdisable);
1404 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1405 writel (OHCI_INTR_WDH, &regs->intrenable);
1406 }
1407
1408 if (ints & OHCI_INTR_SO) {
1409 dbg("USB Schedule overrun\n");
1410 writel (OHCI_INTR_SO, &regs->intrenable);
1411 stat = -1;
1412 }
1413
1414 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1415 if (ints & OHCI_INTR_SF) {
1416 unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
5b84dd67 1417 mdelay(1);
80885a9d
WD		 1418 writel (OHCI_INTR_SF, &regs->intrdisable);
1419 if (ohci->ed_rm_list[frame] != NULL)
1420 writel (OHCI_INTR_SF, &regs->intrenable);
1421 stat = 0xff;
1422 }
1423
1424 writel (ints, &regs->intrstatus);
1425 return stat;
1426}
1427
1428/*-------------------------------------------------------------------------*/
1429
1430/*-------------------------------------------------------------------------*/
1431
1432/* De-allocate all resources.. */
1433
1434static void hc_release_ohci (ohci_t *ohci)
1435{
1436 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1437
1438 if (!ohci->disabled)
1439 hc_reset (ohci);
1440}
1441
1442/*-------------------------------------------------------------------------*/
1443
1444/*
1445 * low level initalisation routine, called from usb.c
1446 */
1447static char ohci_inited = 0;
1448
06d513ec 1449int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
80885a9d
WD		 1450{
1451
1452 /* Set the USB Clock */
4d13cbad 1453 *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
c3f9d493 1454
307ecb6d
EM		 1455#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */
1456 /* remove all PSC3 USB bits first before ORing in ours */
1457 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00;
1458#else
c3f9d493
WD		 1459 /* remove all USB bits first before ORing in ours */
1460 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
307ecb6d 1461#endif
80885a9d 1462 /* Activate USB port */
4d13cbad 1463 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
80885a9d
WD		 1464
1465 memset (&gohci, 0, sizeof (ohci_t));
1466 memset (&urb_priv, 0, sizeof (urb_priv_t));
1467
1468 /* align the storage */
1469 if ((__u32)&ghcca[0] & 0xff) {
1470 err("HCCA not aligned!!");
1471 return -1;
1472 }
1473 phcca = &ghcca[0];
1474 info("aligned ghcca %p", phcca);
1475 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1476 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1477 err("EDs not aligned!!");
1478 return -1;
1479 }
1480 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1481 if ((__u32)gtd & 0x7) {
1482 err("TDs not aligned!!");
1483 return -1;
1484 }
1485 ptd = gtd;
1486 gohci.hcca = phcca;
1487 memset (phcca, 0, sizeof (struct ohci_hcca));
1488
1489 gohci.disabled = 1;
1490 gohci.sleeping = 0;
1491 gohci.irq = -1;
1492 gohci.regs = (struct ohci_regs *)MPC5XXX_USB;
1493
1494 gohci.flags = 0;
1495 gohci.slot_name = "mpc5200";
1496
1497 if (hc_reset (&gohci) < 0) {
1498 hc_release_ohci (&gohci);
1499 return -1;
1500 }
1501
1502 if (hc_start (&gohci) < 0) {
1503 err ("can't start usb-%s", gohci.slot_name);
1504 hc_release_ohci (&gohci);
1505 return -1;
1506 }
1507
1508#ifdef DEBUG
1509 ohci_dump (&gohci, 1);
1510#endif
1511 ohci_inited = 1;
9c998aa8
WD		 1512 urb_finished = 1;
1513
80885a9d
WD		 1514 return 0;
1515}
1516
c7e3b2b5 1517int usb_lowlevel_stop(int index)
80885a9d
WD		 1518{
1519 /* this gets called really early - before the controller has */
1520 /* even been initialized! */
1521 if (!ohci_inited)
1522 return 0;
1523 /* TODO release any interrupts, etc. */
1524 /* call hc_release_ohci() here ? */
1525 hc_reset (&gohci);
1526 return 0;
1527}
1528
1529#endif /* CONFIG_USB_OHCI */
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