[people/ms/u-boot.git] / arch / powerpc / cpu / mpc824x / cpu_init.c

/*
 * (C) Copyright 2000
 * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <mpc824x.h>

#ifndef CONFIG_SYS_BANK0_ROW
#define CONFIG_SYS_BANK0_ROW 0
#endif
#ifndef CONFIG_SYS_BANK1_ROW
#define CONFIG_SYS_BANK1_ROW 0
#endif
#ifndef CONFIG_SYS_BANK2_ROW
#define CONFIG_SYS_BANK2_ROW 0
#endif
#ifndef CONFIG_SYS_BANK3_ROW
#define CONFIG_SYS_BANK3_ROW 0
#endif
#ifndef CONFIG_SYS_BANK4_ROW
#define CONFIG_SYS_BANK4_ROW 0
#endif
#ifndef CONFIG_SYS_BANK5_ROW
#define CONFIG_SYS_BANK5_ROW 0
#endif
#ifndef CONFIG_SYS_BANK6_ROW
#define CONFIG_SYS_BANK6_ROW 0
#endif
#ifndef CONFIG_SYS_BANK7_ROW
#define CONFIG_SYS_BANK7_ROW 0
#endif
#ifndef CONFIG_SYS_DBUS_SIZE2
#define CONFIG_SYS_DBUS_SIZE2 0
#endif

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 */
void
cpu_init_f (void)
{
/* MOUSSE board is initialized in asm */
#if !defined(CONFIG_MOUSSE)
    register unsigned long val;
    CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/

#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
/* Why is this here, you ask?  Try, just try setting 0x8000
 * in PCIACR with CONFIG_WRITE_HALFWORD()
 * this one was a stumper, and we are annoyed
 */

#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
	__asm__ __volatile__("		\
		stw  %2,0(%0)\n		\
		sync\n			\
		sth  %3,2(%1)\n		\
		sync\n			\
		"			\
		: /* no output */	\
		: "r" (CONFIG_ADDR), "r" (CONFIG_DATA),			\
		"r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16))	\
	);

	M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
#endif

	CONFIG_WRITE_BYTE(PCLSR, 0x8);	/* set PCI cache line size */
	CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
	/*
	* Note that although this bit is cleared after a hard reset, it
	* must be explicitly set and then cleared by software during
	* initialization in order to guarantee correct operation of the
	* DLL and the SDRAM_CLK[0:3] signals (if they are used).
	*/
	CONFIG_READ_BYTE (AMBOR, val);
	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
#ifdef CONFIG_MPC8245
	/* silicon bug 28 MPC8245 */
	CONFIG_READ_BYTE(AMBOR,val);
	CONFIG_WRITE_BYTE(AMBOR,val|0x1);

#if 0
	/*
	 * The following bug only affects older (XPC8245) processors.
	 * DMA transfers initiated by external devices get corrupted due
	 * to a hardware scheduling problem.
	 *
	 * The effect is:
	 * when transferring X words, the first 32 words are transferred
	 * OK, the next 3 x 32 words are 'old' data (from previous DMA)
	 * while the rest of the X words is xferred fine.
	 *
	 * Disabling 3 of the 4 32 word hardware buffers solves the problem
	 * with no significant performance loss.
	 */

	CONFIG_READ_BYTE(PCMBCR,val);
	/* in order not to corrupt data which is being read over the PCI bus
	* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
	* 4.11 in the  processor user manual
	* */

#if 1
	CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
#else
	CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
	CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
	/* default, 4 PCMRBs are used */
#endif
#endif
#endif

	CONFIG_READ_WORD(PICR1, val);
#if defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD( PICR1,
		(val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
		       PIRC1_MSK | PICR1_PROC_TYPE_603E |
		       PICR1_FLASH_WR_EN | PICR1_MCP_EN |
		       PICR1_CF_DPARK | PICR1_EN_PCS |
		       PICR1_CF_APARK );
#elif defined(CONFIG_MPC8245)
	CONFIG_WRITE_WORD( PICR1,
		(val & (PICR1_RCS0)) |
		       PICR1_PROC_TYPE_603E |
		       PICR1_FLASH_WR_EN | PICR1_MCP_EN |
		       PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
		       PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

	CONFIG_READ_WORD(PICR2, val);
	val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
#ifndef CONFIG_PN62
	val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
#endif
	CONFIG_WRITE_WORD(PICR2, val);

	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
#ifndef CONFIG_SYS_RAMBOOT
	CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
				 (CONFIG_SYS_BANK0_ROW) |
				 (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
				 (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
				 (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
				 (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
				 (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
				 (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
				 (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
				 (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
#endif

#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
				 CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
				 CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
#else
	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
#endif

#if defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD(MCCR3,
		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT));
#elif defined(CONFIG_MPC8245)
	CONFIG_WRITE_WORD(MCCR3,
		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

/* this is gross.  We think these should all be the same, and various boards
 *  should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
 *  its not set, we define it to zero in this file
 */
#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
	CONFIG_WRITE_WORD(MCCR4,
	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
	MCCR4_BIT21 |
	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		  CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
#elif defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD(MCCR4,
	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
	MCCR4_BIT21 |
	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		  (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#elif defined(CONFIG_MPC8245)
	CONFIG_READ_WORD(MCCR1, val);
	val &= MCCR1_DBUS_SIZE0;    /* test for 64-bit mem bus */

	CONFIG_WRITE_WORD(MCCR4,
		(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
		(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
		(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
		(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
		(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
		((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
		(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
		(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		      (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT)  |
		(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
		(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

	CONFIG_WRITE_WORD(MSAR1,
		( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMSAR1,
		( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MSAR2,
		( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMSAR2,
		( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MEAR1,
		( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMEAR1,
		( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MEAR2,
		( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMEAR2,
		( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));

	CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
#ifdef CONFIG_SYS_DLL_MAX_DELAY
	CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY);	/* needed to make DLL lock */
#endif
#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
	CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
#endif
#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
	CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD);	/* change memory input */
#endif /* setup & hold time */

	CONFIG_WRITE_BYTE(MBER,
		 CONFIG_SYS_BANK0_ENABLE |
		(CONFIG_SYS_BANK1_ENABLE << 1) |
		(CONFIG_SYS_BANK2_ENABLE << 2) |
		(CONFIG_SYS_BANK3_ENABLE << 3) |
		(CONFIG_SYS_BANK4_ENABLE << 4) |
		(CONFIG_SYS_BANK5_ENABLE << 5) |
		(CONFIG_SYS_BANK6_ENABLE << 6) |
		(CONFIG_SYS_BANK7_ENABLE << 7));

#ifdef CONFIG_SYS_PGMAX
	CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
#endif

	/* ! Wait 200us before initialize other registers */
	/*FIXME: write a decent udelay wait */
	__asm__ __volatile__(
		" mtctr	%0 \n \
		0: bdnz	 0b\n"
		:
		: "r" (0x10000));

	CONFIG_READ_WORD(MCCR1, val);
	CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
	__asm__ __volatile__("eieio");

#endif /* !CONFIG_MOUSSE */
}


#ifdef CONFIG_MOUSSE
#ifdef INCLUDE_MPC107_REPORT
struct MPC107_s {
	unsigned int iobase;
	char desc[120];
} MPC107Regs[] = {
	{ BMC_BASE +  0x00, "MPC107 Vendor/Device ID"		},
	{ BMC_BASE +  0x04, "MPC107 PCI Command/Status Register" },
	{ BMC_BASE +  0x08, "MPC107 Revision"			},
	{ BMC_BASE +  0x0C, "MPC107 Cache Line Size"		},
	{ BMC_BASE +  0x10, "MPC107 LMBAR"			},
	{ BMC_BASE +  0x14, "MPC824x PCSR"			},
	{ BMC_BASE +  0xA8, "MPC824x PICR1"			},
	{ BMC_BASE +  0xAC, "MPC824x PICR2"			},
	{ BMC_BASE +  0x46, "MPC824x PACR"			},
	{ BMC_BASE + 0x310, "MPC824x ITWR"			},
	{ BMC_BASE + 0x300, "MPC824x OMBAR"			},
	{ BMC_BASE + 0x308, "MPC824x OTWR"			},
	{ BMC_BASE +  0x14, "MPC107 Peripheral Control and Status Register" },
	{ BMC_BASE + 0x78, "MPC107 EUMBAR"			},
	{ BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status"	},
	{ BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status"	},
	{ BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address"	},
	{ BMC_BASE + 0xE0, "MPC107 AMBOR Register"		},
	{ BMC_BASE + 0xF0, "MPC107 MCCR1 Register"		},
	{ BMC_BASE + 0xF4, "MPC107 MCCR2 Register"		},
	{ BMC_BASE + 0xF8, "MPC107 MCCR3 Register"		},
	{ BMC_BASE + 0xFC, "MPC107 MCCR4 Register"		},
};
#define N_MPC107_Regs	(sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
#endif /* INCLUDE_MPC107_REPORT */
#endif /* CONFIG_MOUSSE */

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
#ifdef CONFIG_MOUSSE
#ifdef INCLUDE_MPC107_REPORT
	unsigned int tmp = 0, i;
#endif
	/*
	 * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
	 * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
	 * be accessed.
	 */

#ifdef CONFIG_MPC8240			/* only on MPC8240 */
	mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
	/* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
	mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
#endif


#ifdef INCLUDE_MPC107_REPORT
	/* Check MPC824x PCI Device and Vendor ID */
	while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
		printf ("	MPC107: offset=0x%x, val = 0x%x\n",
			BMC_BASE,
			tmp);
	}

	for (i = 0; i < N_MPC107_Regs; i++) {
		printf ("	0x%x/%s = 0x%x\n",
			MPC107Regs[i].iobase,
			MPC107Regs[i].desc,
			mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
	}

	printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
	printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
	printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
	printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
	printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
	printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
	printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
	printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
	printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
	printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
	printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
	printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
	printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
	printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
	printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
	printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
#endif /* INCLUDE_MPC107_REPORT */
#endif /* CONFIG_MOUSSE */
	return (0);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	#include <common.h>
	9	#include <asm/processor.h>
	10	#include <mpc824x.h>
	11
6d0f6bcf JCPV	12	#ifndef CONFIG_SYS_BANK0_ROW
6d0f6bcf JCPV	13	#define CONFIG_SYS_BANK0_ROW 0
c609719b	14	#endif
6d0f6bcf JCPV	15	#ifndef CONFIG_SYS_BANK1_ROW
6d0f6bcf JCPV	16	#define CONFIG_SYS_BANK1_ROW 0
c609719b	17	#endif
6d0f6bcf JCPV	18	#ifndef CONFIG_SYS_BANK2_ROW
6d0f6bcf JCPV	19	#define CONFIG_SYS_BANK2_ROW 0
c609719b	20	#endif
6d0f6bcf JCPV	21	#ifndef CONFIG_SYS_BANK3_ROW
6d0f6bcf JCPV	22	#define CONFIG_SYS_BANK3_ROW 0
c609719b	23	#endif
6d0f6bcf JCPV	24	#ifndef CONFIG_SYS_BANK4_ROW
6d0f6bcf JCPV	25	#define CONFIG_SYS_BANK4_ROW 0
c609719b	26	#endif
6d0f6bcf JCPV	27	#ifndef CONFIG_SYS_BANK5_ROW
6d0f6bcf JCPV	28	#define CONFIG_SYS_BANK5_ROW 0
c609719b	29	#endif
6d0f6bcf JCPV	30	#ifndef CONFIG_SYS_BANK6_ROW
6d0f6bcf JCPV	31	#define CONFIG_SYS_BANK6_ROW 0
c609719b	32	#endif
6d0f6bcf JCPV	33	#ifndef CONFIG_SYS_BANK7_ROW
6d0f6bcf JCPV	34	#define CONFIG_SYS_BANK7_ROW 0
c609719b	35	#endif
6d0f6bcf JCPV	36	#ifndef CONFIG_SYS_DBUS_SIZE2
6d0f6bcf JCPV	37	#define CONFIG_SYS_DBUS_SIZE2 0
c609719b WD	38	#endif
	39
	40	/*
	41	* Breath some life into the CPU...
	42	*
	43	* Set up the memory map,
	44	* initialize a bunch of registers,
	45	*/
	46	void
	47	cpu_init_f (void)
	48	{
	49	/* MOUSSE board is initialized in asm */
bfa5b714	50	#if !defined(CONFIG_MOUSSE)
c609719b WD	51	register unsigned long val;
	52	CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
	53	/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); / /reset PCISR*/
	54
	55	#if defined(CONFIG_MUSENKI) \|\| defined(CONFIG_PN62)
	56	/* Why is this here, you ask? Try, just try setting 0x8000
	57	* in PCIACR with CONFIG_WRITE_HALFWORD()
	58	* this one was a stumper, and we are annoyed
	59	*/
	60
	61	#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
39539887 WD	62	__asm__ __volatile__(" \
	63	stw %2,0(%0)\n \
	64	sync\n \
	65	sth %3,2(%1)\n \
	66	sync\n \
	67	" \
	68	: /* no output */ \
	69	: "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
	70	"r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
	71	);
c609719b	72
39539887	73	M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
c609719b WD	74	#endif
c609719b WD	75
39539887	76	CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
30ce5ab0	77	CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
39539887 WD	78	/*
	79	* Note that although this bit is cleared after a hard reset, it
	80	* must be explicitly set and then cleared by software during
	81	* initialization in order to guarantee correct operation of the
	82	* DLL and the SDRAM_CLK[0:3] signals (if they are used).
	83	*/
	84	CONFIG_READ_BYTE (AMBOR, val);
	85	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	86	CONFIG_WRITE_BYTE(AMBOR, val \| 0x20);
	87	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	88	#ifdef CONFIG_MPC8245
	89	/* silicon bug 28 MPC8245 */
	90	CONFIG_READ_BYTE(AMBOR,val);
	91	CONFIG_WRITE_BYTE(AMBOR,val\|0x1);
	92
8b0bfc68 WD	93	#if 0
	94	/*
	95	* The following bug only affects older (XPC8245) processors.
	96	* DMA transfers initiated by external devices get corrupted due
	97	* to a hardware scheduling problem.
	98	*
	99	* The effect is:
	100	* when transferring X words, the first 32 words are transferred
	101	* OK, the next 3 x 32 words are 'old' data (from previous DMA)
	102	* while the rest of the X words is xferred fine.
	103	*
	104	* Disabling 3 of the 4 32 word hardware buffers solves the problem
	105	* with no significant performance loss.
	106	*/
	107
39539887 WD	108	CONFIG_READ_BYTE(PCMBCR,val);
39539887 WD	109	/* in order not to corrupt data which is being read over the PCI bus
281e00a3	110	* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
39539887 WD	111	* 4.11 in the processor user manual
39539887 WD	112	* */
c609719b	113
39539887 WD	114	#if 1
	115	CONFIG_WRITE_BYTE(PCMBCR,(val\|0xC0)); /* 1 PCMRB */
	116	#else
	117	CONFIG_WRITE_BYTE(PCMBCR,(val\|0x80)); /* 2 PCMRBs */
	118	CONFIG_WRITE_BYTE(PCMBCR,(val\|0x40)); /* 3 PCMRBs */
8b0bfc68 WD	119	/* default, 4 PCMRBs are used */
8b0bfc68 WD	120	#endif
39539887 WD	121	#endif
	122	#endif
	123
	124	CONFIG_READ_WORD(PICR1, val);
c609719b	125	#if defined(CONFIG_MPC8240)
39539887 WD	126	CONFIG_WRITE_WORD( PICR1,
	127	(val & (PICR1_ADDRESS_MAP \| PICR1_RCS0)) \|
	128	PIRC1_MSK \| PICR1_PROC_TYPE_603E \|
	129	PICR1_FLASH_WR_EN \| PICR1_MCP_EN \|
	130	PICR1_CF_DPARK \| PICR1_EN_PCS \|
	131	PICR1_CF_APARK );
c609719b	132	#elif defined(CONFIG_MPC8245)
39539887 WD	133	CONFIG_WRITE_WORD( PICR1,
	134	(val & (PICR1_RCS0)) \|
	135	PICR1_PROC_TYPE_603E \|
	136	PICR1_FLASH_WR_EN \| PICR1_MCP_EN \|
	137	PICR1_CF_DPARK \| PICR1_NO_BUSW_CK \|
	138	PICR1_DEC\| PICR1_CF_APARK \| 0x10); /* 8245 UM says bit 4 must be set */
c609719b WD	139	#else
	140	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	141	#endif
	142
39539887 WD	143	CONFIG_READ_WORD(PICR2, val);
39539887 WD	144	val= val & ~ (PICR2_CF_SNOOP_WS_MASK \| PICR2_CF_APHASE_WS_MASK); /mask off waitstate bits/
c609719b	145	#ifndef CONFIG_PN62
39539887	146	val \|= PICR2_CF_SNOOP_WS_1WS \| PICR2_CF_APHASE_WS_1WS; /1 wait state/
c609719b	147	#endif
39539887	148	CONFIG_WRITE_WORD(PICR2, val);
c609719b	149
6d0f6bcf JCPV	150	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
	151	#ifndef CONFIG_SYS_RAMBOOT
	152	CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) \|
	153	(CONFIG_SYS_BANK0_ROW) \|
	154	(CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) \|
	155	(CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) \|
	156	(CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) \|
	157	(CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) \|
	158	(CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) \|
	159	(CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) \|
	160	(CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) \|
	161	(CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
c609719b WD	162	#endif
c609719b WD	163
6d0f6bcf JCPV	164	#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
	165	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT \|
	166	CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT \|
	167	CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
c609719b	168	#else
6d0f6bcf	169	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
c609719b WD	170	#endif
	171
	172	#if defined(CONFIG_MPC8240)
39539887	173	CONFIG_WRITE_WORD(MCCR3,
6d0f6bcf JCPV	174	(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) \|
	175	(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) \|
	176	(CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT));
c609719b	177	#elif defined(CONFIG_MPC8245)
39539887	178	CONFIG_WRITE_WORD(MCCR3,
6d0f6bcf JCPV	179	(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) \|
6d0f6bcf JCPV	180	(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
c609719b WD	181	#else
	182	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	183	#endif
	184
	185	/* this is gross. We think these should all be the same, and various boards
6d0f6bcf	186	* should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
c609719b WD	187	* its not set, we define it to zero in this file
	188	*/
	189	#if defined(CONFIG_CU824) \|\| defined(CONFIG_PN62)
	190	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	191	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
6d0f6bcf JCPV	192	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
c609719b	193	MCCR4_BIT21 \|
6d0f6bcf JCPV	194	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	195	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	196	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
	197	CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) \|
	198	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) \|
	199	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
c609719b WD	200	#elif defined(CONFIG_MPC8240)
c609719b WD	201	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	202	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
6d0f6bcf JCPV	203	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
c609719b	204	MCCR4_BIT21 \|
6d0f6bcf JCPV	205	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	206	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	207	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
	208	(CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) \|
	209	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
c609719b	210	#elif defined(CONFIG_MPC8245)
39539887 WD	211	CONFIG_READ_WORD(MCCR1, val);
39539887 WD	212	val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
c609719b	213
39539887	214	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	215	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
	216	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
	217	(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) \|
	218	(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) \|
	219	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	220	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	221	(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) \|
	222	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
39539887	223	(val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) \|
6d0f6bcf JCPV	224	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) \|
6d0f6bcf JCPV	225	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
c609719b WD	226	#else
	227	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	228	#endif
	229
39539887	230	CONFIG_WRITE_WORD(MSAR1,
6d0f6bcf JCPV	231	( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	232	(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	233	(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	234	(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	235	CONFIG_WRITE_WORD(EMSAR1,
6d0f6bcf JCPV	236	( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	237	(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	238	(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	239	(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	240	CONFIG_WRITE_WORD(MSAR2,
6d0f6bcf JCPV	241	( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	242	(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	243	(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	244	(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	245	CONFIG_WRITE_WORD(EMSAR2,
6d0f6bcf JCPV	246	( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	247	(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	248	(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	249	(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	250	CONFIG_WRITE_WORD(MEAR1,
6d0f6bcf JCPV	251	( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	252	(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	253	(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	254	(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	255	CONFIG_WRITE_WORD(EMEAR1,
6d0f6bcf JCPV	256	( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	257	(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	258	(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	259	(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	260	CONFIG_WRITE_WORD(MEAR2,
6d0f6bcf JCPV	261	( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	262	(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	263	(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	264	(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	265	CONFIG_WRITE_WORD(EMEAR2,
6d0f6bcf JCPV	266	( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	267	(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	268	(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	269	(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
c609719b	270
6d0f6bcf JCPV	271	CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
	272	#ifdef CONFIG_SYS_DLL_MAX_DELAY
	273	CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */
c609719b	274	#endif
6d0f6bcf JCPV	275	#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
6d0f6bcf JCPV	276	CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND \| CONFIG_SYS_PCI_HOLD_DEL);
c609719b	277	#endif
6d0f6bcf JCPV	278	#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
6d0f6bcf JCPV	279	CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */
c609719b WD	280	#endif /* setup & hold time */
c609719b WD	281
39539887	282	CONFIG_WRITE_BYTE(MBER,
6d0f6bcf JCPV	283	CONFIG_SYS_BANK0_ENABLE \|
	284	(CONFIG_SYS_BANK1_ENABLE << 1) \|
	285	(CONFIG_SYS_BANK2_ENABLE << 2) \|
	286	(CONFIG_SYS_BANK3_ENABLE << 3) \|
	287	(CONFIG_SYS_BANK4_ENABLE << 4) \|
	288	(CONFIG_SYS_BANK5_ENABLE << 5) \|
	289	(CONFIG_SYS_BANK6_ENABLE << 6) \|
	290	(CONFIG_SYS_BANK7_ENABLE << 7));
c609719b	291
6d0f6bcf JCPV	292	#ifdef CONFIG_SYS_PGMAX
6d0f6bcf JCPV	293	CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
c609719b WD	294	#endif
c609719b WD	295
39539887 WD	296	/* ! Wait 200us before initialize other registers */
	297	/FIXME: write a decent udelay wait /
	298	__asm__ __volatile__(
	299	" mtctr %0 \n \
	300	0: bdnz 0b\n"
	301	:
	302	: "r" (0x10000));
c609719b	303
39539887 WD	304	CONFIG_READ_WORD(MCCR1, val);
	305	CONFIG_WRITE_WORD(MCCR1, val \| MCCR1_MEMGO); /* set memory access going */
	306	__asm__ __volatile__("eieio");
c609719b	307
bfa5b714	308	#endif /* !CONFIG_MOUSSE */
c609719b WD	309	}
	310
	311
	312	#ifdef CONFIG_MOUSSE
	313	#ifdef INCLUDE_MPC107_REPORT
39539887 WD	314	struct MPC107_s {
	315	unsigned int iobase;
	316	char desc[120];
	317	} MPC107Regs[] = {
	318	{ BMC_BASE + 0x00, "MPC107 Vendor/Device ID" },
	319	{ BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" },
	320	{ BMC_BASE + 0x08, "MPC107 Revision" },
	321	{ BMC_BASE + 0x0C, "MPC107 Cache Line Size" },
	322	{ BMC_BASE + 0x10, "MPC107 LMBAR" },
	323	{ BMC_BASE + 0x14, "MPC824x PCSR" },
	324	{ BMC_BASE + 0xA8, "MPC824x PICR1" },
	325	{ BMC_BASE + 0xAC, "MPC824x PICR2" },
	326	{ BMC_BASE + 0x46, "MPC824x PACR" },
	327	{ BMC_BASE + 0x310, "MPC824x ITWR" },
	328	{ BMC_BASE + 0x300, "MPC824x OMBAR" },
	329	{ BMC_BASE + 0x308, "MPC824x OTWR" },
	330	{ BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" },
	331	{ BMC_BASE + 0x78, "MPC107 EUMBAR" },
	332	{ BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" },
	333	{ BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" },
	334	{ BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" },
	335	{ BMC_BASE + 0xE0, "MPC107 AMBOR Register" },
	336	{ BMC_BASE + 0xF0, "MPC107 MCCR1 Register" },
	337	{ BMC_BASE + 0xF4, "MPC107 MCCR2 Register" },
	338	{ BMC_BASE + 0xF8, "MPC107 MCCR3 Register" },
	339	{ BMC_BASE + 0xFC, "MPC107 MCCR4 Register" },
c609719b WD	340	};
	341	#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
	342	#endif /* INCLUDE_MPC107_REPORT */
	343	#endif /* CONFIG_MOUSSE */
	344
	345	/*
	346	* initialize higher level parts of CPU like time base and timers
	347	*/
	348	int cpu_init_r (void)
	349	{
	350	#ifdef CONFIG_MOUSSE
	351	#ifdef INCLUDE_MPC107_REPORT
	352	unsigned int tmp = 0, i;
	353	#endif
	354	/*
	355	* Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
	356	* This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
	357	* be accessed.
	358	*/
	359
	360	#ifdef CONFIG_MPC8240 /* only on MPC8240 */
	361	mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
	362	/* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
	363	mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
	364	#endif
	365
	366
	367	#ifdef INCLUDE_MPC107_REPORT
	368	/* Check MPC824x PCI Device and Vendor ID */
	369	while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
	370	printf (" MPC107: offset=0x%x, val = 0x%x\n",
	371	BMC_BASE,
	372	tmp);
	373	}
	374
	375	for (i = 0; i < N_MPC107_Regs; i++) {
	376	printf (" 0x%x/%s = 0x%x\n",
	377	MPC107Regs[i].iobase,
	378	MPC107Regs[i].desc,
	379	mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
	380	}
	381
	382	printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
	383	printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
	384	printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
	385	printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
	386	printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
	387	printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
	388	printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
	389	printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
	390	printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
	391	printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
	392	printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
	393	printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
	394	printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
	395	printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
	396	printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
	397	printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
	398	#endif /* INCLUDE_MPC107_REPORT */
	399	#endif /* CONFIG_MOUSSE */
	400	return (0);
	401	}