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arch/powerpc/cpu/mpc8260/ether_fcc.c: Fix compile warning
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / ether_fcc.c
CommitLineData
affae2bf
WD		 1/*
2 * MPC8260 FCC Fast Ethernet
3 *
4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
5 *
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/*
29 * MPC8260 FCC Fast Ethernet
30 * Basic ET HW initialization and packet RX/TX routines
31 *
32 * This code will not perform the IO port configuration. This should be
33 * done in the iop_conf_t structure specific for the board.
34 *
35 * TODO:
36 * add a PHY driver to do the negotiation
37 * reflect negotiation results in FPSMR
38 * look for ways to configure the board specific stuff elsewhere, eg.
39 * config_xxx.h or the board directory
40 */
41
42#include <common.h>
aacf9a49 43#include <malloc.h>
affae2bf
WD		 44#include <asm/cpm_8260.h>
45#include <mpc8260.h>
affae2bf
WD		 46#include <command.h>
47#include <config.h>
aacf9a49 48#include <net.h>
affae2bf 49
4431283c 50#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
63ff004c
MB		 51#include <miiphy.h>
52#endif
53
d87080b7
WD		 54DECLARE_GLOBAL_DATA_PTR;
55
e2a53458 56#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
affae2bf 57
aacf9a49
WD		 58static struct ether_fcc_info_s
59{
60 int ether_index;
61 int proff_enet;
62 ulong cpm_cr_enet_sblock;
63 ulong cpm_cr_enet_page;
64 ulong cmxfcr_mask;
65 ulong cmxfcr_value;
66}
67 ether_fcc_info[] =
68{
69#ifdef CONFIG_ETHER_ON_FCC1
70{
71 0,
72 PROFF_FCC1,
73 CPM_CR_FCC1_SBLOCK,
74 CPM_CR_FCC1_PAGE,
6d0f6bcf
JCPV		 75 CONFIG_SYS_CMXFCR_MASK1,
76 CONFIG_SYS_CMXFCR_VALUE1
aacf9a49
WD		 77},
78#endif
affae2bf 79
aacf9a49
WD		 80#ifdef CONFIG_ETHER_ON_FCC2
81{
82 1,
83 PROFF_FCC2,
84 CPM_CR_FCC2_SBLOCK,
85 CPM_CR_FCC2_PAGE,
6d0f6bcf
JCPV		 86 CONFIG_SYS_CMXFCR_MASK2,
87 CONFIG_SYS_CMXFCR_VALUE2
aacf9a49
WD		 88},
89#endif
affae2bf 90
aacf9a49
WD		 91#ifdef CONFIG_ETHER_ON_FCC3
92{
93 2,
94 PROFF_FCC3,
95 CPM_CR_FCC3_SBLOCK,
96 CPM_CR_FCC3_PAGE,
6d0f6bcf
JCPV		 97 CONFIG_SYS_CMXFCR_MASK3,
98 CONFIG_SYS_CMXFCR_VALUE3
aacf9a49 99},
affae2bf 100#endif
aacf9a49
WD		 101};
102
affae2bf
WD		 103/*---------------------------------------------------------------------*/
104
105/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
106#define PKT_MAXDMA_SIZE 1520
107
108/* The FCC stores dest/src/type, data, and checksum for receive packets. */
109#define PKT_MAXBUF_SIZE 1518
110#define PKT_MINBUF_SIZE 64
111
112/* Maximum input buffer size. Must be a multiple of 32. */
113#define PKT_MAXBLR_SIZE 1536
114
115#define TOUT_LOOP 1000000
116
117#define TX_BUF_CNT 2
118#ifdef __GNUC__
119static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
120#else
121#error "txbuf must be 64-bit aligned"
122#endif
123
124static uint rxIdx; /* index of the current RX buffer */
125static uint txIdx; /* index of the current TX buffer */
126
127/*
128 * FCC Ethernet Tx and Rx buffer descriptors.
129 * Provide for Double Buffering
130 * Note: PKTBUFSRX is defined in net.h
131 */
132
133typedef volatile struct rtxbd {
134 cbd_t rxbd[PKTBUFSRX];
135 cbd_t txbd[TX_BUF_CNT];
136} RTXBD;
137
138/* Good news: the FCC supports external BDs! */
139#ifdef __GNUC__
140static RTXBD rtx __attribute__ ((aligned(8)));
141#else
142#error "rtx must be 64-bit aligned"
143#endif
144
888fc615 145static int fec_send(struct eth_device *dev, void *packet, int length)
affae2bf
WD		 146{
147 int i;
148 int result = 0;
149
150 if (length <= 0) {
151 printf("fec: bad packet size: %d\n", length);
152 goto out;
153 }
154
155 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
156 if (i >= TOUT_LOOP) {
4b9206ed 157 puts ("fec: tx buffer not ready\n");
affae2bf
WD		 158 goto out;
159 }
160 }
161
162 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
163 rtx.txbd[txIdx].cbd_datlen = length;
164 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
165 BD_ENET_TX_WRAP);
166
167 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
168 if (i >= TOUT_LOOP) {
4b9206ed 169 puts ("fec: tx error\n");
affae2bf
WD		 170 goto out;
171 }
172 }
173
174#ifdef ET_DEBUG
175 printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
176#endif
177
178 /* return only status bits */
179 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
180
181out:
182 return result;
183}
184
aacf9a49 185static int fec_recv(struct eth_device* dev)
affae2bf
WD		 186{
187 int length;
188
189 for (;;)
190 {
191 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
192 length = -1;
193 break; /* nothing received - leave for() loop */
194 }
195 length = rtx.rxbd[rxIdx].cbd_datlen;
196
197 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
198 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
199 }
200 else {
201 /* Pass the packet up to the protocol layers. */
202 NetReceive(NetRxPackets[rxIdx], length - 4);
203 }
204
205
206 /* Give the buffer back to the FCC. */
207 rtx.rxbd[rxIdx].cbd_datlen = 0;
208
209 /* wrap around buffer index when necessary */
210 if ((rxIdx + 1) >= PKTBUFSRX) {
211 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
212 rxIdx = 0;
213 }
214 else {
215 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
216 rxIdx++;
217 }
218 }
219 return length;
220}
221
222
aacf9a49 223static int fec_init(struct eth_device* dev, bd_t *bis)
affae2bf 224{
aacf9a49 225 struct ether_fcc_info_s * info = dev->priv;
affae2bf 226 int i;
6d0f6bcf 227 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
affae2bf
WD		 228 volatile cpm8260_t *cp = &(immr->im_cpm);
229 fcc_enet_t *pram_ptr;
230 unsigned long mem_addr;
231
232#if 0
233 mii_discover_phy();
234#endif
235
236 /* 28.9 - (1-2): ioports have been set up already */
237
238 /* 28.9 - (3): connect FCC's tx and rx clocks */
239 immr->im_cpmux.cmx_uar = 0;
aacf9a49 240 immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
42d1f039 241 info->cmxfcr_value;
affae2bf
WD		 242
243 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
aacf9a49 244 immr->im_fcc[info->ether_index].fcc_gfmr =
affae2bf
WD		 245 FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
246
247 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
6d0f6bcf 248 immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
affae2bf
WD		 249
250 /* 28.9 - (6): FDSR: Ethernet Syn */
aacf9a49 251 immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
affae2bf
WD		 252
253 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
254 rxIdx = 0;
255 txIdx = 0;
256
257 /* Setup Receiver Buffer Descriptors */
258 for (i = 0; i < PKTBUFSRX; i++)
259 {
260 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
261 rtx.rxbd[i].cbd_datlen = 0;
262 rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
263 }
264 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
265
266 /* Setup Ethernet Transmitter Buffer Descriptors */
267 for (i = 0; i < TX_BUF_CNT; i++)
268 {
269 rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
270 rtx.txbd[i].cbd_datlen = 0;
271 rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
272 }
273 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
274
275 /* 28.9 - (7): initialise parameter ram */
aacf9a49 276 pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
affae2bf
WD		 277
278 /* clear whole structure to make sure all reserved fields are zero */
279 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
280
281 /*
282 * common Parameter RAM area
283 *
284 * Allocate space in the reserved FCC area of DPRAM for the
285 * internal buffers. No one uses this space (yet), so we
286 * can do this. Later, we will add resource management for
287 * this area.
288 */
aacf9a49 289 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
affae2bf
WD		 290 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
291 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
292 /*
293 * Set maximum bytes per receive buffer.
294 * It must be a multiple of 32.
295 */
296 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
297 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
6d0f6bcf 298 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
affae2bf
WD		 299 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
300 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
6d0f6bcf 301 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
affae2bf
WD		 302 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
303
304 /* protocol-specific area */
305 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
306 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
307 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
308 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
309 /*
310 * Set Ethernet station address.
311 *
312 * This is supplied in the board information structure, so we
313 * copy that into the controller.
314 * So, far we have only been given one Ethernet address. We make
315 * it unique by setting a few bits in the upper byte of the
316 * non-static part of the address.
317 */
aacf9a49 318#define ea eth_get_dev()->enetaddr
affae2bf
WD		 319 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
320 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
321 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
322#undef ea
323 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
324 /* pad pointer. use tiptr since we don't need a specific padding char */
325 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
326 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
327 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
328 pram_ptr->fen_rfthr = 1;
329 pram_ptr->fen_rfcnt = 1;
330#if 0
331 printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n",
332 pram_ptr->fen_genfcc.fcc_rbase);
333 printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n",
334 pram_ptr->fen_genfcc.fcc_tbase);
335#endif
336
337 /* 28.9 - (8): clear out events in FCCE */
aacf9a49 338 immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
affae2bf
WD		 339
340 /* 28.9 - (9): FCCM: mask all events */
aacf9a49 341 immr->im_fcc[info->ether_index].fcc_fccm = 0;
affae2bf
WD		 342
343 /* 28.9 - (10-12): we don't use ethernet interrupts */
344
345 /* 28.9 - (13)
346 *
347 * Let's re-initialize the channel now. We have to do it later
348 * than the manual describes because we have just now finished
349 * the BD initialization.
350 */
aacf9a49
WD		 351 cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
352 info->cpm_cr_enet_sblock,
affae2bf
WD		 353 0x0c,
354 CPM_CR_INIT_TRX) | CPM_CR_FLG;
355 do {
356 __asm__ __volatile__ ("eieio");
357 } while (cp->cp_cpcr & CPM_CR_FLG);
358
359 /* 28.9 - (14): enable tx/rx in gfmr */
aacf9a49 360 immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
affae2bf
WD		 361
362 return 1;
363}
364
aacf9a49 365static void fec_halt(struct eth_device* dev)
affae2bf 366{
aacf9a49 367 struct ether_fcc_info_s * info = dev->priv;
6d0f6bcf 368 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
affae2bf
WD		 369
370 /* write GFMR: disable tx/rx */
aacf9a49 371 immr->im_fcc[info->ether_index].fcc_gfmr &=
affae2bf
WD		 372 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
373}
374
aacf9a49
WD		 375int fec_initialize(bd_t *bis)
376{
377 struct eth_device* dev;
378 int i;
379
380 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
381 {
382 dev = (struct eth_device*) malloc(sizeof *dev);
383 memset(dev, 0, sizeof *dev);
384
48690d80 385 sprintf(dev->name, "FCC%d",
42d1f039 386 ether_fcc_info[i].ether_index + 1);
aacf9a49
WD		 387 dev->priv = &ether_fcc_info[i];
388 dev->init = fec_init;
389 dev->halt = fec_halt;
390 dev->send = fec_send;
391 dev->recv = fec_recv;
392
393 eth_register(dev);
63ff004c 394
4431283c 395#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
63ff004c
MB		 396 && defined(CONFIG_BITBANGMII)
397 miiphy_register(dev->name,
398 bb_miiphy_read, bb_miiphy_write);
399#endif
aacf9a49
WD		 400 }
401
402 return 1;
403}
404
6dd652fa
WD		 405#ifdef CONFIG_ETHER_LOOPBACK_TEST
406
407#define ELBT_BUFSZ 1024 /* must be multiple of 32 */
408
409#define ELBT_CRCSZ 4
410
411#define ELBT_NRXBD 4 /* must be at least 2 */
412#define ELBT_NTXBD 4
413
414#define ELBT_MAXRXERR 32
415#define ELBT_MAXTXERR 32
416
417#define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */
418
419typedef
420 struct {
421 uint off;
422 char *lab;
423 }
424elbt_prdesc;
425
426typedef
427 struct {
428 uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl;
429 uint badsrc, badtyp, badlen, badbit;
430 }
431elbt_rxeacc;
432
433static elbt_prdesc rxeacc_descs[] = {
434 { offsetof(elbt_rxeacc, _l), "Not Last in Frame" },
435 { offsetof(elbt_rxeacc, _f), "Not First in Frame" },
436 { offsetof(elbt_rxeacc, m), "Address Miss" },
437 { offsetof(elbt_rxeacc, bc), "Broadcast Address" },
438 { offsetof(elbt_rxeacc, mc), "Multicast Address" },
439 { offsetof(elbt_rxeacc, lg), "Frame Length Violation"},
440 { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" },
441 { offsetof(elbt_rxeacc, sh), "Short Frame" },
442 { offsetof(elbt_rxeacc, cr), "CRC Error" },
443 { offsetof(elbt_rxeacc, ov), "Overrun" },
444 { offsetof(elbt_rxeacc, cl), "Collision" },
445 { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" },
446 { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" },
447 { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" },
448 { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" },
449};
450static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
451
452typedef
453 struct {
454 uint def, hb, lc, rl, rc, un, csl;
455 }
456elbt_txeacc;
457
458static elbt_prdesc txeacc_descs[] = {
459 { offsetof(elbt_txeacc, def), "Defer Indication" },
460 { offsetof(elbt_txeacc, hb), "Heartbeat" },
461 { offsetof(elbt_txeacc, lc), "Late Collision" },
462 { offsetof(elbt_txeacc, rl), "Retransmission Limit" },
463 { offsetof(elbt_txeacc, rc), "Retry Count" },
464 { offsetof(elbt_txeacc, un), "Underrun" },
465 { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" },
466};
467static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
468
469typedef
470 struct {
471 uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ];
472 uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ];
473 cbd_t rxbd[ELBT_NRXBD];
474 cbd_t txbd[ELBT_NTXBD];
475 enum { Idle, Running, Closing, Closed } state;
476 int proff, page, sblock;
477 uint clstime, nsent, ntxerr, nrcvd, nrxerr;
478 ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR];
479 elbt_rxeacc rxeacc;
480 elbt_txeacc txeacc;
481 } __attribute__ ((aligned(8)))
482elbt_chan;
483
484static uchar patbytes[ELBT_NTXBD] = {
485 0xff, 0xaa, 0x55, 0x00
486};
487static uint patwords[ELBT_NTXBD] = {
488 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000
489};
490
491#ifdef __GNUC__
492static elbt_chan elbt_chans[3] __attribute__ ((aligned(8)));
493#else
494#error "elbt_chans must be 64-bit aligned"
495#endif
496
497#define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005)
498
499static elbt_prdesc epram_descs[] = {
500 { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" },
501 { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" },
502 { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" },
503 { offsetof(fcc_enet_t, fen_octc), "Octets" },
504 { offsetof(fcc_enet_t, fen_colc), "Collisions" },
505 { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" },
506 { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" },
507 { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" },
508 { offsetof(fcc_enet_t, fen_frgc), "Fragments" },
509 { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" },
510 { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" },
511 { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" },
512 { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" },
513 { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" },
514 { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" },
515 { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" },
516 { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"},
517};
518static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
519
520/*
521 * given an elbt_prdesc array and an array of base addresses, print
522 * each prdesc down the screen with the values fetched from each
523 * base address across the screen
524 */
525static void
526print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase)
527{
528 elbt_prdesc *dp = descs, *edp = dp + ndesc;
529 int i;
530
531 printf ("%32s", "");
532
533 for (i = 0; i < nbase; i++)
534 printf (" Channel %d", i);
535
4b9206ed 536 putc ('\n');
6dd652fa
WD		 537
538 while (dp < edp) {
539
540 printf ("%-32s", dp->lab);
541
542 for (i = 0; i < nbase; i++) {
543 uint val = *(uint *)(bases[i] + dp->off);
544
545 printf (" %10u", val);
546 }
547
4b9206ed 548 putc ('\n');
6dd652fa
WD		 549
550 dp++;
551 }
552}
553
554/*
555 * return number of bits that are set in a value; value contains
556 * nbits (right-justified) bits.
557 */
558static uint __inline__
559nbs (uint value, uint nbits)
560{
561 uint cnt = 0;
562#if 1
563 uint pos = sizeof (uint) * 8;
564
565 __asm__ __volatile__ ("\
566 mtctr %2\n\
5671: rlwnm. %2,%1,%4,31,31\n\
568 beq 2f\n\
569 addi %0,%0,1\n\
5702: subi %4,%4,1\n\
571 bdnz 1b"
572 : "=r"(cnt)
573 : "r"(value), "r"(nbits), "r"(cnt), "r"(pos)
574 : "ctr", "cc" );
575#else
576 uint mask = 1;
577
578 do {
579 if (value & mask)
580 cnt++;
581 mask <<= 1;
582 } while (--nbits);
583#endif
584
585 return (cnt);
586}
587
588static ulong
589badbits (uchar *bp, int n, ulong pat)
590{
591 ulong *lp, cnt = 0;
592 int nl;
593
594 while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) {
595 uchar diff;
596
597 diff = *bp++ ^ (uchar)pat;
598
599 if (diff)
600 cnt += nbs ((ulong)diff, 8);
601
602 n--;
603 }
604
605 lp = (ulong *)bp;
606 nl = n / sizeof (ulong);
607 n -= nl * sizeof (ulong);
608
609 while (nl > 0) {
610 ulong diff;
611
612 diff = *lp++ ^ pat;
613
614 if (diff)
615 cnt += nbs (diff, 32);
616
617 nl--;
618 }
619
620 bp = (uchar *)lp;
621
622 while (n > 0) {
623 uchar diff;
624
625 diff = *bp++ ^ (uchar)pat;
626
627 if (diff)
628 cnt += nbs ((ulong)diff, 8);
629
630 n--;
631 }
632
633 return (cnt);
634}
635
636static inline unsigned short
637swap16 (unsigned short x)
638{
639 return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
640}
641
6dfa434e
WD		 642/* broadcast is not an error - we send them like that */
643#define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC)
644
6dd652fa
WD		 645void
646eth_loopback_test (void)
647{
6d0f6bcf 648 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
6dd652fa
WD		 649 volatile cpm8260_t *cp = &(immr->im_cpm);
650 int c, nclosed;
651 ulong runtime, nmsec;
652 uchar *bases[3];
653
654 puts ("FCC Ethernet External loopback test\n");
655
6bacfa6a 656 eth_getenv_enetaddr("ethaddr", NetOurEther);
6dd652fa
WD		 657
658 /*
659 * global initialisations for all FCC channels
660 */
661
662 /* 28.9 - (1-2): ioports have been set up already */
663
664#if defined(CONFIG_HYMOD)
65bd0e28
WD		 665 /*
666 * Attention: this is board-specific
42d1f039
WD		 667 * 0, FCC1
668 * 1, FCC2
669 * 2, FCC3
670 */
65bd0e28
WD		 671# define FCC_START_LOOP 0
672# define FCC_END_LOOP 2
673
6dd652fa
WD		 674 /*
675 * Attention: this is board-specific
676 * - FCC1 Rx-CLK is CLK10
677 * - FCC1 Tx-CLK is CLK11
678 * - FCC2 Rx-CLK is CLK13
679 * - FCC2 Tx-CLK is CLK14
680 * - FCC3 Rx-CLK is CLK15
681 * - FCC3 Tx-CLK is CLK16
682 */
683
684 /* 28.9 - (3): connect FCC's tx and rx clocks */
685 immr->im_cpmux.cmx_uar = 0;
686 immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
687 CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
688 CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
b30d41ca 689#elif defined(CONFIG_SACSng)
65bd0e28
WD		 690 /*
691 * Attention: this is board-specific
42d1f039
WD		 692 * 1, FCC2
693 */
65bd0e28
WD		 694# define FCC_START_LOOP 1
695# define FCC_END_LOOP 1
696
697 /*
698 * Attention: this is board-specific
699 * - FCC2 Rx-CLK is CLK13
700 * - FCC2 Tx-CLK is CLK14
701 */
702
703 /* 28.9 - (3): connect FCC's tx and rx clocks */
704 immr->im_cpmux.cmx_uar = 0;
705 immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
6dd652fa
WD		 706#else
707#error "eth_loopback_test not supported on your board"
708#endif
709
710 puts ("Initialise FCC channels:");
711
65bd0e28 712 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
6dd652fa
WD		 713 elbt_chan *ecp = &elbt_chans[c];
714 volatile fcc_t *fcp = &immr->im_fcc[c];
715 volatile fcc_enet_t *fpp;
716 int i;
717 ulong addr;
718
719 /*
720 * initialise channel data
721 */
722
723 printf (" %d", c);
724
725 memset ((void *)ecp, 0, sizeof (*ecp));
726
727 ecp->state = Idle;
728
729 switch (c) {
730
731 case 0: /* FCC1 */
732 ecp->proff = PROFF_FCC1;
733 ecp->page = CPM_CR_FCC1_PAGE;
734 ecp->sblock = CPM_CR_FCC1_SBLOCK;
735 break;
736
737 case 1: /* FCC2 */
738 ecp->proff = PROFF_FCC2;
739 ecp->page = CPM_CR_FCC2_PAGE;
740 ecp->sblock = CPM_CR_FCC2_SBLOCK;
741 break;
742
743 case 2: /* FCC3 */
744 ecp->proff = PROFF_FCC3;
745 ecp->page = CPM_CR_FCC3_PAGE;
746 ecp->sblock = CPM_CR_FCC3_SBLOCK;
747 break;
748 }
749
750 /*
751 * set up tx buffers and bds
752 */
753
754 for (i = 0; i < ELBT_NTXBD; i++) {
755 cbd_t *bdp = &ecp->txbd[i];
756 uchar *bp = &ecp->txbufs[i][0];
757
758 bdp->cbd_bufaddr = (uint)bp;
759 /* room for crc */
760 bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ;
761 bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
762 BD_ENET_TX_LAST | BD_ENET_TX_TC;
763
764 memset ((void *)bp, patbytes[i], ELBT_BUFSZ);
765 NetSetEther (bp, NetBcastAddr, 0x8000);
766 }
767 ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
768
769 /*
770 * set up rx buffers and bds
771 */
772
773 for (i = 0; i < ELBT_NRXBD; i++) {
774 cbd_t *bdp = &ecp->rxbd[i];
775 uchar *bp = &ecp->rxbufs[i][0];
776
777 bdp->cbd_bufaddr = (uint)bp;
778 bdp->cbd_datlen = 0;
779 bdp->cbd_sc = BD_ENET_RX_EMPTY;
780
781 memset ((void *)bp, 0, ELBT_BUFSZ);
782 }
783 ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP;
784
785 /*
786 * set up the FCC channel hardware
787 */
788
789 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
790 fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
791
792 /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */
793 fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \
794 FCC_PSMR_ENCRC | FCC_PSMR_PRO | \
795 FCC_PSMR_MON | FCC_PSMR_RSH;
796
797 /* 28.9 - (6): FDSR: Ethernet Syn */
798 fcp->fcc_fdsr = 0xD555;
799
800 /* 29.9 - (7): initialise parameter ram */
801 fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]);
802
803 /* clear whole struct to make sure all resv fields are zero */
804 memset ((void *)fpp, 0, sizeof (fcc_enet_t));
805
806 /*
807 * common Parameter RAM area
808 *
809 * Allocate space in the reserved FCC area of DPRAM for the
810 * internal buffers. No one uses this space (yet), so we
811 * can do this. Later, we will add resource management for
812 * this area.
813 */
814 addr = CPM_FCC_SPECIAL_BASE + (c * 64);
815 fpp->fen_genfcc.fcc_riptr = addr;
816 fpp->fen_genfcc.fcc_tiptr = addr + 32;
817
818 /*
819 * Set maximum bytes per receive buffer.
820 * It must be a multiple of 32.
821 * buffers are in 60x bus memory.
822 */
823 fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
824 fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
825 fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]);
826 fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
827 fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]);
828
829 /* protocol-specific area */
830 fpp->fen_cmask = 0xdebb20e3; /* CRC mask */
831 fpp->fen_cpres = 0xffffffff; /* CRC preset */
832 fpp->fen_retlim = 15; /* Retry limit threshold */
833 fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */
834
835 /*
836 * Set Ethernet station address.
837 *
838 * This is supplied in the board information structure, so we
839 * copy that into the controller.
840 * So, far we have only been given one Ethernet address. We use
841 * the same address for all channels
842 */
6bacfa6a 843#define ea NetOurEther
6dd652fa
WD		 844 fpp->fen_paddrh = (ea[5] << 8) + ea[4];
845 fpp->fen_paddrm = (ea[3] << 8) + ea[2];
846 fpp->fen_paddrl = (ea[1] << 8) + ea[0];
847#undef ea
848
849 fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
850 /*
851 * pad pointer. use tiptr since we don't need
852 * a specific padding char
853 */
854 fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr;
855 fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */
856 fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */
857 fpp->fen_rfthr = 1;
858 fpp->fen_rfcnt = 1;
859
860 /* 28.9 - (8): clear out events in FCCE */
861 fcp->fcc_fcce = ~0x0;
862
863 /* 28.9 - (9): FCCM: mask all events */
864 fcp->fcc_fccm = 0;
865
866 /* 28.9 - (10-12): we don't use ethernet interrupts */
867
868 /* 28.9 - (13)
869 *
870 * Let's re-initialize the channel now. We have to do it later
871 * than the manual describes because we have just now finished
872 * the BD initialization.
873 */
874 cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \
875 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG;
876 do {
877 __asm__ __volatile__ ("eieio");
878 } while (cp->cp_cpcr & CPM_CR_FLG);
879 }
880
881 puts (" done\nStarting test... (Ctrl-C to Finish)\n");
882
883 /*
884 * Note: don't want serial output from here until the end of the
885 * test - the delays would probably stuff things up.
886 */
887
888 clear_ctrlc ();
889 runtime = get_timer (0);
890
891 do {
892 nclosed = 0;
893
65bd0e28 894 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
6dd652fa
WD		 895 volatile fcc_t *fcp = &immr->im_fcc[c];
896 elbt_chan *ecp = &elbt_chans[c];
897 int i;
898
899 switch (ecp->state) {
900
901 case Idle:
902 /*
903 * set the channel Running ...
904 */
905
906 /* 28.9 - (14): enable tx/rx in gfmr */
907 fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
908
909 ecp->state = Running;
910 break;
911
912 case Running:
913 /*
914 * (while Running only) check for
915 * termination of the test
916 */
917
918 (void)ctrlc ();
919
920 if (had_ctrlc ()) {
921 /*
922 * initiate a "graceful stop transmit"
923 * on the channel
924 */
925 cp->cp_cpcr = mk_cr_cmd (ecp->page, \
926 ecp->sblock, 0x0c, \
927 CPM_CR_GRACEFUL_STOP_TX) | \
928 CPM_CR_FLG;
929 do {
930 __asm__ __volatile__ ("eieio");
931 } while (cp->cp_cpcr & CPM_CR_FLG);
932
933 ecp->clstime = get_timer (0);
934 ecp->state = Closing;
935 }
936 /* fall through ... */
937
938 case Closing:
939 /*
940 * (while Running or Closing) poll the channel:
941 * - check for any non-READY tx buffers and
942 * make them ready
943 * - check for any non-EMPTY rx buffers and
944 * check that they were received correctly,
945 * adjust counters etc, then make empty
946 */
947
948 for (i = 0; i < ELBT_NTXBD; i++) {
949 cbd_t *bdp = &ecp->txbd[i];
950 ushort sc = bdp->cbd_sc;
951
952 if ((sc & BD_ENET_TX_READY) != 0)
953 continue;
954
955 /*
956 * this frame has finished
957 * transmitting
958 */
959 ecp->nsent++;
960
961 if (sc & BD_ENET_TX_STATS) {
962 ulong n;
963
964 /*
965 * we had an error on
966 * the transmission
967 */
968 n = ecp->ntxerr++;
969 if (n < ELBT_MAXTXERR)
970 ecp->txerrs[n] = sc;
971
972 if (sc & BD_ENET_TX_DEF)
973 ecp->txeacc.def++;
974 if (sc & BD_ENET_TX_HB)
975 ecp->txeacc.hb++;
976 if (sc & BD_ENET_TX_LC)
977 ecp->txeacc.lc++;
978 if (sc & BD_ENET_TX_RL)
979 ecp->txeacc.rl++;
980 if (sc & BD_ENET_TX_RCMASK)
981 ecp->txeacc.rc++;
982 if (sc & BD_ENET_TX_UN)
983 ecp->txeacc.un++;
984 if (sc & BD_ENET_TX_CSL)
985 ecp->txeacc.csl++;
986
987 bdp->cbd_sc &= \
988 ~BD_ENET_TX_STATS;
989 }
990
991 if (ecp->state == Closing)
992 ecp->clstime = get_timer (0);
993
994 /* make it ready again */
995 bdp->cbd_sc |= BD_ENET_TX_READY;
996 }
997
998 for (i = 0; i < ELBT_NRXBD; i++) {
999 cbd_t *bdp = &ecp->rxbd[i];
1000 ushort sc = bdp->cbd_sc, mask;
1001
1002 if ((sc & BD_ENET_RX_EMPTY) != 0)
1003 continue;
1004
1005 /* we have a new frame in this buffer */
1006 ecp->nrcvd++;
1007
1008 mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST;
1009 if ((sc & mask) != mask) {
1010 /* somethings wrong here ... */
1011 if (!(sc & BD_ENET_RX_LAST))
1012 ecp->rxeacc._l++;
1013 if (!(sc & BD_ENET_RX_FIRST))
1014 ecp->rxeacc._f++;
1015 }
1016
6dfa434e 1017 if (sc & BD_ENET_RX_ERRS) {
6dd652fa
WD		 1018 ulong n;
1019
1020 /*
1021 * we had some sort of error
1022 * on the frame
1023 */
1024 n = ecp->nrxerr++;
1025 if (n < ELBT_MAXRXERR)
1026 ecp->rxerrs[n] = sc;
1027
1028 if (sc & BD_ENET_RX_MISS)
1029 ecp->rxeacc.m++;
1030 if (sc & BD_ENET_RX_BC)
1031 ecp->rxeacc.bc++;
1032 if (sc & BD_ENET_RX_MC)
1033 ecp->rxeacc.mc++;
1034 if (sc & BD_ENET_RX_LG)
1035 ecp->rxeacc.lg++;
1036 if (sc & BD_ENET_RX_NO)
1037 ecp->rxeacc.no++;
1038 if (sc & BD_ENET_RX_SH)
1039 ecp->rxeacc.sh++;
1040 if (sc & BD_ENET_RX_CR)
1041 ecp->rxeacc.cr++;
1042 if (sc & BD_ENET_RX_OV)
1043 ecp->rxeacc.ov++;
1044 if (sc & BD_ENET_RX_CL)
1045 ecp->rxeacc.cl++;
1046
1047 bdp->cbd_sc &= \
6dfa434e 1048 ~BD_ENET_RX_ERRS;
6dd652fa
WD		 1049 }
1050 else {
1051 ushort datlen = bdp->cbd_datlen;
1052 Ethernet_t *ehp;
1053 ushort prot;
1054 int ours, tb, n, nbytes;
1055
1056 ehp = (Ethernet_t *) \
1057 &ecp->rxbufs[i][0];
1058
1059 ours = memcmp (ehp->et_src, \
1060 NetOurEther, 6);
1061
1062 prot = swap16 (ehp->et_protlen);
1063 tb = prot & 0x8000;
1064 n = prot & 0x7fff;
1065
1066 nbytes = ELBT_BUFSZ - \
1067 offsetof (Ethernet_t, \
1068 et_dsap) - \
1069 ELBT_CRCSZ;
1070
1071 /* check the frame is correct */
1072 if (datlen != ELBT_BUFSZ)
1073 ecp->rxeacc.badlen++;
1074 else if (!ours)
1075 ecp->rxeacc.badsrc++;
1076 else if (!tb || n >= ELBT_NTXBD)
1077 ecp->rxeacc.badtyp++;
1078 else {
1079 ulong patword = \
1080 patwords[n];
1081 uint nbb;
1082
1083 nbb = badbits ( \
1084 &ehp->et_dsap, \
1085 nbytes, \
1086 patword);
1087
1088 ecp->rxeacc.badbit += \
1089 nbb;
1090 }
1091 }
1092
1093 if (ecp->state == Closing)
1094 ecp->clstime = get_timer (0);
1095
1096 /* make it empty again */
1097 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
1098 }
1099
1100 if (ecp->state != Closing)
1101 break;
1102
1103 /*
1104 * (while Closing) check to see if
1105 * waited long enough
1106 */
1107
1108 if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) {
1109 /* write GFMR: disable tx/rx */
1110 fcp->fcc_gfmr &= \
1111 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
1112 ecp->state = Closed;
1113 }
1114
1115 break;
1116
1117 case Closed:
1118 nclosed++;
1119 break;
1120 }
1121 }
1122
65bd0e28 1123 } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
6dd652fa
WD		 1124
1125 runtime = get_timer (runtime);
1126 if (runtime <= ELBT_CLSWAIT) {
1127 printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n",
1128 runtime, ELBT_CLSWAIT);
1129 return;
1130 }
1131 nmsec = runtime - ELBT_CLSWAIT;
1132
1133 printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n",
1134 nmsec, ELBT_CLSWAIT);
1135
1136 /*
1137 * now print stats
1138 */
1139
65bd0e28 1140 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
6dd652fa
WD		 1141 elbt_chan *ecp = &elbt_chans[c];
1142 uint rxpps, txpps, nerr;
1143
1144 rxpps = (ecp->nrcvd * 1000) / nmsec;
1145 txpps = (ecp->nsent * 1000) / nmsec;
1146
1147 printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), "
1148 "%d sent (%d pps, %d txerrs)\n\n", c,
1149 ecp->nrcvd, rxpps, ecp->nrxerr,
1150 ecp->nsent, txpps, ecp->ntxerr);
1151
1152 if ((nerr = ecp->nrxerr) > 0) {
1153 ulong i;
1154
1155 printf ("\tFirst %d rx errs:", nerr);
1156 for (i = 0; i < nerr; i++)
1157 printf (" %04x", ecp->rxerrs[i]);
4b9206ed 1158 putc ('\n');
6dd652fa
WD		 1159 }
1160
1161 if ((nerr = ecp->ntxerr) > 0) {
1162 ulong i;
1163
1164 printf ("\tFirst %d tx errs:", nerr);
1165 for (i = 0; i < nerr; i++)
1166 printf (" %04x", ecp->txerrs[i]);
4b9206ed 1167 putc ('\n');
6dd652fa
WD		 1168 }
1169 }
1170
1171 puts ("Receive Error Counts:\n");
65bd0e28 1172 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
6dd652fa
WD		 1173 bases[c] = (uchar *)&elbt_chans[c].rxeacc;
1174 print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
1175
1176 puts ("\nTransmit Error Counts:\n");
65bd0e28 1177 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
6dd652fa
WD		 1178 bases[c] = (uchar *)&elbt_chans[c].txeacc;
1179 print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
1180
1181 puts ("\nRMON(-like) Counters:\n");
65bd0e28 1182 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
6dd652fa
WD		 1183 bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
1184 print_desc (epram_descs, epram_ndesc, bases, 3);
1185}
1186
1187#endif /* CONFIG_ETHER_LOOPBACK_TEST */
1188
068b60a0 1189#endif
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