[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / ether_scc.c

/*
 * MPC8260 SCC Ethernet
 *
 * Copyright (c) 2000 MontaVista Software, Inc.   Dan Malek (dmalek@jlc.net)
 *
 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright (c) 2001
 * Advent Networks, Inc. <http://www.adventnetworks.com>
 * Jay Monkman <jtm@smoothsmoothie.com>
 *
 * Modified so that it plays nicely when more than one ETHERNET interface
 * is in use a la ether_fcc.c.
 * (C) Copyright 2008
 * DENX Software Engineerin GmbH
 * Gary Jennejohn <garyj@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/cpm_8260.h>
#include <mpc8260.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <config.h>

#if (CONFIG_ETHER_INDEX == 1)
#  define PROFF_ENET            PROFF_SCC1
#  define CPM_CR_ENET_PAGE      CPM_CR_SCC1_PAGE
#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC1_SBLOCK
#  define CMXSCR_MASK          (CMXSCR_SC1          |\
				CMXSCR_RS1CS_MSK    |\
				CMXSCR_TS1CS_MSK)

#elif (CONFIG_ETHER_INDEX == 2)
#  define PROFF_ENET            PROFF_SCC2
#  define CPM_CR_ENET_PAGE      CPM_CR_SCC2_PAGE
#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC2_SBLOCK
#  define CMXSCR_MASK          (CMXSCR_SC2          |\
				CMXSCR_RS2CS_MSK    |\
				CMXSCR_TS2CS_MSK)

#elif (CONFIG_ETHER_INDEX == 3)
#  define PROFF_ENET            PROFF_SCC3
#  define CPM_CR_ENET_PAGE      CPM_CR_SCC3_PAGE
#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC3_SBLOCK
#  define CMXSCR_MASK          (CMXSCR_SC3          |\
				CMXSCR_RS3CS_MSK    |\
				CMXSCR_TS3CS_MSK)
#elif (CONFIG_ETHER_INDEX == 4)
#  define PROFF_ENET            PROFF_SCC4
#  define CPM_CR_ENET_PAGE      CPM_CR_SCC4_PAGE
#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC4_SBLOCK
#  define CMXSCR_MASK          (CMXSCR_SC4          |\
				CMXSCR_RS4CS_MSK    |\
				CMXSCR_TS4CS_MSK)

#endif


/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH  1520

#define TX_BUF_CNT 2

#if !defined(CONFIG_SYS_SCC_TOUT_LOOP)
  #define CONFIG_SYS_SCC_TOUT_LOOP 1000000
#endif

static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];

static uint rxIdx;      /* index of the current RX buffer */
static uint txIdx;      /* index of the current TX buffer */

/*
 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
 *  immr->udata_bd address on Dual-Port RAM
 * Provide for Double Buffering
 */

typedef volatile struct CommonBufferDescriptor {
    cbd_t rxbd[PKTBUFSRX];         /* Rx BD */
    cbd_t txbd[TX_BUF_CNT];        /* Tx BD */
} RTXBD;

static RTXBD *rtx;


static int sec_send(struct eth_device *dev, void *packet, int length)
{
    int i;
    int result = 0;

    if (length <= 0) {
	printf("scc: bad packet size: %d\n", length);
	goto out;
    }

    for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
	if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
	    puts ("scc: tx buffer not ready\n");
	    goto out;
	}
    }

    rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
    rtx->txbd[txIdx].cbd_datlen = length;
    rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
				BD_ENET_TX_WRAP);

    for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
	if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
	    puts ("scc: tx error\n");
	    goto out;
	}
    }

    /* return only status bits */
    result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;

 out:
    return result;
}


static int sec_rx(struct eth_device *dev)
{
    int length;

    for (;;)
    {
	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
	    length = -1;
	    break;     /* nothing received - leave for() loop */
	}

	length = rtx->rxbd[rxIdx].cbd_datlen;

	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
	{
	    printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
	}
	else
	{
	    /* Pass the packet up to the protocol layers. */
	    NetReceive(NetRxPackets[rxIdx], length - 4);
	}


	/* Give the buffer back to the SCC. */
	rtx->rxbd[rxIdx].cbd_datlen = 0;

	/* wrap around buffer index when necessary */
	if ((rxIdx + 1) >= PKTBUFSRX) {
	    rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
					       BD_ENET_RX_EMPTY);
	    rxIdx = 0;
	}
	else {
	    rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
	    rxIdx++;
	}
    }
    return length;
}

/**************************************************************
 *
 * SCC Ethernet Initialization Routine
 *
 *************************************************************/

static int sec_init(struct eth_device *dev, bd_t *bis)
{
    int i;
    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
    scc_enet_t *pram_ptr;
    uint dpaddr;
    uchar ea[6];

    rxIdx = 0;
    txIdx = 0;

    /*
     * Assign static pointer to BD area.
     * Avoid exhausting DPRAM, which would cause a panic.
     */
    if (rtx == NULL) {
	    dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
	    rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
    }

    /* 24.21 - (1-3): ioports have been set up already */

    /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
    immr->im_cpmux.cmx_uar = 0;
    immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
			       CONFIG_SYS_CMXSCR_VALUE);


    /* 24.21 (6) write RBASE and TBASE to parameter RAM */
    pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
    pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
    pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);

    pram_ptr->sen_genscc.scc_rfcr = 0x18;  /* Nrml Ops and Mot byte ordering */
    pram_ptr->sen_genscc.scc_tfcr = 0x18;  /* Mot byte ordering, Nrml access */

    pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */

    pram_ptr->sen_cpres  = ~(0x0);        /* Preset CRC */
    pram_ptr->sen_cmask  = 0xdebb20e3;    /* Constant Mask for CRC */


    /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
    while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
    immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
				     CPM_CR_ENET_SBLOCK,
				     0x0c,
				     CPM_CR_INIT_TRX) | CPM_CR_FLG;

    /* 24.21 - (8-18): Set up parameter RAM */
    pram_ptr->sen_crcec  = 0x0;           /* Error Counter CRC (unused) */
    pram_ptr->sen_alec   = 0x0;           /* Align Error Counter (unused) */
    pram_ptr->sen_disfc  = 0x0;           /* Discard Frame Counter (unused) */

    pram_ptr->sen_pads   = 0x8888;        /* Short Frame PAD Characters */

    pram_ptr->sen_retlim = 15;            /* Retry Limit Threshold */

    pram_ptr->sen_maxflr = 1518;  /* MAX Frame Length Register */
    pram_ptr->sen_minflr = 64;            /* MIN Frame Length Register */

    pram_ptr->sen_maxd1  = DBUF_LENGTH;   /* MAX DMA1 Length Register */
    pram_ptr->sen_maxd2  = DBUF_LENGTH;   /* MAX DMA2 Length Register */

    pram_ptr->sen_gaddr1 = 0x0;   /* Group Address Filter 1 (unused) */
    pram_ptr->sen_gaddr2 = 0x0;   /* Group Address Filter 2 (unused) */
    pram_ptr->sen_gaddr3 = 0x0;   /* Group Address Filter 3 (unused) */
    pram_ptr->sen_gaddr4 = 0x0;   /* Group Address Filter 4 (unused) */

    eth_getenv_enetaddr("ethaddr", ea);
    pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
    pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
    pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];

    pram_ptr->sen_pper   = 0x0;   /* Persistence (unused) */

    pram_ptr->sen_iaddr1 = 0x0;   /* Individual Address Filter 1 (unused) */
    pram_ptr->sen_iaddr2 = 0x0;   /* Individual Address Filter 2 (unused) */
    pram_ptr->sen_iaddr3 = 0x0;   /* Individual Address Filter 3 (unused) */
    pram_ptr->sen_iaddr4 = 0x0;   /* Individual Address Filter 4 (unused) */

    pram_ptr->sen_taddrh = 0x0;   /* Tmp Address (MSB) (unused) */
    pram_ptr->sen_taddrm = 0x0;   /* Tmp Address (unused) */
    pram_ptr->sen_taddrl = 0x0;   /* Tmp Address (LSB) (unused) */

    /* 24.21 - (19): Initialize RxBD */
    for (i = 0; i < PKTBUFSRX; i++)
    {
	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	rtx->rxbd[i].cbd_datlen = 0;                  /* Reset */
	rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
    }

    rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

    /* 24.21 - (20): Initialize TxBD */
    for (i = 0; i < TX_BUF_CNT; i++)
    {
	rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD  |
			       BD_ENET_TX_LAST |
			       BD_ENET_TX_TC);
	rtx->txbd[i].cbd_datlen = 0;                  /* Reset */
	rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
    }

    rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;

    /* 24.21 - (21): Write 0xffff to SCCE */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);

    /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
						   SCCE_ENET_RXF |
						   SCCE_ENET_TXB);

    /* 24.21 - (23): we don't use ethernet interrupts */

    /* 24.21 - (24): Clear GSMR_H to enable normal operations */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;

    /* 24.21 - (25): Clear GSMR_L to enable normal operations */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI        |
						    SCC_GSMRL_TPL_48     |
						    SCC_GSMRL_TPP_10     |
						    SCC_GSMRL_MODE_ENET);

    /* 24.21 - (26): Initialize DSR */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;

    /* 24.21 - (27): Initialize PSMR2
     *
     * Settings:
     *	CRC = 32-Bit CCITT
     *	NIB = Begin searching for SFD 22 bits after RENA
     *	FDE = Full Duplex Enable
     *	BRO = Reject broadcast packets
     *	PROMISCOUS = Catch all packets regardless of dest. MAC adress
     */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr   =	SCC_PSMR_ENCRC	|
							SCC_PSMR_NIB22	|
#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
							SCC_PSMR_FDE	|
#endif
#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
							SCC_PSMR_BRO	|
#endif
#if defined(CONFIG_SCC_ENET_PROMISCOUS)
							SCC_PSMR_PRO	|
#endif
							0;

    /* 24.21 - (28): Write to GSMR_L to enable SCC */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
						     SCC_GSMRL_ENT);

    return 0;
}


static void sec_halt(struct eth_device *dev)
{
    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
						      SCC_GSMRL_ENT);
}

#if 0
static void sec_restart(void)
{
    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
    immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
							    SCC_GSMRL_ENT);
}
#endif

int mpc82xx_scc_enet_initialize(bd_t *bis)
{
	struct eth_device *dev;

	dev = (struct eth_device *) malloc(sizeof *dev);
	memset(dev, 0, sizeof *dev);

	sprintf(dev->name, "SCC");
	dev->init   = sec_init;
	dev->halt   = sec_halt;
	dev->send   = sec_send;
	dev->recv   = sec_rx;

	eth_register(dev);

	return 1;
}
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* MPC8260 SCC Ethernet
	3	*
	4	* Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
	5	*
	6	* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* (C) Copyright (c) 2001
	10	* Advent Networks, Inc. <http://www.adventnetworks.com>
	11	* Jay Monkman <jtm@smoothsmoothie.com>
	12	*
ba705b5b GJ	13	* Modified so that it plays nicely when more than one ETHERNET interface
	14	* is in use a la ether_fcc.c.
	15	* (C) Copyright 2008
	16	* DENX Software Engineerin GmbH
	17	* Gary Jennejohn <garyj@denx.de>
	18	*
1a459660	19	* SPDX-License-Identifier: GPL-2.0+
fe8c2806 WD	20	*/
	21
	22	#include <common.h>
	23	#include <asm/cpm_8260.h>
	24	#include <mpc8260.h>
ba705b5b	25	#include <malloc.h>
fe8c2806 WD	26	#include <net.h>
	27	#include <command.h>
	28	#include <config.h>
	29
fe8c2806 WD	30	#if (CONFIG_ETHER_INDEX == 1)
	31	# define PROFF_ENET PROFF_SCC1
	32	# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE
	33	# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK
	34	# define CMXSCR_MASK (CMXSCR_SC1 \|\
8bde7f77 WD	35	CMXSCR_RS1CS_MSK \|\
8bde7f77 WD	36	CMXSCR_TS1CS_MSK)
fe8c2806 WD	37
	38	#elif (CONFIG_ETHER_INDEX == 2)
	39	# define PROFF_ENET PROFF_SCC2
	40	# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE
	41	# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK
	42	# define CMXSCR_MASK (CMXSCR_SC2 \|\
8bde7f77 WD	43	CMXSCR_RS2CS_MSK \|\
8bde7f77 WD	44	CMXSCR_TS2CS_MSK)
fe8c2806 WD	45
	46	#elif (CONFIG_ETHER_INDEX == 3)
	47	# define PROFF_ENET PROFF_SCC3
	48	# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE
	49	# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK
	50	# define CMXSCR_MASK (CMXSCR_SC3 \|\
8bde7f77 WD	51	CMXSCR_RS3CS_MSK \|\
8bde7f77 WD	52	CMXSCR_TS3CS_MSK)
fe8c2806 WD	53	#elif (CONFIG_ETHER_INDEX == 4)
	54	# define PROFF_ENET PROFF_SCC4
	55	# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE
	56	# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK
	57	# define CMXSCR_MASK (CMXSCR_SC4 \|\
8bde7f77 WD	58	CMXSCR_RS4CS_MSK \|\
8bde7f77 WD	59	CMXSCR_TS4CS_MSK)
fe8c2806 WD	60
	61	#endif
	62
	63
	64	/* Ethernet Transmit and Receive Buffers */
	65	#define DBUF_LENGTH 1520
	66
	67	#define TX_BUF_CNT 2
	68
6d0f6bcf JCPV	69	#if !defined(CONFIG_SYS_SCC_TOUT_LOOP)
6d0f6bcf JCPV	70	#define CONFIG_SYS_SCC_TOUT_LOOP 1000000
ac9db066	71	#endif
fe8c2806 WD	72
	73	static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];
	74
	75	static uint rxIdx; /* index of the current RX buffer */
	76	static uint txIdx; /* index of the current TX buffer */
	77
	78	/*
	79	* SCC Ethernet Tx and Rx buffer descriptors allocated at the
	80	* immr->udata_bd address on Dual-Port RAM
	81	* Provide for Double Buffering
	82	*/
	83
	84	typedef volatile struct CommonBufferDescriptor {
	85	cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
	86	cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
	87	} RTXBD;
	88
	89	static RTXBD *rtx;
	90
	91
7a10692a	92	static int sec_send(struct eth_device dev, void packet, int length)
fe8c2806 WD	93	{
	94	int i;
	95	int result = 0;
	96
	97	if (length <= 0) {
8bde7f77 WD	98	printf("scc: bad packet size: %d\n", length);
8bde7f77 WD	99	goto out;
fe8c2806 WD	100	}
	101
	102	for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
6d0f6bcf	103	if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
4b9206ed	104	puts ("scc: tx buffer not ready\n");
8bde7f77 WD	105	goto out;
8bde7f77 WD	106	}
fe8c2806 WD	107	}
	108
	109	rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
	110	rtx->txbd[txIdx].cbd_datlen = length;
	111	rtx->txbd[txIdx].cbd_sc \|= (BD_ENET_TX_READY \| BD_ENET_TX_LAST \|
8bde7f77	112	BD_ENET_TX_WRAP);
fe8c2806 WD	113
fe8c2806 WD	114	for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
6d0f6bcf	115	if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
4b9206ed	116	puts ("scc: tx error\n");
8bde7f77 WD	117	goto out;
8bde7f77 WD	118	}
fe8c2806 WD	119	}
	120
	121	/* return only status bits */
	122	result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
	123
	124	out:
	125	return result;
	126	}
	127
	128
ba705b5b	129	static int sec_rx(struct eth_device *dev)
fe8c2806 WD	130	{
	131	int length;
	132
	133	for (;;)
	134	{
8bde7f77 WD	135	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
	136	length = -1;
	137	break; /* nothing received - leave for() loop */
	138	}
	139
	140	length = rtx->rxbd[rxIdx].cbd_datlen;
	141
	142	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
	143	{
	144	printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
	145	}
	146	else
	147	{
	148	/* Pass the packet up to the protocol layers. */
	149	NetReceive(NetRxPackets[rxIdx], length - 4);
	150	}
	151
	152
	153	/* Give the buffer back to the SCC. */
	154	rtx->rxbd[rxIdx].cbd_datlen = 0;
	155
	156	/* wrap around buffer index when necessary */
	157	if ((rxIdx + 1) >= PKTBUFSRX) {
	158	rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP \|
	159	BD_ENET_RX_EMPTY);
	160	rxIdx = 0;
	161	}
	162	else {
	163	rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
	164	rxIdx++;
	165	}
fe8c2806 WD	166	}
	167	return length;
	168	}
	169
	170	/**************************************************************
	171	*
	172	* SCC Ethernet Initialization Routine
	173	*
	174	*************************************************************/
	175
ba705b5b	176	static int sec_init(struct eth_device dev, bd_t bis)
fe8c2806 WD	177	{
fe8c2806 WD	178	int i;
6d0f6bcf	179	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
fe8c2806 WD	180	scc_enet_t *pram_ptr;
fe8c2806 WD	181	uint dpaddr;
6bacfa6a	182	uchar ea[6];
fe8c2806 WD	183
	184	rxIdx = 0;
	185	txIdx = 0;
	186
ba705b5b GJ	187	/*
	188	* Assign static pointer to BD area.
	189	* Avoid exhausting DPRAM, which would cause a panic.
	190	*/
	191	if (rtx == NULL) {
	192	dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
	193	rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
	194	}
fe8c2806 WD	195
	196	/* 24.21 - (1-3): ioports have been set up already */
	197
	198	/* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
	199	immr->im_cpmux.cmx_uar = 0;
	200	immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) \|
6d0f6bcf	201	CONFIG_SYS_CMXSCR_VALUE);
fe8c2806 WD	202
	203
	204	/* 24.21 (6) write RBASE and TBASE to parameter RAM */
	205	pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
	206	pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
	207	pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);
	208
	209	pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */
	210	pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */
	211
	212	pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */
	213
	214	pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
	215	pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
	216
	217
	218	/* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
	219	while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	220	immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
8bde7f77 WD	221	CPM_CR_ENET_SBLOCK,
	222	0x0c,
	223	CPM_CR_INIT_TRX) \| CPM_CR_FLG;
fe8c2806 WD	224
	225	/* 24.21 - (8-18): Set up parameter RAM */
	226	pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
	227	pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */
	228	pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
	229
	230	pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
	231
	232	pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
	233
	234	pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
	235	pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
	236
	237	pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
	238	pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
	239
	240	pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
	241	pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
	242	pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
	243	pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
	244
6bacfa6a	245	eth_getenv_enetaddr("ethaddr", ea);
fe8c2806 WD	246	pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
	247	pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
	248	pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
fe8c2806 WD	249
	250	pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
	251
	252	pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
	253	pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
	254	pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
	255	pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
	256
	257	pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
	258	pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
	259	pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
	260
fe8c2806 WD	261	/* 24.21 - (19): Initialize RxBD */
	262	for (i = 0; i < PKTBUFSRX; i++)
	263	{
8bde7f77 WD	264	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	265	rtx->rxbd[i].cbd_datlen = 0; /* Reset */
	266	rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
fe8c2806 WD	267	}
	268
	269	rtx->rxbd[PKTBUFSRX - 1].cbd_sc \|= BD_ENET_RX_WRAP;
	270
	271	/* 24.21 - (20): Initialize TxBD */
	272	for (i = 0; i < TX_BUF_CNT; i++)
	273	{
8bde7f77 WD	274	rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD \|
	275	BD_ENET_TX_LAST \|
	276	BD_ENET_TX_TC);
	277	rtx->txbd[i].cbd_datlen = 0; /* Reset */
	278	rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
fe8c2806 WD	279	}
	280
	281	rtx->txbd[TX_BUF_CNT - 1].cbd_sc \|= BD_ENET_TX_WRAP;
	282
	283	/* 24.21 - (21): Write 0xffff to SCCE */
	284	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);
	285
	286	/* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
	287	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE \|
8bde7f77 WD	288	SCCE_ENET_RXF \|
8bde7f77 WD	289	SCCE_ENET_TXB);
fe8c2806 WD	290
	291	/* 24.21 - (23): we don't use ethernet interrupts */
	292
	293	/* 24.21 - (24): Clear GSMR_H to enable normal operations */
	294	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;
	295
	296	/* 24.21 - (25): Clear GSMR_L to enable normal operations */
	297	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI \|
8bde7f77 WD	298	SCC_GSMRL_TPL_48 \|
	299	SCC_GSMRL_TPP_10 \|
	300	SCC_GSMRL_MODE_ENET);
fe8c2806 WD	301
	302	/* 24.21 - (26): Initialize DSR */
	303	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
	304
	305	/* 24.21 - (27): Initialize PSMR2
	306	*
	307	* Settings:
	308	* CRC = 32-Bit CCITT
	309	* NIB = Begin searching for SFD 22 bits after RENA
	310	* FDE = Full Duplex Enable
	311	* BRO = Reject broadcast packets
	312	* PROMISCOUS = Catch all packets regardless of dest. MAC adress
	313	*/
	314	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC \|
	315	SCC_PSMR_NIB22 \|
	316	#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
	317	SCC_PSMR_FDE \|
	318	#endif
	319	#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
	320	SCC_PSMR_BRO \|
	321	#endif
	322	#if defined(CONFIG_SCC_ENET_PROMISCOUS)
	323	SCC_PSMR_PRO \|
	324	#endif
	325	0;
	326
	327	/* 24.21 - (28): Write to GSMR_L to enable SCC */
	328	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl \|= (SCC_GSMRL_ENR \|
8bde7f77	329	SCC_GSMRL_ENT);
fe8c2806	330
48b42616	331	return 0;
fe8c2806 WD	332	}
	333
	334
ba705b5b	335	static void sec_halt(struct eth_device *dev)
fe8c2806	336	{
6d0f6bcf	337	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
fe8c2806	338	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR \|
8bde7f77	339	SCC_GSMRL_ENT);
fe8c2806 WD	340	}
	341
	342	#if 0
ba705b5b	343	static void sec_restart(void)
fe8c2806	344	{
6d0f6bcf	345	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
fe8c2806	346	immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl \|= (SCC_GSMRL_ENR \|
8bde7f77	347	SCC_GSMRL_ENT);
fe8c2806 WD	348	}
	349	#endif
	350
ba705b5b GJ	351	int mpc82xx_scc_enet_initialize(bd_t *bis)
	352	{
	353	struct eth_device *dev;
	354
	355	dev = (struct eth_device ) malloc(sizeof dev);
	356	memset(dev, 0, sizeof *dev);
	357
48690d80	358	sprintf(dev->name, "SCC");
ba705b5b GJ	359	dev->init = sec_init;
	360	dev->halt = sec_halt;
	361	dev->send = sec_send;
	362	dev->recv = sec_rx;
	363
	364	eth_register(dev);
	365
	366	return 1;
	367	}