[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / serial_scc.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
 */

/*
 * Minimal serial functions needed to use one of the SCC ports
 * as serial console interface.
 */

#include <common.h>
#include <mpc8260.h>
#include <asm/cpm_8260.h>
#include <serial.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_CONS_ON_SCC)

#if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */

#define SCC_INDEX		0
#define PROFF_SCC		PROFF_SCC1
#define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
#define CMXSCR_VALUE		(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
#define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK

#elif CONFIG_CONS_INDEX == 2	/* Console on SCC2 */

#define SCC_INDEX		1
#define PROFF_SCC		PROFF_SCC2
#define CMXSCR_MASK		(CMXSCR_GR2|CMXSCR_SC2|\
					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
#define CMXSCR_VALUE		(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
#define CPM_CR_SCC_PAGE		CPM_CR_SCC2_PAGE
#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK

#elif CONFIG_CONS_INDEX == 3	/* Console on SCC3 */

#define SCC_INDEX		2
#define PROFF_SCC		PROFF_SCC3
#define CMXSCR_MASK		(CMXSCR_GR3|CMXSCR_SC3|\
					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
#define CMXSCR_VALUE		(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
#define CPM_CR_SCC_PAGE		CPM_CR_SCC3_PAGE
#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK

#elif CONFIG_CONS_INDEX == 4	/* Console on SCC4 */

#define SCC_INDEX		3
#define PROFF_SCC		PROFF_SCC4
#define CMXSCR_MASK		(CMXSCR_GR4|CMXSCR_SC4|\
					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
#define CMXSCR_VALUE		(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
#define CPM_CR_SCC_PAGE		CPM_CR_SCC4_PAGE
#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK

#else

#error "console not correctly defined"

#endif

static int mpc8260_scc_serial_init(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	volatile scc_t *sp;
	volatile scc_uart_t *up;
	volatile cbd_t *tbdf, *rbdf;
	volatile cpm8260_t *cp = &(im->im_cpm);
	uint	dpaddr;

	/* initialize pointers to SCC */

	sp = (scc_t *) &(im->im_scc[SCC_INDEX]);
	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];

	/* Disable transmitter/receiver.
	*/
	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	/* put the SCC channel into NMSI (non multiplexd serial interface)
	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
	 */
	im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE;

	/* Set up the baud rate generator.
	*/
	serial_setbrg ();

	/* Allocate space for two buffer descriptors in the DP ram.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
	rbdf->cbd_bufaddr = (uint) (rbdf+2);
	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
	tbdf = rbdf + 1;
	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
	tbdf->cbd_sc = BD_SC_WRAP;

	/* Set up the uart parameters in the parameter ram.
	*/
	up->scc_genscc.scc_rbase = dpaddr;
	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
	up->scc_genscc.scc_rfcr = CPMFCR_EB;
	up->scc_genscc.scc_tfcr = CPMFCR_EB;
	up->scc_genscc.scc_mrblr = 1;
	up->scc_maxidl = 0;
	up->scc_brkcr = 1;
	up->scc_parec = 0;
	up->scc_frmec = 0;
	up->scc_nosec = 0;
	up->scc_brkec = 0;
	up->scc_uaddr1 = 0;
	up->scc_uaddr2 = 0;
	up->scc_toseq = 0;
	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
	up->scc_rccm = 0xc0ff;

	/* Mask all interrupts and remove anything pending.
	*/
	sp->scc_sccm = 0;
	sp->scc_scce = 0xffff;

	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
	*/
	sp->scc_gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
	sp->scc_gsmrl = \
		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;

	/* Set CTS flow control, 1 stop bit, 8 bit character length,
	 * normal async UART mode, no parity
	 */
	sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;

	/* execute the "Init Rx and Tx params" CP command.
	*/

	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
	  ;

	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;

	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
	  ;

	/* Enable transmitter/receiver.
	*/
	sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;

	return (0);
}

static void mpc8260_scc_serial_setbrg(void)
{
#if defined(CONFIG_CONS_USE_EXTC)
	m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
#else
	m8260_cpm_setbrg(SCC_INDEX, gd->baudrate);
#endif
}

static void mpc8260_scc_serial_putc(const char c)
{
	volatile scc_uart_t	*up;
	volatile cbd_t		*tbdf;
	volatile immap_t	*im;

	if (c == '\n')
		serial_putc ('\r');

	im = (immap_t *)CONFIG_SYS_IMMR;
	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];

	/* Wait for last character to go.
	 */
	while (tbdf->cbd_sc & BD_SC_READY)
		;

	/* Load the character into the transmit buffer.
	 */
	*(volatile char *)tbdf->cbd_bufaddr = c;
	tbdf->cbd_datlen = 1;
	tbdf->cbd_sc |= BD_SC_READY;
}

static int mpc8260_scc_serial_getc(void)
{
	volatile cbd_t		*rbdf;
	volatile scc_uart_t	*up;
	volatile immap_t	*im;
	unsigned char		c;

	im = (immap_t *)CONFIG_SYS_IMMR;
	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];

	/* Wait for character to show up.
	 */
	while (rbdf->cbd_sc & BD_SC_EMPTY)
		;

	/* Grab the char and clear the buffer again.
	 */
	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
	rbdf->cbd_sc |= BD_SC_EMPTY;

	return (c);
}

static int mpc8260_scc_serial_tstc(void)
{
	volatile cbd_t		*rbdf;
	volatile scc_uart_t	*up;
	volatile immap_t	*im;

	im = (immap_t *)CONFIG_SYS_IMMR;
	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];

	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}

static struct serial_device mpc8260_scc_serial_drv = {
	.name	= "mpc8260_scc_uart",
	.start	= mpc8260_scc_serial_init,
	.stop	= NULL,
	.setbrg	= mpc8260_scc_serial_setbrg,
	.putc	= mpc8260_scc_serial_putc,
	.puts	= default_serial_puts,
	.getc	= mpc8260_scc_serial_getc,
	.tstc	= mpc8260_scc_serial_tstc,
};

void mpc8260_scc_serial_initialize(void)
{
	serial_register(&mpc8260_scc_serial_drv);
}

__weak struct serial_device *default_serial_console(void)
{
	return &mpc8260_scc_serial_drv;
}
#endif	/* CONFIG_CONS_ON_SCC */

#if defined(CONFIG_KGDB_ON_SCC)

#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
#error Whoops! serial console and kgdb are on the same scc serial port
#endif

#if CONFIG_KGDB_INDEX == 1	/* KGDB Port on SCC1 */

#define KGDB_SCC_INDEX		0
#define KGDB_PROFF_SCC		PROFF_SCC1
#define KGDB_CMXSCR_MASK	(CMXSCR_GR1|CMXSCR_SC1|\
					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
#define KGDB_CMXSCR_VALUE	(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC1_PAGE
#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK

#elif CONFIG_KGDB_INDEX == 2	/* KGDB Port on SCC2 */

#define KGDB_SCC_INDEX		1
#define KGDB_PROFF_SCC		PROFF_SCC2
#define KGDB_CMXSCR_MASK	(CMXSCR_GR2|CMXSCR_SC2|\
					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
#define KGDB_CMXSCR_VALUE	(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC2_PAGE
#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK

#elif CONFIG_KGDB_INDEX == 3	/* KGDB Port on SCC3 */

#define KGDB_SCC_INDEX		2
#define KGDB_PROFF_SCC		PROFF_SCC3
#define KGDB_CMXSCR_MASK	(CMXSCR_GR3|CMXSCR_SC3|\
					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
#define KGDB_CMXSCR_VALUE	(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC3_PAGE
#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK

#elif CONFIG_KGDB_INDEX == 4	/* KGDB Port on SCC4 */

#define KGDB_SCC_INDEX		3
#define KGDB_PROFF_SCC		PROFF_SCC4
#define KGDB_CMXSCR_MASK	(CMXSCR_GR4|CMXSCR_SC4|\
					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
#define KGDB_CMXSCR_VALUE	(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC4_PAGE
#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK

#else

#error "kgdb serial port not correctly defined"

#endif

void
kgdb_serial_init (void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	volatile scc_t *sp;
	volatile scc_uart_t *up;
	volatile cbd_t *tbdf, *rbdf;
	volatile cpm8260_t *cp = &(im->im_cpm);
	uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
	char *s, *e;

	if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
		ulong rate = simple_strtoul(s, &e, 10);
		if (e > s && *e == '\0')
			speed = rate;
	}

	/* initialize pointers to SCC */

	sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]);
	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];

	/* Disable transmitter/receiver.
	*/
	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	/* put the SCC channel into NMSI (non multiplexd serial interface)
	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
	 */
	im->im_cpmux.cmx_scr = \
		(im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE;

	/* Set up the baud rate generator.
	*/
#if defined(CONFIG_KGDB_USE_EXTC)
	m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed,
		CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
#else
	m8260_cpm_setbrg(KGDB_SCC_INDEX, speed);
#endif

	/* Allocate space for two buffer descriptors in the DP ram.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
	rbdf->cbd_bufaddr = (uint) (rbdf+2);
	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
	tbdf = rbdf + 1;
	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
	tbdf->cbd_sc = BD_SC_WRAP;

	/* Set up the uart parameters in the parameter ram.
	*/
	up->scc_genscc.scc_rbase = dpaddr;
	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
	up->scc_genscc.scc_rfcr = CPMFCR_EB;
	up->scc_genscc.scc_tfcr = CPMFCR_EB;
	up->scc_genscc.scc_mrblr = 1;
	up->scc_maxidl = 0;
	up->scc_brkcr = 1;
	up->scc_parec = 0;
	up->scc_frmec = 0;
	up->scc_nosec = 0;
	up->scc_brkec = 0;
	up->scc_uaddr1 = 0;
	up->scc_uaddr2 = 0;
	up->scc_toseq = 0;
	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
	up->scc_rccm = 0xc0ff;

	/* Mask all interrupts and remove anything pending.
	*/
	sp->scc_sccm = 0;
	sp->scc_scce = 0xffff;

	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
	*/
	sp->scc_gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
	sp->scc_gsmrl = \
		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;

	/* Set CTS flow control, 1 stop bit, 8 bit character length,
	 * normal async UART mode, no parity
	 */
	sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;

	/* execute the "Init Rx and Tx params" CP command.
	*/

	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
	  ;

	cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK,
					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;

	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
	  ;

	/* Enable transmitter/receiver.
	*/
	sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;

	printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
}

void
putDebugChar(const char c)
{
	volatile scc_uart_t	*up;
	volatile cbd_t		*tbdf;
	volatile immap_t	*im;

	if (c == '\n')
		putDebugChar ('\r');

	im = (immap_t *)CONFIG_SYS_IMMR;
	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];

	/* Wait for last character to go.
	 */
	while (tbdf->cbd_sc & BD_SC_READY)
		;

	/* Load the character into the transmit buffer.
	 */
	*(volatile char *)tbdf->cbd_bufaddr = c;
	tbdf->cbd_datlen = 1;
	tbdf->cbd_sc |= BD_SC_READY;
}

void
putDebugStr (const char *s)
{
	while (*s) {
		putDebugChar (*s++);
	}
}

int
getDebugChar(void)
{
	volatile cbd_t		*rbdf;
	volatile scc_uart_t	*up;
	volatile immap_t	*im;
	unsigned char		c;

	im = (immap_t *)CONFIG_SYS_IMMR;
	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];

	/* Wait for character to show up.
	 */
	while (rbdf->cbd_sc & BD_SC_EMPTY)
		;

	/* Grab the char and clear the buffer again.
	 */
	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
	rbdf->cbd_sc |= BD_SC_EMPTY;

	return (c);
}

void
kgdb_interruptible(int yes)
{
	return;
}

#endif	/* CONFIG_KGDB_ON_SCC */
Commit	Line	Data
4a9cbbe8 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
	24	*/
	25
	26	/*
	27	* Minimal serial functions needed to use one of the SCC ports
	28	* as serial console interface.
	29	*/
	30
	31	#include <common.h>
	32	#include <mpc8260.h>
	33	#include <asm/cpm_8260.h>
d68f4da2 MV	34	#include <serial.h>
d68f4da2 MV	35	#include <linux/compiler.h>
4a9cbbe8	36
d87080b7 WD	37	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	38
4a9cbbe8 WD	39	#if defined(CONFIG_CONS_ON_SCC)
	40
	41	#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
	42
	43	#define SCC_INDEX 0
	44	#define PROFF_SCC PROFF_SCC1
	45	#define CMXSCR_MASK (CMXSCR_GR1\|CMXSCR_SC1\|\
	46	CMXSCR_RS1CS_MSK\|CMXSCR_TS1CS_MSK)
	47	#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1\|CMXSCR_TS1CS_BRG1)
	48	#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
	49	#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
	50
	51	#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
	52
	53	#define SCC_INDEX 1
	54	#define PROFF_SCC PROFF_SCC2
	55	#define CMXSCR_MASK (CMXSCR_GR2\|CMXSCR_SC2\|\
	56	CMXSCR_RS2CS_MSK\|CMXSCR_TS2CS_MSK)
	57	#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2\|CMXSCR_TS2CS_BRG2)
	58	#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
	59	#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
	60
	61	#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
	62
	63	#define SCC_INDEX 2
	64	#define PROFF_SCC PROFF_SCC3
	65	#define CMXSCR_MASK (CMXSCR_GR3\|CMXSCR_SC3\|\
	66	CMXSCR_RS3CS_MSK\|CMXSCR_TS3CS_MSK)
	67	#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3\|CMXSCR_TS3CS_BRG3)
	68	#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
	69	#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
	70
	71	#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
	72
	73	#define SCC_INDEX 3
	74	#define PROFF_SCC PROFF_SCC4
	75	#define CMXSCR_MASK (CMXSCR_GR4\|CMXSCR_SC4\|\
	76	CMXSCR_RS4CS_MSK\|CMXSCR_TS4CS_MSK)
	77	#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4\|CMXSCR_TS4CS_BRG4)
	78	#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
	79	#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
	80
	81	#else
	82
	83	#error "console not correctly defined"
	84
	85	#endif
	86
d68f4da2	87	static int mpc8260_scc_serial_init(void)
4a9cbbe8	88	{
6d0f6bcf	89	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8 WD	90	volatile scc_t *sp;
	91	volatile scc_uart_t *up;
	92	volatile cbd_t tbdf, rbdf;
	93	volatile cpm8260_t *cp = &(im->im_cpm);
	94	uint dpaddr;
	95
	96	/* initialize pointers to SCC */
	97
	98	sp = (scc_t *) &(im->im_scc[SCC_INDEX]);
	99	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
	100
	101	/* Disable transmitter/receiver.
	102	*/
	103	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	104
	105	/* put the SCC channel into NMSI (non multiplexd serial interface)
	106	* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
	107	*/
	108	im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)\|CMXSCR_VALUE;
	109
	110	/* Set up the baud rate generator.
	111	*/
	112	serial_setbrg ();
	113
	114	/* Allocate space for two buffer descriptors in the DP ram.
	115	* damm: allocating space after the two buffers for rx/tx data
	116	*/
	117
	118	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
	119
	120	/* Set the physical address of the host memory buffers in
	121	* the buffer descriptors.
	122	*/
	123	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
	124	rbdf->cbd_bufaddr = (uint) (rbdf+2);
	125	rbdf->cbd_sc = BD_SC_EMPTY \| BD_SC_WRAP;
	126	tbdf = rbdf + 1;
	127	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
	128	tbdf->cbd_sc = BD_SC_WRAP;
	129
	130	/* Set up the uart parameters in the parameter ram.
	131	*/
	132	up->scc_genscc.scc_rbase = dpaddr;
	133	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
	134	up->scc_genscc.scc_rfcr = CPMFCR_EB;
	135	up->scc_genscc.scc_tfcr = CPMFCR_EB;
	136	up->scc_genscc.scc_mrblr = 1;
	137	up->scc_maxidl = 0;
	138	up->scc_brkcr = 1;
	139	up->scc_parec = 0;
	140	up->scc_frmec = 0;
	141	up->scc_nosec = 0;
	142	up->scc_brkec = 0;
	143	up->scc_uaddr1 = 0;
	144	up->scc_uaddr2 = 0;
	145	up->scc_toseq = 0;
	146	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
	147	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
	148	up->scc_rccm = 0xc0ff;
	149
	150	/* Mask all interrupts and remove anything pending.
	151	*/
	152	sp->scc_sccm = 0;
	153	sp->scc_scce = 0xffff;
154
155	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
156	*/
157	sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
158	sp->scc_gsmrl = \
159	SCC_GSMRL_TDCR_16 \| SCC_GSMRL_RDCR_16 \| SCC_GSMRL_MODE_UART;
160
161	/* Set CTS flow control, 1 stop bit, 8 bit character length,
162	* normal async UART mode, no parity
163	*/
164	sp->scc_psmr = SCU_PSMR_FLC \| SCU_PSMR_CL;
165
166	/* execute the "Init Rx and Tx params" CP command.
167	*/
168
169	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
170	;
171
172	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
173	0, CPM_CR_INIT_TRX) \| CPM_CR_FLG;
174
175	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
176	;
177
178	/* Enable transmitter/receiver.
179	*/
180	sp->scc_gsmrl \|= SCC_GSMRL_ENR \| SCC_GSMRL_ENT;
181
182	return (0);
183	}
184
d68f4da2	185	static void mpc8260_scc_serial_setbrg(void)
4a9cbbe8	186	{
4a9cbbe8 WD	187	#if defined(CONFIG_CONS_USE_EXTC)
	188	m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
	189	CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
	190	#else
	191	m8260_cpm_setbrg(SCC_INDEX, gd->baudrate);
	192	#endif
	193	}
	194
d68f4da2	195	static void mpc8260_scc_serial_putc(const char c)
4a9cbbe8 WD	196	{
	197	volatile scc_uart_t *up;
	198	volatile cbd_t *tbdf;
8bde7f77	199	volatile immap_t *im;
4a9cbbe8 WD	200
	201	if (c == '\n')
	202	serial_putc ('\r');
	203
6d0f6bcf	204	im = (immap_t *)CONFIG_SYS_IMMR;
4a9cbbe8 WD	205	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
	206	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
	207
	208	/* Wait for last character to go.
	209	*/
	210	while (tbdf->cbd_sc & BD_SC_READY)
	211	;
	212
	213	/* Load the character into the transmit buffer.
	214	*/
	215	(volatile char )tbdf->cbd_bufaddr = c;
	216	tbdf->cbd_datlen = 1;
	217	tbdf->cbd_sc \|= BD_SC_READY;
	218	}
	219
d68f4da2	220	static int mpc8260_scc_serial_getc(void)
4a9cbbe8 WD	221	{
	222	volatile cbd_t *rbdf;
	223	volatile scc_uart_t *up;
8bde7f77	224	volatile immap_t *im;
4a9cbbe8 WD	225	unsigned char c;
4a9cbbe8 WD	226
6d0f6bcf	227	im = (immap_t *)CONFIG_SYS_IMMR;
4a9cbbe8 WD	228	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
	229	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
	230
	231	/* Wait for character to show up.
	232	*/
	233	while (rbdf->cbd_sc & BD_SC_EMPTY)
	234	;
	235
	236	/* Grab the char and clear the buffer again.
	237	*/
	238	c = (volatile unsigned char )rbdf->cbd_bufaddr;
	239	rbdf->cbd_sc \|= BD_SC_EMPTY;
	240
	241	return (c);
	242	}
	243
d68f4da2	244	static int mpc8260_scc_serial_tstc(void)
4a9cbbe8 WD	245	{
	246	volatile cbd_t *rbdf;
	247	volatile scc_uart_t *up;
8bde7f77	248	volatile immap_t *im;
4a9cbbe8	249
6d0f6bcf	250	im = (immap_t *)CONFIG_SYS_IMMR;
4a9cbbe8 WD	251	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
	252	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
	253
	254	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
	255	}
	256
d68f4da2 MV	257	static struct serial_device mpc8260_scc_serial_drv = {
	258	.name = "mpc8260_scc_uart",
	259	.start = mpc8260_scc_serial_init,
	260	.stop = NULL,
	261	.setbrg = mpc8260_scc_serial_setbrg,
	262	.putc = mpc8260_scc_serial_putc,
ec3fd689	263	.puts = default_serial_puts,
d68f4da2 MV	264	.getc = mpc8260_scc_serial_getc,
	265	.tstc = mpc8260_scc_serial_tstc,
	266	};
	267
	268	void mpc8260_scc_serial_initialize(void)
	269	{
	270	serial_register(&mpc8260_scc_serial_drv);
	271	}
	272
	273	__weak struct serial_device *default_serial_console(void)
	274	{
	275	return &mpc8260_scc_serial_drv;
	276	}
4a9cbbe8 WD	277	#endif /* CONFIG_CONS_ON_SCC */
	278
	279	#if defined(CONFIG_KGDB_ON_SCC)
	280
	281	#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
	282	#error Whoops! serial console and kgdb are on the same scc serial port
	283	#endif
	284
	285	#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SCC1 */
	286
	287	#define KGDB_SCC_INDEX 0
	288	#define KGDB_PROFF_SCC PROFF_SCC1
	289	#define KGDB_CMXSCR_MASK (CMXSCR_GR1\|CMXSCR_SC1\|\
	290	CMXSCR_RS1CS_MSK\|CMXSCR_TS1CS_MSK)
	291	#define KGDB_CMXSCR_VALUE (CMXSCR_RS1CS_BRG1\|CMXSCR_TS1CS_BRG1)
	292	#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
	293	#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
	294
	295	#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SCC2 */
	296
	297	#define KGDB_SCC_INDEX 1
	298	#define KGDB_PROFF_SCC PROFF_SCC2
	299	#define KGDB_CMXSCR_MASK (CMXSCR_GR2\|CMXSCR_SC2\|\
	300	CMXSCR_RS2CS_MSK\|CMXSCR_TS2CS_MSK)
	301	#define KGDB_CMXSCR_VALUE (CMXSCR_RS2CS_BRG2\|CMXSCR_TS2CS_BRG2)
	302	#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
	303	#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
	304
	305	#elif CONFIG_KGDB_INDEX == 3 /* KGDB Port on SCC3 */
	306
	307	#define KGDB_SCC_INDEX 2
	308	#define KGDB_PROFF_SCC PROFF_SCC3
	309	#define KGDB_CMXSCR_MASK (CMXSCR_GR3\|CMXSCR_SC3\|\
	310	CMXSCR_RS3CS_MSK\|CMXSCR_TS3CS_MSK)
	311	#define KGDB_CMXSCR_VALUE (CMXSCR_RS3CS_BRG3\|CMXSCR_TS3CS_BRG3)
	312	#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
	313	#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
	314
	315	#elif CONFIG_KGDB_INDEX == 4 /* KGDB Port on SCC4 */
	316
	317	#define KGDB_SCC_INDEX 3
	318	#define KGDB_PROFF_SCC PROFF_SCC4
	319	#define KGDB_CMXSCR_MASK (CMXSCR_GR4\|CMXSCR_SC4\|\
	320	CMXSCR_RS4CS_MSK\|CMXSCR_TS4CS_MSK)
	321	#define KGDB_CMXSCR_VALUE (CMXSCR_RS4CS_BRG4\|CMXSCR_TS4CS_BRG4)
	322	#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
	323	#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
	324
	325	#else
	326
	327	#error "kgdb serial port not correctly defined"
	328
	329	#endif
	330
	331	void
	332	kgdb_serial_init (void)
	333	{
6d0f6bcf	334	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8 WD	335	volatile scc_t *sp;
	336	volatile scc_uart_t *up;
	337	volatile cbd_t tbdf, rbdf;
	338	volatile cpm8260_t *cp = &(im->im_cpm);
	339	uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
	340	char s, e;
	341
	342	if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
	343	ulong rate = simple_strtoul(s, &e, 10);
	344	if (e > s && *e == '\0')
	345	speed = rate;
	346	}
	347
	348	/* initialize pointers to SCC */
	349
	350	sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]);
	351	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
	352
	353	/* Disable transmitter/receiver.
	354	*/
	355	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	356
	357	/* put the SCC channel into NMSI (non multiplexd serial interface)
	358	* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
	359	*/
	360	im->im_cpmux.cmx_scr = \
	361	(im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) \| KGDB_CMXSCR_VALUE;
	362
	363	/* Set up the baud rate generator.
	364	*/
	365	#if defined(CONFIG_KGDB_USE_EXTC)
	366	m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed,
	367	CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
	368	#else
	369	m8260_cpm_setbrg(KGDB_SCC_INDEX, speed);
	370	#endif
	371
	372	/* Allocate space for two buffer descriptors in the DP ram.
	373	* damm: allocating space after the two buffers for rx/tx data
	374	*/
	375
	376	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
	377
	378	/* Set the physical address of the host memory buffers in
	379	* the buffer descriptors.
	380	*/
	381	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
	382	rbdf->cbd_bufaddr = (uint) (rbdf+2);
	383	rbdf->cbd_sc = BD_SC_EMPTY \| BD_SC_WRAP;
	384	tbdf = rbdf + 1;
	385	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
	386	tbdf->cbd_sc = BD_SC_WRAP;
	387
	388	/* Set up the uart parameters in the parameter ram.
	389	*/
	390	up->scc_genscc.scc_rbase = dpaddr;
	391	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
	392	up->scc_genscc.scc_rfcr = CPMFCR_EB;
	393	up->scc_genscc.scc_tfcr = CPMFCR_EB;
	394	up->scc_genscc.scc_mrblr = 1;
	395	up->scc_maxidl = 0;
	396	up->scc_brkcr = 1;
	397	up->scc_parec = 0;
	398	up->scc_frmec = 0;
399	up->scc_nosec = 0;
400	up->scc_brkec = 0;
401	up->scc_uaddr1 = 0;
402	up->scc_uaddr2 = 0;
403	up->scc_toseq = 0;
404	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
405	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
406	up->scc_rccm = 0xc0ff;
407
408	/* Mask all interrupts and remove anything pending.
409	*/
410	sp->scc_sccm = 0;
411	sp->scc_scce = 0xffff;
412
413	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
414	*/
415	sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
416	sp->scc_gsmrl = \
417	SCC_GSMRL_TDCR_16 \| SCC_GSMRL_RDCR_16 \| SCC_GSMRL_MODE_UART;
418
419	/* Set CTS flow control, 1 stop bit, 8 bit character length,
420	* normal async UART mode, no parity
421	*/
422	sp->scc_psmr = SCU_PSMR_FLC \| SCU_PSMR_CL;
423
424	/* execute the "Init Rx and Tx params" CP command.
425	*/
426
427	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
428	;
429
430	cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK,
431	0, CPM_CR_INIT_TRX) \| CPM_CR_FLG;
432
433	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
434	;
435
436	/* Enable transmitter/receiver.
437	*/
438	sp->scc_gsmrl \|= SCC_GSMRL_ENR \| SCC_GSMRL_ENT;
439
440	printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
441	}
442
443	void
444	putDebugChar(const char c)
445	{
446	volatile scc_uart_t *up;
447	volatile cbd_t *tbdf;
8bde7f77	448	volatile immap_t *im;
4a9cbbe8 WD	449
	450	if (c == '\n')
	451	putDebugChar ('\r');
	452
6d0f6bcf	453	im = (immap_t *)CONFIG_SYS_IMMR;
4a9cbbe8 WD	454	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
	455	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
	456
	457	/* Wait for last character to go.
	458	*/
	459	while (tbdf->cbd_sc & BD_SC_READY)
	460	;
	461
	462	/* Load the character into the transmit buffer.
	463	*/
	464	(volatile char )tbdf->cbd_bufaddr = c;
	465	tbdf->cbd_datlen = 1;
	466	tbdf->cbd_sc \|= BD_SC_READY;
	467	}
	468
	469	void
	470	putDebugStr (const char *s)
	471	{
	472	while (*s) {
	473	putDebugChar (*s++);
	474	}
	475	}
	476
	477	int
	478	getDebugChar(void)
	479	{
	480	volatile cbd_t *rbdf;
	481	volatile scc_uart_t *up;
8bde7f77	482	volatile immap_t *im;
4a9cbbe8 WD	483	unsigned char c;
4a9cbbe8 WD	484
6d0f6bcf	485	im = (immap_t *)CONFIG_SYS_IMMR;
4a9cbbe8 WD	486	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
	487	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
	488
	489	/* Wait for character to show up.
	490	*/
	491	while (rbdf->cbd_sc & BD_SC_EMPTY)
	492	;
	493
	494	/* Grab the char and clear the buffer again.
	495	*/
	496	c = (volatile unsigned char )rbdf->cbd_bufaddr;
	497	rbdf->cbd_sc \|= BD_SC_EMPTY;
	498
	499	return (c);
	500	}
	501
	502	void
	503	kgdb_interruptible(int yes)
	504	{
	505	return;
	506	}
	507
	508	#endif /* CONFIG_KGDB_ON_SCC */