[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / speed.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc8260.h>
#include <asm/processor.h>

#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
extern unsigned long board_get_cpu_clk_f (void);
#endif

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */

/* Bus-to-Core Multiplier */
#define _1x	2
#define _1_5x	3
#define _2x	4
#define _2_5x	5
#define _3x	6
#define _3_5x	7
#define _4x	8
#define _4_5x	9
#define _5x	10
#define _5_5x	11
#define _6x	12
#define _6_5x	13
#define _7x	14
#define _7_5x	15
#define _8x	16
#define _byp	-1
#define _off	-2
#define _unk	-3

typedef struct {
	int b2c_mult;
	int vco_div;
	char *freq_60x;
	char *freq_core;
} corecnf_t;

/*
 * this table based on "Errata to MPC8260 PowerQUICC II User's Manual",
 * Rev. 1, 8/2000, page 10.
 */
corecnf_t corecnf_tab[] = {
	{ _1_5x,  4, " 33-100", " 33-100" },	/* 0x00 */
	{   _1x,  4, " 50-150", " 50-150" },	/* 0x01 */
	{   _1x,  8, " 25-75 ", " 25-75 " },	/* 0x02 */
	{  _byp, -1, "  ?-?  ", "  ?-?  " },	/* 0x03 */
	{   _2x,  2, " 50-150", "100-300" },	/* 0x04 */
	{   _2x,  4, " 25-75 ", " 50-150" },	/* 0x05 */
	{ _2_5x,  2, " 40-120", "100-240" },	/* 0x06 */
	{ _4_5x,  2, " 22-65 ", "100-300" },	/* 0x07 */
	{   _3x,  2, " 33-100", "100-300" },	/* 0x08 */
	{ _5_5x,  2, " 18-55 ", "100-300" },	/* 0x09 */
	{   _4x,  2, " 25-75 ", "100-300" },	/* 0x0A */
	{   _5x,  2, " 20-60 ", "100-300" },	/* 0x0B */
	{ _1_5x,  8, " 16-50 ", " 16-50 " },	/* 0x0C */
	{   _6x,  2, " 16-50 ", "100-300" },	/* 0x0D */
	{ _3_5x,  2, " 30-85 ", "100-300" },	/* 0x0E */
	{  _off, -1, "  ?-?  ", "  ?-?  " },	/* 0x0F */
	{   _3x,  4, " 16-50 ", " 50-150" },	/* 0x10 */
	{ _2_5x,  4, " 20-60 ", " 50-120" },	/* 0x11 */
	{ _6_5x,  2, " 15-46 ", "100-300" },	/* 0x12 */
	{  _byp, -1, "  ?-?  ", "  ?-?  " },	/* 0x13 */
	{   _7x,  2, " 14-43 ", "100-300" },	/* 0x14 */
	{   _2x,  4, " 25-75 ", " 50-150" },	/* 0x15 */
	{ _7_5x,  2, " 13-40 ", "100-300" },	/* 0x16 */
	{ _4_5x,  2, " 22-65 ", "100-300" },	/* 0x17 */
	{  _unk, -1, "  ?-?  ", "  ?-?  " },	/* 0x18 */
	{ _5_5x,  2, " 18-55 ", "100-300" },	/* 0x19 */
	{   _4x,  2, " 25-75 ", "100-300" },	/* 0x1A */
	{   _5x,  2, " 20-60 ", "100-300" },	/* 0x1B */
	{   _8x,  2, " 12-38 ", "100-300" },	/* 0x1C */
	{   _6x,  2, " 16-50 ", "100-300" },	/* 0x1D */
	{ _3_5x,  2, " 30-85 ", "100-300" },	/* 0x1E */
	{  _off, -1, "  ?-?  ", "  ?-?  " },	/* 0x1F */
};

/* ------------------------------------------------------------------------- */

/*
 *
 */

int get_clocks (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	ulong clkin;
	ulong sccr, dfbrg;
	ulong scmr, corecnf, plldf, pllmf;
	corecnf_t *cp;

#if !defined(CONFIG_8260_CLKIN)
#error clock measuring not implemented yet - define CONFIG_8260_CLKIN
#else
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
	clkin = board_get_cpu_clk_f ();
#else
	clkin = CONFIG_8260_CLKIN;
#endif
#endif

	sccr = immap->im_clkrst.car_sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;

	scmr = immap->im_clkrst.car_scmr;
	corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
	cp = &corecnf_tab[corecnf];

	/* HiP7, HiP7 Rev01, HiP7 RevA */
	if ((get_pvr () == PVR_8260_HIP7) ||
	    (get_pvr () == PVR_8260_HIP7R1) ||
	    (get_pvr () == PVR_8260_HIP7RA)) {
		pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
		gd->arch.vco_out = clkin * (pllmf + 1);
	} else {                        /* HiP3, HiP4 */
		pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
		plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
		gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
	}

	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	gd->bus_clk = clkin;
	gd->arch.scc_clk = gd->arch.vco_out / 4;
	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));

	if (cp->b2c_mult > 0) {
		gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
	} else {
		gd->cpu_clk = clkin;
	}

#ifdef CONFIG_PCI
	gd->pci_clk = clkin;

	if (sccr & SCCR_PCI_MODE) {
		uint pci_div;
		uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;

		if (sccr & SCCR_PCI_MODCK) {
			pci_div = 2;
			if (pcidf == 9) {
				pci_div *= 5;
			} else if (pcidf == 0xB) {
				pci_div *= 6;
			} else {
				pci_div *= (pcidf + 1);
			}
		} else {
			pci_div = pcidf + 1;
		}

		gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div;
	}
#endif

	return (0);
}

int prt_8260_clks (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	ulong sccr, dfbrg;
	ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
	corecnf_t *cp;

	sccr = immap->im_clkrst.car_sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;

	scmr = immap->im_clkrst.car_scmr;
	corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
	busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
	cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
	plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
	pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
	pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;

	cp = &corecnf_tab[corecnf];

	puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");

	switch (cp->b2c_mult) {
	case _byp:
		puts ("BYPASS");
		break;

	case _off:
		puts ("OFF");
		break;

	case _unk:
		puts ("UNKNOWN");
		break;

	default:
		printf ("%d%sx",
			cp->b2c_mult / 2,
			(cp->b2c_mult % 2) ? ".5" : "");
		break;
	}

	printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
			cp->vco_div, cp->freq_60x, cp->freq_core);

	printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
		"plldf %ld, pllmf %ld, pcidf %ld\n",
			dfbrg, corecnf, busdf, cpmdf,
			plldf, pllmf, pcidf);

	printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
			gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk);

	printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
			gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk);
#ifdef CONFIG_PCI
	printf (" - pci_clk %10ld\n", gd->pci_clk);
#endif
	putc ('\n');

	return (0);
}
Commit	Line	Data
4a9cbbe8 WD	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
4a9cbbe8 WD	6	*/
	7
	8	#include <common.h>
	9	#include <mpc8260.h>
	10	#include <asm/processor.h>
	11
fa230445 HS	12	#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
	13	extern unsigned long board_get_cpu_clk_f (void);
	14	#endif
	15
d87080b7 WD	16	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	17
4a9cbbe8 WD	18	/* ------------------------------------------------------------------------- */
	19
	20	/* Bus-to-Core Multiplier */
	21	#define _1x 2
	22	#define _1_5x 3
	23	#define _2x 4
	24	#define _2_5x 5
	25	#define _3x 6
	26	#define _3_5x 7
	27	#define _4x 8
	28	#define _4_5x 9
	29	#define _5x 10
	30	#define _5_5x 11
	31	#define _6x 12
	32	#define _6_5x 13
	33	#define _7x 14
	34	#define _7_5x 15
	35	#define _8x 16
	36	#define _byp -1
	37	#define _off -2
	38	#define _unk -3
	39
	40	typedef struct {
	41	int b2c_mult;
	42	int vco_div;
	43	char *freq_60x;
	44	char *freq_core;
	45	} corecnf_t;
	46
	47	/*
	48	* this table based on "Errata to MPC8260 PowerQUICC II User's Manual",
	49	* Rev. 1, 8/2000, page 10.
	50	*/
	51	corecnf_t corecnf_tab[] = {
	52	{ _1_5x, 4, " 33-100", " 33-100" }, /* 0x00 */
	53	{ _1x, 4, " 50-150", " 50-150" }, /* 0x01 */
	54	{ _1x, 8, " 25-75 ", " 25-75 " }, /* 0x02 */
	55	{ _byp, -1, " ?-? ", " ?-? " }, /* 0x03 */
	56	{ _2x, 2, " 50-150", "100-300" }, /* 0x04 */
	57	{ _2x, 4, " 25-75 ", " 50-150" }, /* 0x05 */
	58	{ _2_5x, 2, " 40-120", "100-240" }, /* 0x06 */
	59	{ _4_5x, 2, " 22-65 ", "100-300" }, /* 0x07 */
	60	{ _3x, 2, " 33-100", "100-300" }, /* 0x08 */
	61	{ _5_5x, 2, " 18-55 ", "100-300" }, /* 0x09 */
	62	{ _4x, 2, " 25-75 ", "100-300" }, /* 0x0A */
	63	{ _5x, 2, " 20-60 ", "100-300" }, /* 0x0B */
	64	{ _1_5x, 8, " 16-50 ", " 16-50 " }, /* 0x0C */
	65	{ _6x, 2, " 16-50 ", "100-300" }, /* 0x0D */
	66	{ _3_5x, 2, " 30-85 ", "100-300" }, /* 0x0E */
	67	{ _off, -1, " ?-? ", " ?-? " }, /* 0x0F */
	68	{ _3x, 4, " 16-50 ", " 50-150" }, /* 0x10 */
	69	{ _2_5x, 4, " 20-60 ", " 50-120" }, /* 0x11 */
	70	{ _6_5x, 2, " 15-46 ", "100-300" }, /* 0x12 */
	71	{ _byp, -1, " ?-? ", " ?-? " }, /* 0x13 */
	72	{ _7x, 2, " 14-43 ", "100-300" }, /* 0x14 */
	73	{ _2x, 4, " 25-75 ", " 50-150" }, /* 0x15 */
	74	{ _7_5x, 2, " 13-40 ", "100-300" }, /* 0x16 */
	75	{ _4_5x, 2, " 22-65 ", "100-300" }, /* 0x17 */
	76	{ _unk, -1, " ?-? ", " ?-? " }, /* 0x18 */
	77	{ _5_5x, 2, " 18-55 ", "100-300" }, /* 0x19 */
	78	{ _4x, 2, " 25-75 ", "100-300" }, /* 0x1A */
	79	{ _5x, 2, " 20-60 ", "100-300" }, /* 0x1B */
	80	{ _8x, 2, " 12-38 ", "100-300" }, /* 0x1C */
	81	{ _6x, 2, " 16-50 ", "100-300" }, /* 0x1D */
82	{ _3_5x, 2, " 30-85 ", "100-300" }, /* 0x1E */
83	{ _off, -1, " ?-? ", " ?-? " }, /* 0x1F */
84	};
85
86	/* ------------------------------------------------------------------------- */
87
88	/*
89	*
90	*/
91
92	int get_clocks (void)
93	{
6d0f6bcf	94	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
4a9cbbe8 WD	95	ulong clkin;
4a9cbbe8 WD	96	ulong sccr, dfbrg;
89a7b78c	97	ulong scmr, corecnf, plldf, pllmf;
4a9cbbe8 WD	98	corecnf_t *cp;
	99
	100	#if !defined(CONFIG_8260_CLKIN)
	101	#error clock measuring not implemented yet - define CONFIG_8260_CLKIN
fa230445 HS	102	#else
	103	#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
	104	clkin = board_get_cpu_clk_f ();
4a9cbbe8 WD	105	#else
4a9cbbe8 WD	106	clkin = CONFIG_8260_CLKIN;
fa230445	107	#endif
4a9cbbe8 WD	108	#endif
	109
	110	sccr = immap->im_clkrst.car_sccr;
	111	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	112
	113	scmr = immap->im_clkrst.car_scmr;
	114	corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
4a9cbbe8 WD	115	cp = &corecnf_tab[corecnf];
4a9cbbe8 WD	116
e1599e83 WD	117	/* HiP7, HiP7 Rev01, HiP7 RevA */
	118	if ((get_pvr () == PVR_8260_HIP7) \|\|
	119	(get_pvr () == PVR_8260_HIP7R1) \|\|
	120	(get_pvr () == PVR_8260_HIP7RA)) {
8564acf9	121	pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
748cd059	122	gd->arch.vco_out = clkin * (pllmf + 1);
8564acf9 WD	123	} else { /* HiP3, HiP4 */
	124	pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
	125	plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
748cd059	126	gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
8564acf9	127	}
4a9cbbe8	128
748cd059	129	gd->arch.cpm_clk = gd->arch.vco_out / 2;
4a9cbbe8	130	gd->bus_clk = clkin;
748cd059 SG	131	gd->arch.scc_clk = gd->arch.vco_out / 4;
748cd059 SG	132	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
4a9cbbe8 WD	133
	134	if (cp->b2c_mult > 0) {
	135	gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
	136	} else {
	137	gd->cpu_clk = clkin;
	138	}
	139
f2302d44 SR	140	#ifdef CONFIG_PCI
	141	gd->pci_clk = clkin;
	142
	143	if (sccr & SCCR_PCI_MODE) {
	144	uint pci_div;
	145	uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
	146
	147	if (sccr & SCCR_PCI_MODCK) {
	148	pci_div = 2;
	149	if (pcidf == 9) {
	150	pci_div *= 5;
	151	} else if (pcidf == 0xB) {
	152	pci_div *= 6;
	153	} else {
	154	pci_div *= (pcidf + 1);
	155	}
	156	} else {
	157	pci_div = pcidf + 1;
	158	}
	159
748cd059	160	gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div;
f2302d44 SR	161	}
	162	#endif
	163
4a9cbbe8 WD	164	return (0);
	165	}
	166
	167	int prt_8260_clks (void)
	168	{
6d0f6bcf	169	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
4a9cbbe8	170	ulong sccr, dfbrg;
23466d6a	171	ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
4a9cbbe8 WD	172	corecnf_t *cp;
	173
	174	sccr = immap->im_clkrst.car_sccr;
	175	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	176
	177	scmr = immap->im_clkrst.car_scmr;
	178	corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
	179	busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
	180	cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
	181	plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
	182	pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
23466d6a	183	pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
4a9cbbe8 WD	184
	185	cp = &corecnf_tab[corecnf];
	186
4b9206ed	187	puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
4a9cbbe8 WD	188
	189	switch (cp->b2c_mult) {
	190	case _byp:
4b9206ed	191	puts ("BYPASS");
4a9cbbe8 WD	192	break;
	193
	194	case _off:
4b9206ed	195	puts ("OFF");
4a9cbbe8 WD	196	break;
	197
	198	case _unk:
4b9206ed	199	puts ("UNKNOWN");
4a9cbbe8 WD	200	break;
	201
	202	default:
	203	printf ("%d%sx",
	204	cp->b2c_mult / 2,
	205	(cp->b2c_mult % 2) ? ".5" : "");
	206	break;
	207	}
	208
	209	printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
	210	cp->vco_div, cp->freq_60x, cp->freq_core);
	211
	212	printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
23466d6a WD	213	"plldf %ld, pllmf %ld, pcidf %ld\n",
	214	dfbrg, corecnf, busdf, cpmdf,
	215	plldf, pllmf, pcidf);
4a9cbbe8 WD	216
4a9cbbe8 WD	217	printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
748cd059	218	gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk);
4a9cbbe8	219
4b9206ed	220	printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
748cd059	221	gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk);
f2302d44 SR	222	#ifdef CONFIG_PCI
	223	printf (" - pci_clk %10ld\n", gd->pci_clk);
	224	#endif
4b9206ed WD	225	putc ('\n');
4b9206ed WD	226
4a9cbbe8 WD	227	return (0);
4a9cbbe8 WD	228	}