[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc83xx / speed.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc83xx.h>
#include <command.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

/* ----------------------------------------------------------------- */

typedef enum {
	_unk,
	_off,
	_byp,
	_x8,
	_x4,
	_x2,
	_x1,
	_1x,
	_1_5x,
	_2x,
	_2_5x,
	_3x
} mult_t;

typedef struct {
	mult_t core_csb_ratio;
	mult_t vco_divider;
} corecnf_t;

static corecnf_t corecnf_tab[] = {
	{_byp, _byp},		/* 0x00 */
	{_byp, _byp},		/* 0x01 */
	{_byp, _byp},		/* 0x02 */
	{_byp, _byp},		/* 0x03 */
	{_byp, _byp},		/* 0x04 */
	{_byp, _byp},		/* 0x05 */
	{_byp, _byp},		/* 0x06 */
	{_byp, _byp},		/* 0x07 */
	{_1x, _x2},		/* 0x08 */
	{_1x, _x4},		/* 0x09 */
	{_1x, _x8},		/* 0x0A */
	{_1x, _x8},		/* 0x0B */
	{_1_5x, _x2},		/* 0x0C */
	{_1_5x, _x4},		/* 0x0D */
	{_1_5x, _x8},		/* 0x0E */
	{_1_5x, _x8},		/* 0x0F */
	{_2x, _x2},		/* 0x10 */
	{_2x, _x4},		/* 0x11 */
	{_2x, _x8},		/* 0x12 */
	{_2x, _x8},		/* 0x13 */
	{_2_5x, _x2},		/* 0x14 */
	{_2_5x, _x4},		/* 0x15 */
	{_2_5x, _x8},		/* 0x16 */
	{_2_5x, _x8},		/* 0x17 */
	{_3x, _x2},		/* 0x18 */
	{_3x, _x4},		/* 0x19 */
	{_3x, _x8},		/* 0x1A */
	{_3x, _x8},		/* 0x1B */
};

/* ----------------------------------------------------------------- */

/*
 *
 */
int get_clocks(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 pci_sync_in;
	u8 spmf;
	u8 clkin_div;
	u32 sccr;
	u32 corecnf_tab_index;
	u8 corepll;
	u32 lcrr;

	u32 csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	u32 tsec1_clk;
	u32 tsec2_clk;
	u32 usbdr_clk;
#elif defined(CONFIG_MPC8309)
	u32 usbdr_clk;
#endif
#ifdef CONFIG_MPC834x
	u32 usbmph_clk;
#endif
	u32 core_clk;
	u32 i2c1_clk;
#if !defined(CONFIG_MPC832x)
	u32 i2c2_clk;
#endif
#if defined(CONFIG_MPC8315)
	u32 tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	u32 sdhc_clk;
#endif
#if !defined(CONFIG_MPC8309)
	u32 enc_clk;
#endif
	u32 lbiu_clk;
	u32 lclk_clk;
	u32 mem_clk;
#if defined(CONFIG_MPC8360)
	u32 mem_sec_clk;
#endif
#if defined(CONFIG_QE)
	u32 qepmf;
	u32 qepdf;
	u32 qe_clk;
	u32 brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	u32 pciexp1_clk;
	u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	u32 sata_clk;
#endif

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);

	if (im->reset.rcwh & HRCWH_PCI_HOST) {
#if defined(CONFIG_83XX_CLKIN)
		pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	} else {
#if defined(CONFIG_83XX_PCICLK)
		pci_sync_in = CONFIG_83XX_PCICLK;
#else
		pci_sync_in = 0xDEADBEEF;
#endif
	}

	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;

	sccr = im->clk.sccr;

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	case 0:
		tsec1_clk = 0;
		break;
	case 1:
		tsec1_clk = csb_clk;
		break;
	case 2:
		tsec1_clk = csb_clk / 2;
		break;
	case 3:
		tsec1_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TSEC1CM value */
		return -2;
	}
#endif

#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	case 0:
		usbdr_clk = 0;
		break;
	case 1:
		usbdr_clk = csb_clk;
		break;
	case 2:
		usbdr_clk = csb_clk / 2;
		break;
	case 3:
		usbdr_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_USBDRCM value */
		return -3;
	}
#endif

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	case 0:
		tsec2_clk = 0;
		break;
	case 1:
		tsec2_clk = csb_clk;
		break;
	case 2:
		tsec2_clk = csb_clk / 2;
		break;
	case 3:
		tsec2_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TSEC2CM value */
		return -4;
	}
#elif defined(CONFIG_MPC8313)
	tsec2_clk = tsec1_clk;

	if (!(sccr & SCCR_TSEC1ON))
		tsec1_clk = 0;
	if (!(sccr & SCCR_TSEC2ON))
		tsec2_clk = 0;
#endif

#if defined(CONFIG_MPC834x)
	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	case 0:
		usbmph_clk = 0;
		break;
	case 1:
		usbmph_clk = csb_clk;
		break;
	case 2:
		usbmph_clk = csb_clk / 2;
		break;
	case 3:
		usbmph_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_USBMPHCM value */
		return -5;
	}

	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
		/* if USB MPH clock is not disabled and
		 * USB DR clock is not disabled then
		 * USB MPH & USB DR must have the same rate
		 */
		return -6;
	}
#endif
#if !defined(CONFIG_MPC8309)
	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	case 0:
		enc_clk = 0;
		break;
	case 1:
		enc_clk = csb_clk;
		break;
	case 2:
		enc_clk = csb_clk / 2;
		break;
	case 3:
		enc_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_ENCCM value */
		return -7;
	}
#endif

#if defined(CONFIG_FSL_ESDHC)
	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	case 0:
		sdhc_clk = 0;
		break;
	case 1:
		sdhc_clk = csb_clk;
		break;
	case 2:
		sdhc_clk = csb_clk / 2;
		break;
	case 3:
		sdhc_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_SDHCCM value */
		return -8;
	}
#endif
#if defined(CONFIG_MPC8315)
	switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
	case 0:
		tdm_clk = 0;
		break;
	case 1:
		tdm_clk = csb_clk;
		break;
	case 2:
		tdm_clk = csb_clk / 2;
		break;
	case 3:
		tdm_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_TDMCM value */
		return -8;
	}
#endif

#if defined(CONFIG_MPC834x)
	i2c1_clk = tsec2_clk;
#elif defined(CONFIG_MPC8360)
	i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832x)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
	i2c1_clk = sdhc_clk;
#elif defined(CONFIG_MPC837x)
	i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC8309)
	i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_MPC832x)
	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif

#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
	case 0:
		pciexp1_clk = 0;
		break;
	case 1:
		pciexp1_clk = csb_clk;
		break;
	case 2:
		pciexp1_clk = csb_clk / 2;
		break;
	case 3:
		pciexp1_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_PCIEXP1CM value */
		return -9;
	}

	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	case 0:
		pciexp2_clk = 0;
		break;
	case 1:
		pciexp2_clk = csb_clk;
		break;
	case 2:
		pciexp2_clk = csb_clk / 2;
		break;
	case 3:
		pciexp2_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_PCIEXP2CM value */
		return -10;
	}
#endif

#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
	case 0:
		sata_clk = 0;
		break;
	case 1:
		sata_clk = csb_clk;
		break;
	case 2:
		sata_clk = csb_clk / 2;
		break;
	case 3:
		sata_clk = csb_clk / 3;
		break;
	default:
		/* unkown SCCR_SATACM value */
		return -11;
	}
#endif

	lbiu_clk = csb_clk *
		   (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
	switch (lcrr) {
	case 2:
	case 4:
	case 8:
		lclk_clk = lbiu_clk / lcrr;
		break;
	default:
		/* unknown lcrr */
		return -12;
	}

	mem_clk = csb_clk *
		  (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;

#if defined(CONFIG_MPC8360)
	mem_sec_clk = csb_clk * (1 +
		       ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif

	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
		/* corecnf_tab_index is too high, possibly worng value */
		return -11;
	}
	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	case _byp:
	case _x1:
	case _1x:
		core_clk = csb_clk;
		break;
	case _1_5x:
		core_clk = (3 * csb_clk) / 2;
		break;
	case _2x:
		core_clk = 2 * csb_clk;
		break;
	case _2_5x:
		core_clk = (5 * csb_clk) / 2;
		break;
	case _3x:
		core_clk = 3 * csb_clk;
		break;
	default:
		/* unkown core to csb ratio */
		return -13;
	}

#if defined(CONFIG_QE)
	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
	brg_clk = qe_clk / 2;
#endif

	gd->arch.csb_clk = csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	gd->arch.tsec1_clk = tsec1_clk;
	gd->arch.tsec2_clk = tsec2_clk;
	gd->arch.usbdr_clk = usbdr_clk;
#elif defined(CONFIG_MPC8309)
	gd->arch.usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834x)
	gd->arch.usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_MPC8315)
	gd->arch.tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
	gd->arch.sdhc_clk = sdhc_clk;
#endif
	gd->arch.core_clk = core_clk;
	gd->arch.i2c1_clk = i2c1_clk;
#if !defined(CONFIG_MPC832x)
	gd->arch.i2c2_clk = i2c2_clk;
#endif
#if !defined(CONFIG_MPC8309)
	gd->arch.enc_clk = enc_clk;
#endif
	gd->arch.lbiu_clk = lbiu_clk;
	gd->arch.lclk_clk = lclk_clk;
	gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
	gd->arch.mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_QE)
	gd->arch.qe_clk = qe_clk;
	gd->arch.brg_clk = brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	gd->arch.pciexp1_clk = pciexp1_clk;
	gd->arch.pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	gd->arch.sata_clk = sata_clk;
#endif
	gd->pci_clk = pci_sync_in;
	gd->cpu_clk = gd->arch.core_clk;
	gd->bus_clk = gd->arch.csb_clk;
	return 0;

}

/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq(ulong dummy)
{
	return gd->arch.csb_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq(ulong dummy)
{
	return gd->mem_clk;
}

static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	char buf[32];

	printf("Clock configuration:\n");
	printf("  Core:                %-4s MHz\n",
	       strmhz(buf, gd->arch.core_clk));
	printf("  Coherent System Bus: %-4s MHz\n",
	       strmhz(buf, gd->arch.csb_clk));
#if defined(CONFIG_QE)
	printf("  QE:                  %-4s MHz\n",
	       strmhz(buf, gd->arch.qe_clk));
	printf("  BRG:                 %-4s MHz\n",
	       strmhz(buf, gd->arch.brg_clk));
#endif
	printf("  Local Bus Controller:%-4s MHz\n",
	       strmhz(buf, gd->arch.lbiu_clk));
	printf("  Local Bus:           %-4s MHz\n",
	       strmhz(buf, gd->arch.lclk_clk));
	printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_MPC8360)
	printf("  DDR Secondary:       %-4s MHz\n",
	       strmhz(buf, gd->arch.mem_sec_clk));
#endif
#if !defined(CONFIG_MPC8309)
	printf("  SEC:                 %-4s MHz\n",
	       strmhz(buf, gd->arch.enc_clk));
#endif
	printf("  I2C1:                %-4s MHz\n",
	       strmhz(buf, gd->arch.i2c1_clk));
#if !defined(CONFIG_MPC832x)
	printf("  I2C2:                %-4s MHz\n",
	       strmhz(buf, gd->arch.i2c2_clk));
#endif
#if defined(CONFIG_MPC8315)
	printf("  TDM:                 %-4s MHz\n",
	       strmhz(buf, gd->arch.tdm_clk));
#endif
#if defined(CONFIG_FSL_ESDHC)
	printf("  SDHC:                %-4s MHz\n",
	       strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
	printf("  TSEC1:               %-4s MHz\n",
	       strmhz(buf, gd->arch.tsec1_clk));
	printf("  TSEC2:               %-4s MHz\n",
	       strmhz(buf, gd->arch.tsec2_clk));
	printf("  USB DR:              %-4s MHz\n",
	       strmhz(buf, gd->arch.usbdr_clk));
#elif defined(CONFIG_MPC8309)
	printf("  USB DR:              %-4s MHz\n",
	       strmhz(buf, gd->arch.usbdr_clk));
#endif
#if defined(CONFIG_MPC834x)
	printf("  USB MPH:             %-4s MHz\n",
	       strmhz(buf, gd->arch.usbmph_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
	defined(CONFIG_MPC837x)
	printf("  PCIEXP1:             %-4s MHz\n",
	       strmhz(buf, gd->arch.pciexp1_clk));
	printf("  PCIEXP2:             %-4s MHz\n",
	       strmhz(buf, gd->arch.pciexp2_clk));
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
	printf("  SATA:                %-4s MHz\n",
	       strmhz(buf, gd->arch.sata_clk));
#endif
	return 0;
}

U_BOOT_CMD(clocks, 1, 0, do_clocks,
	"print clock configuration",
	"    clocks"
);
Commit	Line	Data
f046ccd1 EL	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
03051c3d	5	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
f046ccd1	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
f046ccd1 EL	8	*/
	9
	10	#include <common.h>
	11	#include <mpc83xx.h>
54b2d434	12	#include <command.h>
f046ccd1 EL	13	#include <asm/processor.h>
f046ccd1 EL	14
d87080b7 WD	15	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	16
f046ccd1 EL	17	/* ----------------------------------------------------------------- */
	18
	19	typedef enum {
	20	_unk,
	21	_off,
	22	_byp,
	23	_x8,
	24	_x4,
	25	_x2,
	26	_x1,
	27	_1x,
	28	_1_5x,
	29	_2x,
	30	_2_5x,
	31	_3x
	32	} mult_t;
	33
	34	typedef struct {
	35	mult_t core_csb_ratio;
f7fb2e70	36	mult_t vco_divider;
f046ccd1 EL	37	} corecnf_t;
f046ccd1 EL	38
a2873bde	39	static corecnf_t corecnf_tab[] = {
f7fb2e70 KP	40	{_byp, _byp}, /* 0x00 */
	41	{_byp, _byp}, /* 0x01 */
	42	{_byp, _byp}, /* 0x02 */
	43	{_byp, _byp}, /* 0x03 */
	44	{_byp, _byp}, /* 0x04 */
	45	{_byp, _byp}, /* 0x05 */
	46	{_byp, _byp}, /* 0x06 */
	47	{_byp, _byp}, /* 0x07 */
	48	{_1x, _x2}, /* 0x08 */
	49	{_1x, _x4}, /* 0x09 */
	50	{_1x, _x8}, /* 0x0A */
	51	{_1x, _x8}, /* 0x0B */
	52	{_1_5x, _x2}, /* 0x0C */
	53	{_1_5x, _x4}, /* 0x0D */
	54	{_1_5x, _x8}, /* 0x0E */
	55	{_1_5x, _x8}, /* 0x0F */
	56	{_2x, _x2}, /* 0x10 */
	57	{_2x, _x4}, /* 0x11 */
	58	{_2x, _x8}, /* 0x12 */
	59	{_2x, _x8}, /* 0x13 */
	60	{_2_5x, _x2}, /* 0x14 */
	61	{_2_5x, _x4}, /* 0x15 */
	62	{_2_5x, _x8}, /* 0x16 */
	63	{_2_5x, _x8}, /* 0x17 */
	64	{_3x, _x2}, /* 0x18 */
	65	{_3x, _x4}, /* 0x19 */
	66	{_3x, _x8}, /* 0x1A */
	67	{_3x, _x8}, /* 0x1B */
f046ccd1 EL	68	};
	69
	70	/* ----------------------------------------------------------------- */
	71
	72	/*
	73	*
	74	*/
f7fb2e70	75	int get_clocks(void)
f046ccd1	76	{
6d0f6bcf	77	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
f046ccd1	78	u32 pci_sync_in;
f7fb2e70 KP	79	u8 spmf;
f7fb2e70 KP	80	u8 clkin_div;
f046ccd1 EL	81	u32 sccr;
f046ccd1 EL	82	u32 corecnf_tab_index;
f7fb2e70	83	u8 corepll;
f046ccd1	84	u32 lcrr;
de1d0a69	85
f046ccd1	86	u32 csb_clk;
7c619ddc IY	87	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	88	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	89	u32 tsec1_clk;
f046ccd1 EL	90	u32 tsec2_clk;
f046ccd1	91	u32 usbdr_clk;
a88731a6 GF	92	#elif defined(CONFIG_MPC8309)
a88731a6 GF	93	u32 usbdr_clk;
7c98e519	94	#endif
2c7920af	95	#ifdef CONFIG_MPC834x
7c98e519	96	u32 usbmph_clk;
5f820439 DL	97	#endif
	98	u32 core_clk;
	99	u32 i2c1_clk;
2c7920af	100	#if !defined(CONFIG_MPC832x)
5f820439	101	u32 i2c2_clk;
03051c3d	102	#endif
555da617 DL	103	#if defined(CONFIG_MPC8315)
	104	u32 tdm_clk;
	105	#endif
27ef578d	106	#if defined(CONFIG_FSL_ESDHC)
03051c3d	107	u32 sdhc_clk;
24c3aca3	108	#endif
a88731a6	109	#if !defined(CONFIG_MPC8309)
f046ccd1	110	u32 enc_clk;
a88731a6	111	#endif
f046ccd1 EL	112	u32 lbiu_clk;
f046ccd1 EL	113	u32 lclk_clk;
35cf155c	114	u32 mem_clk;
24c3aca3	115	#if defined(CONFIG_MPC8360)
35cf155c	116	u32 mem_sec_clk;
24c3aca3	117	#endif
4b5282de	118	#if defined(CONFIG_QE)
5f820439 DL	119	u32 qepmf;
5f820439 DL	120	u32 qepdf;
5f820439 DL	121	u32 qe_clk;
	122	u32 brg_clk;
	123	#endif
7c619ddc IY	124	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	125	defined(CONFIG_MPC837x)
03051c3d DL	126	u32 pciexp1_clk;
03051c3d DL	127	u32 pciexp2_clk;
555da617	128	#endif
2c7920af	129	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
03051c3d DL	130	u32 sata_clk;
03051c3d DL	131	#endif
de1d0a69	132
f7fb2e70	133	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
f046ccd1	134	return -1;
de1d0a69	135
5f820439	136	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
e6f2e902	137
5f820439 DL	138	if (im->reset.rcwh & HRCWH_PCI_HOST) {
	139	#if defined(CONFIG_83XX_CLKIN)
	140	pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
	141	#else
	142	pci_sync_in = 0xDEADBEEF;
	143	#endif
	144	} else {
	145	#if defined(CONFIG_83XX_PCICLK)
	146	pci_sync_in = CONFIG_83XX_PCICLK;
	147	#else
	148	pci_sync_in = 0xDEADBEEF;
	149	#endif
f046ccd1	150	}
f046ccd1	151
26e5f794	152	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
5f820439	153	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
de1d0a69	154
f046ccd1	155	sccr = im->clk.sccr;
5f820439	156
7c619ddc IY	157	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	158	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	159	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
	160	case 0:
	161	tsec1_clk = 0;
	162	break;
	163	case 1:
	164	tsec1_clk = csb_clk;
	165	break;
	166	case 2:
	167	tsec1_clk = csb_clk / 2;
	168	break;
	169	case 3:
	170	tsec1_clk = csb_clk / 3;
	171	break;
	172	default:
	173	/* unkown SCCR_TSEC1CM value */
03051c3d	174	return -2;
f046ccd1	175	}
8afad91f	176	#endif
de1d0a69	177
8afad91f GF	178	#if defined(CONFIG_MPC830x) \|\| defined(CONFIG_MPC831x) \|\| \
8afad91f GF	179	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
7c98e519 SW	180	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
	181	case 0:
	182	usbdr_clk = 0;
	183	break;
	184	case 1:
	185	usbdr_clk = csb_clk;
	186	break;
	187	case 2:
	188	usbdr_clk = csb_clk / 2;
	189	break;
	190	case 3:
	191	usbdr_clk = csb_clk / 3;
	192	break;
	193	default:
	194	/* unkown SCCR_USBDRCM value */
03051c3d	195	return -3;
7c98e519 SW	196	}
	197	#endif
	198
7c619ddc IY	199	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC8315) \|\| \
7c619ddc IY	200	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
f046ccd1 EL	201	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
	202	case 0:
	203	tsec2_clk = 0;
	204	break;
	205	case 1:
	206	tsec2_clk = csb_clk;
	207	break;
	208	case 2:
	209	tsec2_clk = csb_clk / 2;
	210	break;
	211	case 3:
	212	tsec2_clk = csb_clk / 3;
	213	break;
	214	default:
	215	/* unkown SCCR_TSEC2CM value */
03051c3d	216	return -4;
f046ccd1	217	}
555da617	218	#elif defined(CONFIG_MPC8313)
03051c3d	219	tsec2_clk = tsec1_clk;
de1d0a69	220
03051c3d DL	221	if (!(sccr & SCCR_TSEC1ON))
	222	tsec1_clk = 0;
	223	if (!(sccr & SCCR_TSEC2ON))
	224	tsec2_clk = 0;
	225	#endif
de1d0a69	226
2c7920af	227	#if defined(CONFIG_MPC834x)
f046ccd1 EL	228	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
	229	case 0:
	230	usbmph_clk = 0;
	231	break;
	232	case 1:
	233	usbmph_clk = csb_clk;
	234	break;
	235	case 2:
	236	usbmph_clk = csb_clk / 2;
	237	break;
	238	case 3:
	239	usbmph_clk = csb_clk / 3;
	240	break;
	241	default:
	242	/* unkown SCCR_USBMPHCM value */
03051c3d	243	return -5;
f046ccd1 EL	244	}
f046ccd1 EL	245
f7fb2e70 KP	246	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
	247	/* if USB MPH clock is not disabled and
	248	* USB DR clock is not disabled then
	249	* USB MPH & USB DR must have the same rate
	250	*/
03051c3d DL	251	return -6;
	252	}
	253	#endif
a88731a6	254	#if !defined(CONFIG_MPC8309)
03051c3d DL	255	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
	256	case 0:
	257	enc_clk = 0;
	258	break;
	259	case 1:
	260	enc_clk = csb_clk;
	261	break;
	262	case 2:
	263	enc_clk = csb_clk / 2;
	264	break;
	265	case 3:
	266	enc_clk = csb_clk / 3;
	267	break;
	268	default:
	269	/* unkown SCCR_ENCCM value */
	270	return -7;
f046ccd1	271	}
a88731a6	272	#endif
7c98e519	273
27ef578d	274	#if defined(CONFIG_FSL_ESDHC)
03051c3d DL	275	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
	276	case 0:
	277	sdhc_clk = 0;
	278	break;
	279	case 1:
	280	sdhc_clk = csb_clk;
	281	break;
	282	case 2:
	283	sdhc_clk = csb_clk / 2;
	284	break;
	285	case 3:
	286	sdhc_clk = csb_clk / 3;
	287	break;
	288	default:
	289	/* unkown SCCR_SDHCCM value */
	290	return -8;
	291	}
5f820439	292	#endif
555da617 DL	293	#if defined(CONFIG_MPC8315)
	294	switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
	295	case 0:
	296	tdm_clk = 0;
	297	break;
	298	case 1:
	299	tdm_clk = csb_clk;
	300	break;
	301	case 2:
	302	tdm_clk = csb_clk / 2;
	303	break;
	304	case 3:
	305	tdm_clk = csb_clk / 3;
	306	break;
	307	default:
	308	/* unkown SCCR_TDMCM value */
	309	return -8;
	310	}
	311	#endif
7c98e519	312
2c7920af	313	#if defined(CONFIG_MPC834x)
03051c3d DL	314	i2c1_clk = tsec2_clk;
03051c3d DL	315	#elif defined(CONFIG_MPC8360)
5f820439	316	i2c1_clk = csb_clk;
2c7920af	317	#elif defined(CONFIG_MPC832x)
03051c3d	318	i2c1_clk = enc_clk;
7c619ddc	319	#elif defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x)
03051c3d	320	i2c1_clk = enc_clk;
27ef578d	321	#elif defined(CONFIG_FSL_ESDHC)
03051c3d	322	i2c1_clk = sdhc_clk;
1bda1624 AS	323	#elif defined(CONFIG_MPC837x)
1bda1624 AS	324	i2c1_clk = enc_clk;
a88731a6 GF	325	#elif defined(CONFIG_MPC8309)
a88731a6 GF	326	i2c1_clk = csb_clk;
5f820439	327	#endif
2c7920af	328	#if !defined(CONFIG_MPC832x)
03051c3d	329	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
24c3aca3	330	#endif
de1d0a69	331
7c619ddc IY	332	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	333	defined(CONFIG_MPC837x)
03051c3d	334	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
5f820439	335	case 0:
03051c3d	336	pciexp1_clk = 0;
5f820439 DL	337	break;
5f820439 DL	338	case 1:
03051c3d	339	pciexp1_clk = csb_clk;
5f820439 DL	340	break;
5f820439 DL	341	case 2:
03051c3d	342	pciexp1_clk = csb_clk / 2;
5f820439 DL	343	break;
5f820439 DL	344	case 3:
03051c3d	345	pciexp1_clk = csb_clk / 3;
5f820439 DL	346	break;
5f820439 DL	347	default:
03051c3d DL	348	/* unkown SCCR_PCIEXP1CM value */
03051c3d DL	349	return -9;
5f820439	350	}
24c3aca3	351
03051c3d DL	352	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
	353	case 0:
	354	pciexp2_clk = 0;
	355	break;
	356	case 1:
	357	pciexp2_clk = csb_clk;
	358	break;
	359	case 2:
	360	pciexp2_clk = csb_clk / 2;
	361	break;
	362	case 3:
	363	pciexp2_clk = csb_clk / 3;
	364	break;
	365	default:
	366	/* unkown SCCR_PCIEXP2CM value */
	367	return -10;
	368	}
	369	#endif
	370
2c7920af	371	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
a8cb43a8 DL	372	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
a8cb43a8 DL	373	case 0:
03051c3d DL	374	sata_clk = 0;
03051c3d DL	375	break;
a8cb43a8	376	case 1:
03051c3d DL	377	sata_clk = csb_clk;
03051c3d DL	378	break;
a8cb43a8	379	case 2:
03051c3d DL	380	sata_clk = csb_clk / 2;
03051c3d DL	381	break;
a8cb43a8	382	case 3:
03051c3d DL	383	sata_clk = csb_clk / 3;
	384	break;
	385	default:
9e896478	386	/* unkown SCCR_SATACM value */
03051c3d DL	387	return -11;
	388	}
	389	#endif
	390
f7fb2e70	391	lbiu_clk = csb_clk *
26e5f794	392	(1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
f51cdaf1	393	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
f046ccd1 EL	394	switch (lcrr) {
	395	case 2:
	396	case 4:
	397	case 8:
	398	lclk_clk = lbiu_clk / lcrr;
	399	break;
	400	default:
	401	/* unknown lcrr */
03051c3d	402	return -12;
f046ccd1	403	}
24c3aca3	404
35cf155c	405	mem_clk = csb_clk *
26e5f794 JT	406	(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
	407	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
	408
24c3aca3	409	#if defined(CONFIG_MPC8360)
35cf155c	410	mem_sec_clk = csb_clk * (1 +
26e5f794	411	((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
5f820439 DL	412	#endif
5f820439 DL	413
f046ccd1	414	corecnf_tab_index = ((corepll & 0x1F) << 2) \| ((corepll & 0x60) >> 5);
f7fb2e70	415	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
f046ccd1 EL	416	/* corecnf_tab_index is too high, possibly worng value */
	417	return -11;
	418	}
	419	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
	420	case _byp:
	421	case _x1:
	422	case _1x:
	423	core_clk = csb_clk;
	424	break;
	425	case _1_5x:
	426	core_clk = (3 * csb_clk) / 2;
	427	break;
	428	case _2x:
	429	core_clk = 2 * csb_clk;
	430	break;
	431	case _2_5x:
f7fb2e70	432	core_clk = (5 * csb_clk) / 2;
f046ccd1 EL	433	break;
	434	case _3x:
	435	core_clk = 3 * csb_clk;
	436	break;
	437	default:
	438	/* unkown core to csb ratio */
03051c3d	439	return -13;
f046ccd1	440	}
de1d0a69	441
4b5282de	442	#if defined(CONFIG_QE)
26e5f794 JT	443	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
26e5f794 JT	444	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
f7fb2e70	445	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
5f820439 DL	446	brg_clk = qe_clk / 2;
	447	#endif
	448
c6731fe2	449	gd->arch.csb_clk = csb_clk;
7c619ddc IY	450	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	451	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
c6731fe2 SG	452	gd->arch.tsec1_clk = tsec1_clk;
	453	gd->arch.tsec2_clk = tsec2_clk;
	454	gd->arch.usbdr_clk = usbdr_clk;
a88731a6	455	#elif defined(CONFIG_MPC8309)
c6731fe2	456	gd->arch.usbdr_clk = usbdr_clk;
7c98e519	457	#endif
2c7920af	458	#if defined(CONFIG_MPC834x)
c6731fe2	459	gd->arch.usbmph_clk = usbmph_clk;
03051c3d	460	#endif
555da617	461	#if defined(CONFIG_MPC8315)
c6731fe2	462	gd->arch.tdm_clk = tdm_clk;
555da617	463	#endif
27ef578d	464	#if defined(CONFIG_FSL_ESDHC)
e9adeca3	465	gd->arch.sdhc_clk = sdhc_clk;
5f820439	466	#endif
c6731fe2	467	gd->arch.core_clk = core_clk;
609e6ec3	468	gd->arch.i2c1_clk = i2c1_clk;
2c7920af	469	#if !defined(CONFIG_MPC832x)
609e6ec3	470	gd->arch.i2c2_clk = i2c2_clk;
24c3aca3	471	#endif
a88731a6	472	#if !defined(CONFIG_MPC8309)
c6731fe2	473	gd->arch.enc_clk = enc_clk;
a88731a6	474	#endif
c6731fe2 SG	475	gd->arch.lbiu_clk = lbiu_clk;
c6731fe2 SG	476	gd->arch.lclk_clk = lclk_clk;
35cf155c	477	gd->mem_clk = mem_clk;
24c3aca3	478	#if defined(CONFIG_MPC8360)
c6731fe2	479	gd->arch.mem_sec_clk = mem_sec_clk;
24c3aca3	480	#endif
4b5282de	481	#if defined(CONFIG_QE)
45bae2e3	482	gd->arch.qe_clk = qe_clk;
1206c184	483	gd->arch.brg_clk = brg_clk;
03051c3d	484	#endif
810cb190 BC	485	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
810cb190 BC	486	defined(CONFIG_MPC837x)
c6731fe2 SG	487	gd->arch.pciexp1_clk = pciexp1_clk;
c6731fe2 SG	488	gd->arch.pciexp2_clk = pciexp2_clk;
555da617	489	#endif
2c7920af	490	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
c6731fe2	491	gd->arch.sata_clk = sata_clk;
5f820439	492	#endif
8f9e0e9f	493	gd->pci_clk = pci_sync_in;
c6731fe2 SG	494	gd->cpu_clk = gd->arch.core_clk;
c6731fe2 SG	495	gd->bus_clk = gd->arch.csb_clk;
f046ccd1	496	return 0;
5f820439	497
f046ccd1 EL	498	}
	499
	500	/********************************************
	501	* get_bus_freq
	502	* return system bus freq in Hz
	503	*********************************************/
f7fb2e70	504	ulong get_bus_freq(ulong dummy)
f046ccd1	505	{
c6731fe2	506	return gd->arch.csb_clk;
f046ccd1 EL	507	}
f046ccd1 EL	508
d29d17d7 YS	509	/********************************************
	510	* get_ddr_freq
	511	* return ddr bus freq in Hz
	512	*********************************************/
	513	ulong get_ddr_freq(ulong dummy)
	514	{
	515	return gd->mem_clk;
	516	}
	517
a2873bde	518	static int do_clocks(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
f046ccd1	519	{
08ef89ec WD	520	char buf[32];
08ef89ec WD	521
f046ccd1	522	printf("Clock configuration:\n");
c6731fe2 SG	523	printf(" Core: %-4s MHz\n",
	524	strmhz(buf, gd->arch.core_clk));
	525	printf(" Coherent System Bus: %-4s MHz\n",
	526	strmhz(buf, gd->arch.csb_clk));
4b5282de	527	#if defined(CONFIG_QE)
45bae2e3 SG	528	printf(" QE: %-4s MHz\n",
45bae2e3 SG	529	strmhz(buf, gd->arch.qe_clk));
1206c184 SG	530	printf(" BRG: %-4s MHz\n",
1206c184 SG	531	strmhz(buf, gd->arch.brg_clk));
5f820439	532	#endif
c6731fe2 SG	533	printf(" Local Bus Controller:%-4s MHz\n",
	534	strmhz(buf, gd->arch.lbiu_clk));
	535	printf(" Local Bus: %-4s MHz\n",
	536	strmhz(buf, gd->arch.lclk_clk));
08ef89ec	537	printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
24c3aca3	538	#if defined(CONFIG_MPC8360)
c6731fe2 SG	539	printf(" DDR Secondary: %-4s MHz\n",
c6731fe2 SG	540	strmhz(buf, gd->arch.mem_sec_clk));
5f820439	541	#endif
a88731a6	542	#if !defined(CONFIG_MPC8309)
c6731fe2 SG	543	printf(" SEC: %-4s MHz\n",
c6731fe2 SG	544	strmhz(buf, gd->arch.enc_clk));
a88731a6	545	#endif
609e6ec3 SG	546	printf(" I2C1: %-4s MHz\n",
609e6ec3 SG	547	strmhz(buf, gd->arch.i2c1_clk));
2c7920af	548	#if !defined(CONFIG_MPC832x)
609e6ec3 SG	549	printf(" I2C2: %-4s MHz\n",
609e6ec3 SG	550	strmhz(buf, gd->arch.i2c2_clk));
24c3aca3	551	#endif
555da617	552	#if defined(CONFIG_MPC8315)
c6731fe2 SG	553	printf(" TDM: %-4s MHz\n",
c6731fe2 SG	554	strmhz(buf, gd->arch.tdm_clk));
555da617	555	#endif
27ef578d	556	#if defined(CONFIG_FSL_ESDHC)
e9adeca3 SG	557	printf(" SDHC: %-4s MHz\n",
e9adeca3 SG	558	strmhz(buf, gd->arch.sdhc_clk));
03051c3d	559	#endif
7c619ddc IY	560	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
7c619ddc IY	561	defined(CONFIG_MPC834x) \|\| defined(CONFIG_MPC837x)
c6731fe2 SG	562	printf(" TSEC1: %-4s MHz\n",
	563	strmhz(buf, gd->arch.tsec1_clk));
	564	printf(" TSEC2: %-4s MHz\n",
	565	strmhz(buf, gd->arch.tsec2_clk));
	566	printf(" USB DR: %-4s MHz\n",
	567	strmhz(buf, gd->arch.usbdr_clk));
a88731a6	568	#elif defined(CONFIG_MPC8309)
c6731fe2 SG	569	printf(" USB DR: %-4s MHz\n",
c6731fe2 SG	570	strmhz(buf, gd->arch.usbdr_clk));
7c98e519	571	#endif
2c7920af	572	#if defined(CONFIG_MPC834x)
c6731fe2 SG	573	printf(" USB MPH: %-4s MHz\n",
c6731fe2 SG	574	strmhz(buf, gd->arch.usbmph_clk));
03051c3d	575	#endif
810cb190 BC	576	#if defined(CONFIG_MPC8308) \|\| defined(CONFIG_MPC831x) \|\| \
810cb190 BC	577	defined(CONFIG_MPC837x)
c6731fe2 SG	578	printf(" PCIEXP1: %-4s MHz\n",
	579	strmhz(buf, gd->arch.pciexp1_clk));
	580	printf(" PCIEXP2: %-4s MHz\n",
	581	strmhz(buf, gd->arch.pciexp2_clk));
555da617	582	#endif
2c7920af	583	#if defined(CONFIG_MPC837x) \|\| defined(CONFIG_MPC8315)
c6731fe2 SG	584	printf(" SATA: %-4s MHz\n",
c6731fe2 SG	585	strmhz(buf, gd->arch.sata_clk));
5f820439	586	#endif
de1d0a69	587	return 0;
f046ccd1	588	}
54b2d434 KP	589
54b2d434 KP	590	U_BOOT_CMD(clocks, 1, 0, do_clocks,
2fb2604d	591	"print clock configuration",
a89c33db	592	" clocks"
54b2d434	593	);