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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
e4c09508 SW |
2 | /* |
3 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
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4 | */ |
5 | ||
6 | #include <common.h> | |
7 | #include <mpc83xx.h> | |
8 | ||
9 | DECLARE_GLOBAL_DATA_PTR; | |
10 | ||
11 | /* | |
12 | * Breathe some life into the CPU... | |
13 | * | |
14 | * Set up the memory map, | |
15 | * initialize a bunch of registers, | |
16 | * initialize the UPM's | |
17 | */ | |
18 | void cpu_init_f (volatile immap_t * im) | |
19 | { | |
e4c09508 | 20 | /* Pointer is writable since we allocated a register for it */ |
6d0f6bcf | 21 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
e4c09508 | 22 | |
dbcb2c0e | 23 | /* global data region was cleared in start.S */ |
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24 | |
25 | /* system performance tweaking */ | |
26 | ||
6d0f6bcf | 27 | #ifdef CONFIG_SYS_ACR_PIPE_DEP |
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28 | /* Arbiter pipeline depth */ |
29 | im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | | |
6d0f6bcf | 30 | (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); |
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31 | #endif |
32 | ||
6d0f6bcf | 33 | #ifdef CONFIG_SYS_ACR_RPTCNT |
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34 | /* Arbiter repeat count */ |
35 | im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | | |
6d0f6bcf | 36 | (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); |
e4c09508 SW |
37 | #endif |
38 | ||
6d0f6bcf | 39 | #ifdef CONFIG_SYS_SPCR_OPT |
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40 | /* Optimize transactions between CSB and other devices */ |
41 | im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | | |
6d0f6bcf | 42 | (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); |
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43 | #endif |
44 | ||
d7b4ca2b | 45 | /* Enable Time Base & Decrementer (so we will have udelay()) */ |
e4c09508 SW |
46 | im->sysconf.spcr |= SPCR_TBEN; |
47 | ||
48 | /* DDR control driver register */ | |
6d0f6bcf JCPV |
49 | #ifdef CONFIG_SYS_DDRCDR |
50 | im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; | |
e4c09508 SW |
51 | #endif |
52 | /* Output buffer impedance register */ | |
6d0f6bcf JCPV |
53 | #ifdef CONFIG_SYS_OBIR |
54 | im->sysconf.obir = CONFIG_SYS_OBIR; | |
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55 | #endif |
56 | ||
57 | /* | |
58 | * Memory Controller: | |
59 | */ | |
60 | ||
61 | /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary | |
62 | * addresses - these have to be modified later when FLASH size | |
63 | * has been determined | |
64 | */ | |
65 | ||
6d0f6bcf JCPV |
66 | #if defined(CONFIG_SYS_NAND_BR_PRELIM) \ |
67 | && defined(CONFIG_SYS_NAND_OR_PRELIM) \ | |
68 | && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ | |
69 | && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) | |
f51cdaf1 BB |
70 | set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); |
71 | set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); | |
6d0f6bcf JCPV |
72 | im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; |
73 | im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; | |
e4c09508 | 74 | #else |
6d0f6bcf | 75 | #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined |
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76 | #endif |
77 | } | |
78 | ||
79 | /* | |
80 | * Get timebase clock frequency (like cpu_clk in Hz) | |
81 | */ | |
82 | unsigned long get_tbclk(void) | |
83 | { | |
84 | return (gd->bus_clk + 3L) / 4L; | |
85 | } | |
86 | ||
87 | void puts(const char *str) | |
88 | { | |
89 | while (*str) | |
90 | putc(*str++); | |
91 | } |