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f046ccd1 EL |
1 | /* |
2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> | |
3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> | |
4 | * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> | |
e4c09508 | 5 | * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. |
f046ccd1 EL |
6 | * |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /* | |
27 | * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards | |
28 | */ | |
29 | ||
25ddd1fb | 30 | #include <asm-offsets.h> |
f046ccd1 | 31 | #include <config.h> |
de1d0a69 | 32 | #include <mpc83xx.h> |
09c2e90c AB |
33 | #ifndef CONFIG_IDENT_STRING |
34 | #define CONFIG_IDENT_STRING "MPC83XX" | |
35 | #endif | |
f046ccd1 EL |
36 | #include <version.h> |
37 | ||
38 | #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ | |
39 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
40 | ||
41 | #include <ppc_asm.tmpl> | |
42 | #include <ppc_defs.h> | |
43 | ||
44 | #include <asm/cache.h> | |
45 | #include <asm/mmu.h> | |
d98b0523 | 46 | #include <asm/u-boot.h> |
f046ccd1 | 47 | |
f046ccd1 EL |
48 | /* We don't want the MMU yet. |
49 | */ | |
50 | #undef MSR_KERNEL | |
51 | ||
52 | /* | |
53 | * Floating Point enable, Machine Check and Recoverable Interr. | |
54 | */ | |
55 | #ifdef DEBUG | |
56 | #define MSR_KERNEL (MSR_FP|MSR_RI) | |
57 | #else | |
58 | #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) | |
59 | #endif | |
60 | ||
06f60ae3 SW |
61 | #if defined(CONFIG_NAND_SPL) || \ |
62 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) | |
63 | #define MINIMAL_SPL | |
64 | #endif | |
65 | ||
66 | #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ | |
67 | !defined(CONFIG_SYS_RAMBOOT) | |
6d0f6bcf | 68 | #define CONFIG_SYS_FLASHBOOT |
e4c09508 SW |
69 | #endif |
70 | ||
f046ccd1 EL |
71 | /* |
72 | * Set up GOT: Global Offset Table | |
73 | * | |
0f8aa159 | 74 | * Use r12 to access the GOT |
f046ccd1 EL |
75 | */ |
76 | START_GOT | |
77 | GOT_ENTRY(_GOT2_TABLE_) | |
e4c09508 | 78 | GOT_ENTRY(__bss_start) |
44c6e659 | 79 | GOT_ENTRY(__bss_end__) |
f046ccd1 | 80 | |
06f60ae3 | 81 | #ifndef MINIMAL_SPL |
e4c09508 | 82 | GOT_ENTRY(_FIXUP_TABLE_) |
f046ccd1 EL |
83 | GOT_ENTRY(_start) |
84 | GOT_ENTRY(_start_of_vectors) | |
85 | GOT_ENTRY(_end_of_vectors) | |
86 | GOT_ENTRY(transfer_to_handler) | |
e4c09508 | 87 | #endif |
f046ccd1 EL |
88 | END_GOT |
89 | ||
90 | /* | |
f35f3582 JVB |
91 | * The Hard Reset Configuration Word (HRCW) table is in the first 64 |
92 | * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 | |
93 | * times so the processor can fetch it out of flash whether the flash | |
94 | * is 8, 16, 32, or 64 bits wide (hardware trickery). | |
f046ccd1 | 95 | */ |
f046ccd1 EL |
96 | .text |
97 | #define _HRCW_TABLE_ENTRY(w) \ | |
98 | .fill 8,1,(((w)>>24)&0xff); \ | |
99 | .fill 8,1,(((w)>>16)&0xff); \ | |
100 | .fill 8,1,(((w)>> 8)&0xff); \ | |
101 | .fill 8,1,(((w) )&0xff) | |
102 | ||
6d0f6bcf JCPV |
103 | _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) |
104 | _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) | |
f046ccd1 | 105 | |
f35f3582 JVB |
106 | /* |
107 | * Magic number and version string - put it after the HRCW since it | |
108 | * cannot be first in flash like it is in many other processors. | |
109 | */ | |
110 | .long 0x27051956 /* U-Boot Magic Number */ | |
111 | ||
112 | .globl version_string | |
113 | version_string: | |
09c2e90c | 114 | .ascii U_BOOT_VERSION_STRING, "\0" |
f35f3582 | 115 | |
455a4691 RM |
116 | .align 2 |
117 | ||
118 | .globl enable_addr_trans | |
119 | enable_addr_trans: | |
120 | /* enable address translation */ | |
121 | mfmsr r5 | |
122 | ori r5, r5, (MSR_IR | MSR_DR) | |
123 | mtmsr r5 | |
124 | isync | |
125 | blr | |
126 | ||
127 | .globl disable_addr_trans | |
128 | disable_addr_trans: | |
129 | /* disable address translation */ | |
130 | mflr r4 | |
131 | mfmsr r3 | |
132 | andi. r0, r3, (MSR_IR | MSR_DR) | |
133 | beqlr | |
134 | andc r3, r3, r0 | |
135 | mtspr SRR0, r4 | |
136 | mtspr SRR1, r3 | |
137 | rfi | |
138 | ||
139 | .globl get_pvr | |
140 | get_pvr: | |
141 | mfspr r3, PVR | |
142 | blr | |
143 | ||
144 | .globl ppcDWstore | |
145 | ppcDWstore: | |
146 | lfd 1, 0(r4) | |
147 | stfd 1, 0(r3) | |
148 | blr | |
149 | ||
150 | .globl ppcDWload | |
151 | ppcDWload: | |
152 | lfd 1, 0(r3) | |
153 | stfd 1, 0(r4) | |
154 | blr | |
f046ccd1 | 155 | |
f046ccd1 EL |
156 | #ifndef CONFIG_DEFAULT_IMMR |
157 | #error CONFIG_DEFAULT_IMMR must be defined | |
6d0f6bcf JCPV |
158 | #endif /* CONFIG_SYS_DEFAULT_IMMR */ |
159 | #ifndef CONFIG_SYS_IMMR | |
160 | #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR | |
161 | #endif /* CONFIG_SYS_IMMR */ | |
f046ccd1 EL |
162 | |
163 | /* | |
164 | * After configuration, a system reset exception is executed using the | |
165 | * vector at offset 0x100 relative to the base set by MSR[IP]. If | |
166 | * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the | |
167 | * base address is 0xfff00000. In the case of a Power On Reset or Hard | |
168 | * Reset, the value of MSR[IP] is determined by the CIP field in the | |
169 | * HRCW. | |
170 | * | |
171 | * Other bits in the HRCW set up the Base Address and Port Size in BR0. | |
172 | * This determines the location of the boot ROM (flash or EPROM) in the | |
173 | * processor's address space at boot time. As long as the HRCW is set up | |
174 | * so that we eventually end up executing the code below when the | |
175 | * processor executes the reset exception, the actual values used should | |
176 | * not matter. | |
177 | * | |
178 | * Once we have got here, the address mask in OR0 is cleared so that the | |
179 | * bottom 32K of the boot ROM is effectively repeated all throughout the | |
180 | * processor's address space, after which we can jump to the absolute | |
181 | * address at which the boot ROM was linked at compile time, and proceed | |
182 | * to initialise the memory controller without worrying if the rug will | |
183 | * be pulled out from under us, so to speak (it will be fine as long as | |
184 | * we configure BR0 with the same boot ROM link address). | |
185 | */ | |
186 | . = EXC_OFF_SYS_RESET | |
187 | ||
188 | .globl _start | |
189 | _start: /* time t 0 */ | |
f046ccd1 EL |
190 | lis r4, CONFIG_DEFAULT_IMMR@h |
191 | nop | |
52ebd9c1 | 192 | |
f046ccd1 | 193 | mfmsr r5 /* save msr contents */ |
66778761 SW |
194 | |
195 | /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ | |
196 | bl 1f | |
197 | 1: mflr r7 | |
198 | ||
6d0f6bcf JCPV |
199 | lis r3, CONFIG_SYS_IMMR@h |
200 | ori r3, r3, CONFIG_SYS_IMMR@l | |
66778761 SW |
201 | |
202 | lwz r6, IMMRBAR(r4) | |
203 | isync | |
204 | ||
f046ccd1 | 205 | stw r3, IMMRBAR(r4) |
66778761 SW |
206 | lwz r6, 0(r7) /* Arbitrary external load */ |
207 | isync | |
208 | ||
209 | lwz r6, IMMRBAR(r3) | |
210 | isync | |
de1d0a69 | 211 | |
f046ccd1 EL |
212 | /* Initialise the E300 processor core */ |
213 | /*------------------------------------------*/ | |
de1d0a69 | 214 | |
06f60ae3 SW |
215 | #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ |
216 | defined(CONFIG_NAND_SPL) | |
fa7b1c07 LS |
217 | /* The FCM begins execution after only the first page |
218 | * is loaded. Wait for the rest before branching | |
219 | * to another flash page. | |
220 | */ | |
66778761 | 221 | 1: lwz r6, 0x50b0(r3) |
fa7b1c07 LS |
222 | andi. r6, r6, 1 |
223 | beq 1b | |
224 | #endif | |
225 | ||
f046ccd1 | 226 | bl init_e300_core |
de1d0a69 | 227 | |
6d0f6bcf | 228 | #ifdef CONFIG_SYS_FLASHBOOT |
f046ccd1 EL |
229 | |
230 | /* Inflate flash location so it appears everywhere, calculate */ | |
231 | /* the absolute address in final location of the FLASH, jump */ | |
232 | /* there and deflate the flash size back to minimal size */ | |
233 | /*------------------------------------------------------------*/ | |
234 | bl map_flash_by_law1 | |
6d0f6bcf JCPV |
235 | lis r4, (CONFIG_SYS_MONITOR_BASE)@h |
236 | ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l | |
f046ccd1 EL |
237 | addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET |
238 | mtlr r5 | |
239 | blr | |
240 | in_flash: | |
241 | #if 1 /* Remapping flash with LAW0. */ | |
242 | bl remap_flash_by_law0 | |
243 | #endif | |
6d0f6bcf | 244 | #endif /* CONFIG_SYS_FLASHBOOT */ |
f046ccd1 | 245 | |
2688e2f9 KG |
246 | /* setup the bats */ |
247 | bl setup_bats | |
248 | sync | |
249 | ||
250 | /* | |
251 | * Cache must be enabled here for stack-in-cache trick. | |
252 | * This means we need to enable the BATS. | |
253 | * This means: | |
254 | * 1) for the EVB, original gt regs need to be mapped | |
255 | * 2) need to have an IBAT for the 0xf region, | |
256 | * we are running there! | |
257 | * Cache should be turned on after BATs, since by default | |
258 | * everything is write-through. | |
259 | * The init-mem BAT can be reused after reloc. The old | |
260 | * gt-regs BAT can be reused after board_init_f calls | |
261 | * board_early_init_f (EVB only). | |
262 | */ | |
263 | /* enable address translation */ | |
264 | bl enable_addr_trans | |
265 | sync | |
266 | ||
6eb2a44e | 267 | /* enable the data cache */ |
2688e2f9 KG |
268 | bl dcache_enable |
269 | sync | |
6d0f6bcf | 270 | #ifdef CONFIG_SYS_INIT_RAM_LOCK |
2688e2f9 KG |
271 | bl lock_ram_in_cache |
272 | sync | |
273 | #endif | |
274 | ||
275 | /* set up the stack pointer in our newly created | |
276 | * cache-ram (r1) */ | |
6d0f6bcf JCPV |
277 | lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h |
278 | ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l | |
2688e2f9 KG |
279 | |
280 | li r0, 0 /* Make room for stack frame header and */ | |
281 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
282 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
283 | ||
f046ccd1 EL |
284 | |
285 | /* let the C-code set up the rest */ | |
2688e2f9 | 286 | /* */ |
f046ccd1 EL |
287 | /* Be careful to keep code relocatable & stack humble */ |
288 | /*------------------------------------------------------*/ | |
289 | ||
290 | GET_GOT /* initialize GOT access */ | |
8c4734e9 | 291 | |
f046ccd1 | 292 | /* r3: IMMR */ |
6d0f6bcf | 293 | lis r3, CONFIG_SYS_IMMR@h |
f046ccd1 EL |
294 | /* run low-level CPU init code (in Flash)*/ |
295 | bl cpu_init_f | |
296 | ||
f046ccd1 EL |
297 | /* run 1st part of board init code (in Flash)*/ |
298 | bl board_init_f | |
299 | ||
52ebd9c1 PT |
300 | /* NOTREACHED - board_init_f() does not return */ |
301 | ||
06f60ae3 | 302 | #ifndef MINIMAL_SPL |
f046ccd1 EL |
303 | /* |
304 | * Vector Table | |
305 | */ | |
306 | ||
307 | .globl _start_of_vectors | |
308 | _start_of_vectors: | |
309 | ||
310 | /* Machine check */ | |
311 | STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) | |
312 | ||
313 | /* Data Storage exception. */ | |
314 | STD_EXCEPTION(0x300, DataStorage, UnknownException) | |
315 | ||
316 | /* Instruction Storage exception. */ | |
317 | STD_EXCEPTION(0x400, InstStorage, UnknownException) | |
318 | ||
319 | /* External Interrupt exception. */ | |
320 | #ifndef FIXME | |
321 | STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) | |
de1d0a69 | 322 | #endif |
f046ccd1 EL |
323 | |
324 | /* Alignment exception. */ | |
325 | . = 0x600 | |
326 | Alignment: | |
02032e8f | 327 | EXCEPTION_PROLOG(SRR0, SRR1) |
f046ccd1 EL |
328 | mfspr r4,DAR |
329 | stw r4,_DAR(r21) | |
330 | mfspr r5,DSISR | |
331 | stw r5,_DSISR(r21) | |
332 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 | 333 | EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) |
f046ccd1 EL |
334 | |
335 | /* Program check exception */ | |
336 | . = 0x700 | |
337 | ProgramCheck: | |
02032e8f | 338 | EXCEPTION_PROLOG(SRR0, SRR1) |
f046ccd1 | 339 | addi r3,r1,STACK_FRAME_OVERHEAD |
fc4e1887 JT |
340 | EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, |
341 | MSR_KERNEL, COPY_EE) | |
f046ccd1 EL |
342 | |
343 | STD_EXCEPTION(0x800, FPUnavailable, UnknownException) | |
344 | ||
345 | /* I guess we could implement decrementer, and may have | |
346 | * to someday for timekeeping. | |
347 | */ | |
348 | STD_EXCEPTION(0x900, Decrementer, timer_interrupt) | |
349 | ||
350 | STD_EXCEPTION(0xa00, Trap_0a, UnknownException) | |
351 | STD_EXCEPTION(0xb00, Trap_0b, UnknownException) | |
352 | STD_EXCEPTION(0xc00, SystemCall, UnknownException) | |
353 | STD_EXCEPTION(0xd00, SingleStep, UnknownException) | |
354 | ||
355 | STD_EXCEPTION(0xe00, Trap_0e, UnknownException) | |
356 | STD_EXCEPTION(0xf00, Trap_0f, UnknownException) | |
357 | ||
358 | STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) | |
359 | STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) | |
360 | STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) | |
361 | #ifdef DEBUG | |
362 | . = 0x1300 | |
363 | /* | |
364 | * This exception occurs when the program counter matches the | |
365 | * Instruction Address Breakpoint Register (IABR). | |
366 | * | |
367 | * I want the cpu to halt if this occurs so I can hunt around | |
368 | * with the debugger and look at things. | |
369 | * | |
370 | * When DEBUG is defined, both machine check enable (in the MSR) | |
371 | * and checkstop reset enable (in the reset mode register) are | |
372 | * turned off and so a checkstop condition will result in the cpu | |
373 | * halting. | |
374 | * | |
375 | * I force the cpu into a checkstop condition by putting an illegal | |
376 | * instruction here (at least this is the theory). | |
377 | * | |
378 | * well - that didnt work, so just do an infinite loop! | |
379 | */ | |
380 | 1: b 1b | |
381 | #else | |
382 | STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) | |
383 | #endif | |
384 | STD_EXCEPTION(0x1400, SMI, UnknownException) | |
385 | ||
386 | STD_EXCEPTION(0x1500, Trap_15, UnknownException) | |
387 | STD_EXCEPTION(0x1600, Trap_16, UnknownException) | |
388 | STD_EXCEPTION(0x1700, Trap_17, UnknownException) | |
389 | STD_EXCEPTION(0x1800, Trap_18, UnknownException) | |
390 | STD_EXCEPTION(0x1900, Trap_19, UnknownException) | |
391 | STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) | |
392 | STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) | |
393 | STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) | |
394 | STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) | |
395 | STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) | |
396 | STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) | |
397 | STD_EXCEPTION(0x2000, Trap_20, UnknownException) | |
398 | STD_EXCEPTION(0x2100, Trap_21, UnknownException) | |
399 | STD_EXCEPTION(0x2200, Trap_22, UnknownException) | |
400 | STD_EXCEPTION(0x2300, Trap_23, UnknownException) | |
401 | STD_EXCEPTION(0x2400, Trap_24, UnknownException) | |
402 | STD_EXCEPTION(0x2500, Trap_25, UnknownException) | |
403 | STD_EXCEPTION(0x2600, Trap_26, UnknownException) | |
404 | STD_EXCEPTION(0x2700, Trap_27, UnknownException) | |
405 | STD_EXCEPTION(0x2800, Trap_28, UnknownException) | |
406 | STD_EXCEPTION(0x2900, Trap_29, UnknownException) | |
407 | STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) | |
408 | STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) | |
409 | STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) | |
410 | STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) | |
411 | STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) | |
412 | STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) | |
413 | ||
414 | ||
415 | .globl _end_of_vectors | |
416 | _end_of_vectors: | |
417 | ||
418 | . = 0x3000 | |
419 | ||
420 | /* | |
421 | * This code finishes saving the registers to the exception frame | |
422 | * and jumps to the appropriate handler for the exception. | |
423 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
424 | */ | |
425 | .globl transfer_to_handler | |
426 | transfer_to_handler: | |
427 | stw r22,_NIP(r21) | |
428 | lis r22,MSR_POW@h | |
429 | andc r23,r23,r22 | |
430 | stw r23,_MSR(r21) | |
431 | SAVE_GPR(7, r21) | |
432 | SAVE_4GPRS(8, r21) | |
433 | SAVE_8GPRS(12, r21) | |
434 | SAVE_8GPRS(24, r21) | |
435 | mflr r23 | |
436 | andi. r24,r23,0x3f00 /* get vector offset */ | |
437 | stw r24,TRAP(r21) | |
438 | li r22,0 | |
439 | stw r22,RESULT(r21) | |
440 | lwz r24,0(r23) /* virtual address of handler */ | |
441 | lwz r23,4(r23) /* where to go when done */ | |
442 | mtspr SRR0,r24 | |
443 | mtspr SRR1,r20 | |
444 | mtlr r23 | |
445 | SYNC | |
446 | rfi /* jump to handler, enable MMU */ | |
447 | ||
448 | int_return: | |
449 | mfmsr r28 /* Disable interrupts */ | |
450 | li r4,0 | |
451 | ori r4,r4,MSR_EE | |
452 | andc r28,r28,r4 | |
453 | SYNC /* Some chip revs need this... */ | |
454 | mtmsr r28 | |
455 | SYNC | |
456 | lwz r2,_CTR(r1) | |
457 | lwz r0,_LINK(r1) | |
458 | mtctr r2 | |
459 | mtlr r0 | |
460 | lwz r2,_XER(r1) | |
461 | lwz r0,_CCR(r1) | |
462 | mtspr XER,r2 | |
463 | mtcrf 0xFF,r0 | |
464 | REST_10GPRS(3, r1) | |
465 | REST_10GPRS(13, r1) | |
466 | REST_8GPRS(23, r1) | |
467 | REST_GPR(31, r1) | |
468 | lwz r2,_NIP(r1) /* Restore environment */ | |
469 | lwz r0,_MSR(r1) | |
470 | mtspr SRR0,r2 | |
471 | mtspr SRR1,r0 | |
472 | lwz r0,GPR0(r1) | |
473 | lwz r2,GPR2(r1) | |
474 | lwz r1,GPR1(r1) | |
475 | SYNC | |
476 | rfi | |
06f60ae3 | 477 | #endif /* !MINIMAL_SPL */ |
f046ccd1 EL |
478 | |
479 | /* | |
480 | * This code initialises the E300 processor core | |
481 | * (conforms to PowerPC 603e spec) | |
482 | * Note: expects original MSR contents to be in r5. | |
483 | */ | |
484 | .globl init_e300_core | |
485 | init_e300_core: /* time t 10 */ | |
486 | /* Initialize machine status; enable machine check interrupt */ | |
487 | /*-----------------------------------------------------------*/ | |
488 | ||
489 | li r3, MSR_KERNEL /* Set ME and RI flags */ | |
490 | rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ | |
491 | #ifdef DEBUG | |
492 | rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ | |
493 | #endif | |
494 | SYNC /* Some chip revs need this... */ | |
495 | mtmsr r3 | |
496 | SYNC | |
497 | mtspr SRR1, r3 /* Make SRR1 match MSR */ | |
498 | ||
499 | ||
6d0f6bcf | 500 | lis r3, CONFIG_SYS_IMMR@h |
f046ccd1 | 501 | #if defined(CONFIG_WATCHDOG) |
f6970d0c | 502 | /* Initialise the Watchdog values and reset it (if req) */ |
f046ccd1 | 503 | /*------------------------------------------------------*/ |
6d0f6bcf | 504 | lis r4, CONFIG_SYS_WATCHDOG_VALUE |
f046ccd1 EL |
505 | ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) |
506 | stw r4, SWCRR(r3) | |
de1d0a69 | 507 | |
f046ccd1 | 508 | /* and reset it */ |
de1d0a69 | 509 | |
f046ccd1 EL |
510 | li r4, 0x556C |
511 | sth r4, SWSRR@l(r3) | |
f6db9456 | 512 | li r4, -0x55C7 |
f046ccd1 EL |
513 | sth r4, SWSRR@l(r3) |
514 | #else | |
f6970d0c | 515 | /* Disable Watchdog */ |
f046ccd1 | 516 | /*-------------------*/ |
ec00c335 KG |
517 | lwz r4, SWCRR(r3) |
518 | /* Check to see if its enabled for disabling | |
519 | once disabled by SW you can't re-enable */ | |
520 | andi. r4, r4, 0x4 | |
521 | beq 1f | |
f046ccd1 EL |
522 | xor r4, r4, r4 |
523 | stw r4, SWCRR(r3) | |
ec00c335 | 524 | 1: |
f046ccd1 EL |
525 | #endif /* CONFIG_WATCHDOG */ |
526 | ||
46497056 NS |
527 | #if defined(CONFIG_MASK_AER_AO) |
528 | /* Write the Arbiter Event Enable to mask Address Only traps. */ | |
529 | /* This prevents the dcbz instruction from being trapped when */ | |
530 | /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ | |
531 | /* COHERENCY bit is set in the WIMG bits, which is often */ | |
532 | /* needed for PCI operation. */ | |
533 | lwz r4, 0x0808(r3) | |
534 | rlwinm r0, r4, 0, ~AER_AO | |
535 | stw r0, 0x0808(r3) | |
536 | #endif /* CONFIG_MASK_AER_AO */ | |
537 | ||
f046ccd1 EL |
538 | /* Initialize the Hardware Implementation-dependent Registers */ |
539 | /* HID0 also contains cache control */ | |
6eb2a44e | 540 | /* - force invalidation of data and instruction caches */ |
f046ccd1 EL |
541 | /*------------------------------------------------------*/ |
542 | ||
6d0f6bcf JCPV |
543 | lis r3, CONFIG_SYS_HID0_INIT@h |
544 | ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l | |
f046ccd1 EL |
545 | SYNC |
546 | mtspr HID0, r3 | |
547 | ||
6d0f6bcf JCPV |
548 | lis r3, CONFIG_SYS_HID0_FINAL@h |
549 | ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l | |
f046ccd1 EL |
550 | SYNC |
551 | mtspr HID0, r3 | |
552 | ||
6d0f6bcf JCPV |
553 | lis r3, CONFIG_SYS_HID2@h |
554 | ori r3, r3, CONFIG_SYS_HID2@l | |
f046ccd1 EL |
555 | SYNC |
556 | mtspr HID2, r3 | |
557 | ||
f046ccd1 EL |
558 | /* Done! */ |
559 | /*------------------------------*/ | |
de1d0a69 | 560 | blr |
f046ccd1 | 561 | |
2688e2f9 KG |
562 | /* setup_bats - set them up to some initial state */ |
563 | .globl setup_bats | |
564 | setup_bats: | |
565 | addis r0, r0, 0x0000 | |
566 | ||
567 | /* IBAT 0 */ | |
6d0f6bcf JCPV |
568 | addis r4, r0, CONFIG_SYS_IBAT0L@h |
569 | ori r4, r4, CONFIG_SYS_IBAT0L@l | |
570 | addis r3, r0, CONFIG_SYS_IBAT0U@h | |
571 | ori r3, r3, CONFIG_SYS_IBAT0U@l | |
2688e2f9 KG |
572 | mtspr IBAT0L, r4 |
573 | mtspr IBAT0U, r3 | |
2688e2f9 KG |
574 | |
575 | /* DBAT 0 */ | |
6d0f6bcf JCPV |
576 | addis r4, r0, CONFIG_SYS_DBAT0L@h |
577 | ori r4, r4, CONFIG_SYS_DBAT0L@l | |
578 | addis r3, r0, CONFIG_SYS_DBAT0U@h | |
579 | ori r3, r3, CONFIG_SYS_DBAT0U@l | |
2688e2f9 KG |
580 | mtspr DBAT0L, r4 |
581 | mtspr DBAT0U, r3 | |
2688e2f9 KG |
582 | |
583 | /* IBAT 1 */ | |
6d0f6bcf JCPV |
584 | addis r4, r0, CONFIG_SYS_IBAT1L@h |
585 | ori r4, r4, CONFIG_SYS_IBAT1L@l | |
586 | addis r3, r0, CONFIG_SYS_IBAT1U@h | |
587 | ori r3, r3, CONFIG_SYS_IBAT1U@l | |
2688e2f9 KG |
588 | mtspr IBAT1L, r4 |
589 | mtspr IBAT1U, r3 | |
2688e2f9 KG |
590 | |
591 | /* DBAT 1 */ | |
6d0f6bcf JCPV |
592 | addis r4, r0, CONFIG_SYS_DBAT1L@h |
593 | ori r4, r4, CONFIG_SYS_DBAT1L@l | |
594 | addis r3, r0, CONFIG_SYS_DBAT1U@h | |
595 | ori r3, r3, CONFIG_SYS_DBAT1U@l | |
2688e2f9 KG |
596 | mtspr DBAT1L, r4 |
597 | mtspr DBAT1U, r3 | |
2688e2f9 KG |
598 | |
599 | /* IBAT 2 */ | |
6d0f6bcf JCPV |
600 | addis r4, r0, CONFIG_SYS_IBAT2L@h |
601 | ori r4, r4, CONFIG_SYS_IBAT2L@l | |
602 | addis r3, r0, CONFIG_SYS_IBAT2U@h | |
603 | ori r3, r3, CONFIG_SYS_IBAT2U@l | |
2688e2f9 KG |
604 | mtspr IBAT2L, r4 |
605 | mtspr IBAT2U, r3 | |
2688e2f9 KG |
606 | |
607 | /* DBAT 2 */ | |
6d0f6bcf JCPV |
608 | addis r4, r0, CONFIG_SYS_DBAT2L@h |
609 | ori r4, r4, CONFIG_SYS_DBAT2L@l | |
610 | addis r3, r0, CONFIG_SYS_DBAT2U@h | |
611 | ori r3, r3, CONFIG_SYS_DBAT2U@l | |
2688e2f9 KG |
612 | mtspr DBAT2L, r4 |
613 | mtspr DBAT2U, r3 | |
2688e2f9 KG |
614 | |
615 | /* IBAT 3 */ | |
6d0f6bcf JCPV |
616 | addis r4, r0, CONFIG_SYS_IBAT3L@h |
617 | ori r4, r4, CONFIG_SYS_IBAT3L@l | |
618 | addis r3, r0, CONFIG_SYS_IBAT3U@h | |
619 | ori r3, r3, CONFIG_SYS_IBAT3U@l | |
2688e2f9 KG |
620 | mtspr IBAT3L, r4 |
621 | mtspr IBAT3U, r3 | |
2688e2f9 KG |
622 | |
623 | /* DBAT 3 */ | |
6d0f6bcf JCPV |
624 | addis r4, r0, CONFIG_SYS_DBAT3L@h |
625 | ori r4, r4, CONFIG_SYS_DBAT3L@l | |
626 | addis r3, r0, CONFIG_SYS_DBAT3U@h | |
627 | ori r3, r3, CONFIG_SYS_DBAT3U@l | |
2688e2f9 KG |
628 | mtspr DBAT3L, r4 |
629 | mtspr DBAT3U, r3 | |
2688e2f9 | 630 | |
31d82672 | 631 | #ifdef CONFIG_HIGH_BATS |
2688e2f9 | 632 | /* IBAT 4 */ |
6d0f6bcf JCPV |
633 | addis r4, r0, CONFIG_SYS_IBAT4L@h |
634 | ori r4, r4, CONFIG_SYS_IBAT4L@l | |
635 | addis r3, r0, CONFIG_SYS_IBAT4U@h | |
636 | ori r3, r3, CONFIG_SYS_IBAT4U@l | |
2688e2f9 KG |
637 | mtspr IBAT4L, r4 |
638 | mtspr IBAT4U, r3 | |
2688e2f9 KG |
639 | |
640 | /* DBAT 4 */ | |
6d0f6bcf JCPV |
641 | addis r4, r0, CONFIG_SYS_DBAT4L@h |
642 | ori r4, r4, CONFIG_SYS_DBAT4L@l | |
643 | addis r3, r0, CONFIG_SYS_DBAT4U@h | |
644 | ori r3, r3, CONFIG_SYS_DBAT4U@l | |
2688e2f9 KG |
645 | mtspr DBAT4L, r4 |
646 | mtspr DBAT4U, r3 | |
2688e2f9 KG |
647 | |
648 | /* IBAT 5 */ | |
6d0f6bcf JCPV |
649 | addis r4, r0, CONFIG_SYS_IBAT5L@h |
650 | ori r4, r4, CONFIG_SYS_IBAT5L@l | |
651 | addis r3, r0, CONFIG_SYS_IBAT5U@h | |
652 | ori r3, r3, CONFIG_SYS_IBAT5U@l | |
2688e2f9 KG |
653 | mtspr IBAT5L, r4 |
654 | mtspr IBAT5U, r3 | |
2688e2f9 KG |
655 | |
656 | /* DBAT 5 */ | |
6d0f6bcf JCPV |
657 | addis r4, r0, CONFIG_SYS_DBAT5L@h |
658 | ori r4, r4, CONFIG_SYS_DBAT5L@l | |
659 | addis r3, r0, CONFIG_SYS_DBAT5U@h | |
660 | ori r3, r3, CONFIG_SYS_DBAT5U@l | |
2688e2f9 KG |
661 | mtspr DBAT5L, r4 |
662 | mtspr DBAT5U, r3 | |
2688e2f9 KG |
663 | |
664 | /* IBAT 6 */ | |
6d0f6bcf JCPV |
665 | addis r4, r0, CONFIG_SYS_IBAT6L@h |
666 | ori r4, r4, CONFIG_SYS_IBAT6L@l | |
667 | addis r3, r0, CONFIG_SYS_IBAT6U@h | |
668 | ori r3, r3, CONFIG_SYS_IBAT6U@l | |
2688e2f9 KG |
669 | mtspr IBAT6L, r4 |
670 | mtspr IBAT6U, r3 | |
2688e2f9 KG |
671 | |
672 | /* DBAT 6 */ | |
6d0f6bcf JCPV |
673 | addis r4, r0, CONFIG_SYS_DBAT6L@h |
674 | ori r4, r4, CONFIG_SYS_DBAT6L@l | |
675 | addis r3, r0, CONFIG_SYS_DBAT6U@h | |
676 | ori r3, r3, CONFIG_SYS_DBAT6U@l | |
2688e2f9 KG |
677 | mtspr DBAT6L, r4 |
678 | mtspr DBAT6U, r3 | |
2688e2f9 KG |
679 | |
680 | /* IBAT 7 */ | |
6d0f6bcf JCPV |
681 | addis r4, r0, CONFIG_SYS_IBAT7L@h |
682 | ori r4, r4, CONFIG_SYS_IBAT7L@l | |
683 | addis r3, r0, CONFIG_SYS_IBAT7U@h | |
684 | ori r3, r3, CONFIG_SYS_IBAT7U@l | |
2688e2f9 KG |
685 | mtspr IBAT7L, r4 |
686 | mtspr IBAT7U, r3 | |
2688e2f9 KG |
687 | |
688 | /* DBAT 7 */ | |
6d0f6bcf JCPV |
689 | addis r4, r0, CONFIG_SYS_DBAT7L@h |
690 | ori r4, r4, CONFIG_SYS_DBAT7L@l | |
691 | addis r3, r0, CONFIG_SYS_DBAT7U@h | |
692 | ori r3, r3, CONFIG_SYS_DBAT7U@l | |
2688e2f9 KG |
693 | mtspr DBAT7L, r4 |
694 | mtspr DBAT7U, r3 | |
2688e2f9 KG |
695 | #endif |
696 | ||
e4c09508 SW |
697 | isync |
698 | ||
699 | /* invalidate all tlb's | |
700 | * | |
701 | * From the 603e User Manual: "The 603e provides the ability to | |
702 | * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) | |
703 | * instruction invalidates the TLB entry indexed by the EA, and | |
704 | * operates on both the instruction and data TLBs simultaneously | |
705 | * invalidating four TLB entries (both sets in each TLB). The | |
706 | * index corresponds to bits 15-19 of the EA. To invalidate all | |
707 | * entries within both TLBs, 32 tlbie instructions should be | |
708 | * issued, incrementing this field by one each time." | |
709 | * | |
710 | * "Note that the tlbia instruction is not implemented on the | |
711 | * 603e." | |
712 | * | |
713 | * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 | |
714 | * incrementing by 0x1000 each time. The code below is sort of | |
a47a12be | 715 | * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S |
e4c09508 | 716 | * |
2688e2f9 KG |
717 | */ |
718 | lis r3, 0 | |
719 | lis r5, 2 | |
720 | ||
721 | 1: | |
722 | tlbie r3 | |
723 | addi r3, r3, 0x1000 | |
724 | cmp 0, 0, r3, r5 | |
725 | blt 1b | |
726 | ||
727 | blr | |
728 | ||
f046ccd1 EL |
729 | /* Cache functions. |
730 | * | |
731 | * Note: requires that all cache bits in | |
732 | * HID0 are in the low half word. | |
733 | */ | |
06f60ae3 | 734 | #ifndef MINIMAL_SPL |
f046ccd1 EL |
735 | .globl icache_enable |
736 | icache_enable: | |
737 | mfspr r3, HID0 | |
738 | ori r3, r3, HID0_ICE | |
6eb2a44e | 739 | li r4, HID0_ICFI|HID0_ILOCK |
f046ccd1 EL |
740 | andc r3, r3, r4 |
741 | ori r4, r3, HID0_ICFI | |
742 | isync | |
743 | mtspr HID0, r4 /* sets enable and invalidate, clears lock */ | |
744 | isync | |
745 | mtspr HID0, r3 /* clears invalidate */ | |
746 | blr | |
747 | ||
748 | .globl icache_disable | |
749 | icache_disable: | |
750 | mfspr r3, HID0 | |
751 | lis r4, 0 | |
6eb2a44e | 752 | ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK |
f046ccd1 | 753 | andc r3, r3, r4 |
f046ccd1 | 754 | isync |
6eb2a44e | 755 | mtspr HID0, r3 /* clears invalidate, enable and lock */ |
f046ccd1 EL |
756 | blr |
757 | ||
758 | .globl icache_status | |
759 | icache_status: | |
760 | mfspr r3, HID0 | |
a7c66ad2 | 761 | rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 |
f046ccd1 | 762 | blr |
06f60ae3 | 763 | #endif /* !MINIMAL_SPL */ |
f046ccd1 EL |
764 | |
765 | .globl dcache_enable | |
766 | dcache_enable: | |
767 | mfspr r3, HID0 | |
2688e2f9 KG |
768 | li r5, HID0_DCFI|HID0_DLOCK |
769 | andc r3, r3, r5 | |
2688e2f9 | 770 | ori r3, r3, HID0_DCE |
f046ccd1 | 771 | sync |
6eb2a44e | 772 | mtspr HID0, r3 /* enable, no invalidate */ |
f046ccd1 EL |
773 | blr |
774 | ||
775 | .globl dcache_disable | |
776 | dcache_disable: | |
6eb2a44e NS |
777 | mflr r4 |
778 | bl flush_dcache /* uses r3 and r5 */ | |
f046ccd1 | 779 | mfspr r3, HID0 |
6eb2a44e NS |
780 | li r5, HID0_DCE|HID0_DLOCK |
781 | andc r3, r3, r5 | |
782 | ori r5, r3, HID0_DCFI | |
f046ccd1 | 783 | sync |
6eb2a44e | 784 | mtspr HID0, r5 /* sets invalidate, clears enable and lock */ |
f046ccd1 EL |
785 | sync |
786 | mtspr HID0, r3 /* clears invalidate */ | |
6eb2a44e | 787 | mtlr r4 |
f046ccd1 EL |
788 | blr |
789 | ||
790 | .globl dcache_status | |
791 | dcache_status: | |
792 | mfspr r3, HID0 | |
a7c66ad2 | 793 | rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 |
f046ccd1 EL |
794 | blr |
795 | ||
6eb2a44e NS |
796 | .globl flush_dcache |
797 | flush_dcache: | |
798 | lis r3, 0 | |
6d0f6bcf | 799 | lis r5, CONFIG_SYS_CACHELINE_SIZE |
6eb2a44e NS |
800 | 1: cmp 0, 1, r3, r5 |
801 | bge 2f | |
802 | lwz r5, 0(r3) | |
6d0f6bcf | 803 | lis r5, CONFIG_SYS_CACHELINE_SIZE |
6eb2a44e NS |
804 | addi r3, r3, 0x4 |
805 | b 1b | |
806 | 2: blr | |
807 | ||
f046ccd1 EL |
808 | /*-------------------------------------------------------------------*/ |
809 | ||
810 | /* | |
811 | * void relocate_code (addr_sp, gd, addr_moni) | |
812 | * | |
813 | * This "function" does not return, instead it continues in RAM | |
814 | * after relocating the monitor code. | |
815 | * | |
816 | * r3 = dest | |
817 | * r4 = src | |
818 | * r5 = length in bytes | |
819 | * r6 = cachelinesize | |
820 | */ | |
821 | .globl relocate_code | |
822 | relocate_code: | |
823 | mr r1, r3 /* Set new stack pointer */ | |
824 | mr r9, r4 /* Save copy of Global Data pointer */ | |
825 | mr r10, r5 /* Save copy of Destination Address */ | |
826 | ||
0f8aa159 | 827 | GET_GOT |
f046ccd1 | 828 | mr r3, r5 /* Destination Address */ |
6d0f6bcf JCPV |
829 | lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
830 | ori r4, r4, CONFIG_SYS_MONITOR_BASE@l | |
e4c09508 | 831 | lwz r5, GOT(__bss_start) |
f046ccd1 | 832 | sub r5, r5, r4 |
6d0f6bcf | 833 | li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ |
f046ccd1 EL |
834 | |
835 | /* | |
836 | * Fix GOT pointer: | |
837 | * | |
6d0f6bcf | 838 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) |
f046ccd1 EL |
839 | * + Destination Address |
840 | * | |
841 | * Offset: | |
842 | */ | |
843 | sub r15, r10, r4 | |
844 | ||
845 | /* First our own GOT */ | |
0f8aa159 | 846 | add r12, r12, r15 |
f046ccd1 EL |
847 | /* then the one used by the C code */ |
848 | add r30, r30, r15 | |
849 | ||
850 | /* | |
851 | * Now relocate code | |
852 | */ | |
853 | ||
854 | cmplw cr1,r3,r4 | |
855 | addi r0,r5,3 | |
856 | srwi. r0,r0,2 | |
857 | beq cr1,4f /* In place copy is not necessary */ | |
858 | beq 7f /* Protect against 0 count */ | |
859 | mtctr r0 | |
860 | bge cr1,2f | |
861 | la r8,-4(r4) | |
862 | la r7,-4(r3) | |
863 | ||
864 | /* copy */ | |
865 | 1: lwzu r0,4(r8) | |
866 | stwu r0,4(r7) | |
867 | bdnz 1b | |
868 | ||
869 | addi r0,r5,3 | |
870 | srwi. r0,r0,2 | |
871 | mtctr r0 | |
872 | la r8,-4(r4) | |
873 | la r7,-4(r3) | |
de1d0a69 JL |
874 | |
875 | /* and compare */ | |
f046ccd1 EL |
876 | 20: lwzu r20,4(r8) |
877 | lwzu r21,4(r7) | |
878 | xor. r22, r20, r21 | |
879 | bne 30f | |
880 | bdnz 20b | |
881 | b 4f | |
882 | ||
883 | /* compare failed */ | |
884 | 30: li r3, 0 | |
885 | blr | |
886 | ||
887 | 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ | |
888 | add r8,r4,r0 | |
889 | add r7,r3,r0 | |
890 | 3: lwzu r0,-4(r8) | |
891 | stwu r0,-4(r7) | |
892 | bdnz 3b | |
f046ccd1 EL |
893 | |
894 | /* | |
895 | * Now flush the cache: note that we must start from a cache aligned | |
896 | * address. Otherwise we might miss one cache line. | |
897 | */ | |
2688e2f9 | 898 | 4: cmpwi r6,0 |
f046ccd1 | 899 | add r5,r3,r5 |
2688e2f9 | 900 | beq 7f /* Always flush prefetch queue in any case */ |
f046ccd1 EL |
901 | subi r0,r6,1 |
902 | andc r3,r3,r0 | |
f046ccd1 EL |
903 | mr r4,r3 |
904 | 5: dcbst 0,r4 | |
905 | add r4,r4,r6 | |
906 | cmplw r4,r5 | |
907 | blt 5b | |
2688e2f9 | 908 | sync /* Wait for all dcbst to complete on bus */ |
f046ccd1 EL |
909 | mr r4,r3 |
910 | 6: icbi 0,r4 | |
911 | add r4,r4,r6 | |
912 | cmplw r4,r5 | |
913 | blt 6b | |
2688e2f9 | 914 | 7: sync /* Wait for all icbi to complete on bus */ |
f046ccd1 EL |
915 | isync |
916 | ||
917 | /* | |
918 | * We are done. Do not return, instead branch to second part of board | |
919 | * initialization, now running from RAM. | |
920 | */ | |
f046ccd1 EL |
921 | addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET |
922 | mtlr r0 | |
923 | blr | |
924 | ||
925 | in_ram: | |
926 | ||
927 | /* | |
0f8aa159 | 928 | * Relocation Function, r12 point to got2+0x8000 |
f046ccd1 EL |
929 | * |
930 | * Adjust got2 pointers, no need to check for 0, this code | |
931 | * already puts a few entries in the table. | |
932 | */ | |
933 | li r0,__got2_entries@sectoff@l | |
934 | la r3,GOT(_GOT2_TABLE_) | |
935 | lwz r11,GOT(_GOT2_TABLE_) | |
936 | mtctr r0 | |
937 | sub r11,r3,r11 | |
938 | addi r3,r3,-4 | |
939 | 1: lwzu r0,4(r3) | |
afc3ba0f JT |
940 | cmpwi r0,0 |
941 | beq- 2f | |
f046ccd1 EL |
942 | add r0,r0,r11 |
943 | stw r0,0(r3) | |
afc3ba0f | 944 | 2: bdnz 1b |
f046ccd1 | 945 | |
06f60ae3 | 946 | #ifndef MINIMAL_SPL |
f046ccd1 EL |
947 | /* |
948 | * Now adjust the fixups and the pointers to the fixups | |
949 | * in case we need to move ourselves again. | |
950 | */ | |
afc3ba0f | 951 | li r0,__fixup_entries@sectoff@l |
f046ccd1 EL |
952 | lwz r3,GOT(_FIXUP_TABLE_) |
953 | cmpwi r0,0 | |
954 | mtctr r0 | |
955 | addi r3,r3,-4 | |
956 | beq 4f | |
957 | 3: lwzu r4,4(r3) | |
958 | lwzux r0,r4,r11 | |
d1e0b10a | 959 | cmpwi r0,0 |
f046ccd1 | 960 | add r0,r0,r11 |
34bbf618 | 961 | stw r4,0(r3) |
d1e0b10a | 962 | beq- 5f |
f046ccd1 | 963 | stw r0,0(r4) |
d1e0b10a | 964 | 5: bdnz 3b |
f046ccd1 | 965 | 4: |
e4c09508 SW |
966 | #endif |
967 | ||
f046ccd1 EL |
968 | clear_bss: |
969 | /* | |
970 | * Now clear BSS segment | |
971 | */ | |
972 | lwz r3,GOT(__bss_start) | |
973 | #if defined(CONFIG_HYMOD) | |
974 | /* | |
975 | * For HYMOD - the environment is the very last item in flash. | |
976 | * The real .bss stops just before environment starts, so only | |
977 | * clear up to that point. | |
978 | * | |
979 | * taken from mods for FADS board | |
980 | */ | |
981 | lwz r4,GOT(environment) | |
982 | #else | |
44c6e659 | 983 | lwz r4,GOT(__bss_end__) |
f046ccd1 EL |
984 | #endif |
985 | ||
986 | cmplw 0, r3, r4 | |
987 | beq 6f | |
988 | ||
989 | li r0, 0 | |
990 | 5: | |
991 | stw r0, 0(r3) | |
992 | addi r3, r3, 4 | |
993 | cmplw 0, r3, r4 | |
994 | bne 5b | |
995 | 6: | |
996 | ||
997 | mr r3, r9 /* Global Data pointer */ | |
998 | mr r4, r10 /* Destination Address */ | |
999 | bl board_init_r | |
1000 | ||
06f60ae3 | 1001 | #ifndef MINIMAL_SPL |
f046ccd1 EL |
1002 | /* |
1003 | * Copy exception vector code to low memory | |
1004 | * | |
1005 | * r3: dest_addr | |
1006 | * r7: source address, r8: end address, r9: target address | |
1007 | */ | |
1008 | .globl trap_init | |
1009 | trap_init: | |
0f8aa159 JT |
1010 | mflr r4 /* save link register */ |
1011 | GET_GOT | |
f046ccd1 EL |
1012 | lwz r7, GOT(_start) |
1013 | lwz r8, GOT(_end_of_vectors) | |
1014 | ||
1015 | li r9, 0x100 /* reset vector always at 0x100 */ | |
1016 | ||
1017 | cmplw 0, r7, r8 | |
1018 | bgelr /* return if r7>=r8 - just in case */ | |
f046ccd1 EL |
1019 | 1: |
1020 | lwz r0, 0(r7) | |
1021 | stw r0, 0(r9) | |
1022 | addi r7, r7, 4 | |
1023 | addi r9, r9, 4 | |
1024 | cmplw 0, r7, r8 | |
1025 | bne 1b | |
1026 | ||
1027 | /* | |
1028 | * relocate `hdlr' and `int_return' entries | |
1029 | */ | |
1030 | li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET | |
1031 | li r8, Alignment - _start + EXC_OFF_SYS_RESET | |
1032 | 2: | |
1033 | bl trap_reloc | |
1034 | addi r7, r7, 0x100 /* next exception vector */ | |
1035 | cmplw 0, r7, r8 | |
1036 | blt 2b | |
1037 | ||
1038 | li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET | |
1039 | bl trap_reloc | |
1040 | ||
1041 | li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET | |
1042 | bl trap_reloc | |
1043 | ||
1044 | li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET | |
1045 | li r8, SystemCall - _start + EXC_OFF_SYS_RESET | |
1046 | 3: | |
1047 | bl trap_reloc | |
1048 | addi r7, r7, 0x100 /* next exception vector */ | |
1049 | cmplw 0, r7, r8 | |
1050 | blt 3b | |
1051 | ||
1052 | li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET | |
1053 | li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET | |
1054 | 4: | |
1055 | bl trap_reloc | |
1056 | addi r7, r7, 0x100 /* next exception vector */ | |
1057 | cmplw 0, r7, r8 | |
1058 | blt 4b | |
1059 | ||
1060 | mfmsr r3 /* now that the vectors have */ | |
1061 | lis r7, MSR_IP@h /* relocated into low memory */ | |
1062 | ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ | |
1063 | andc r3, r3, r7 /* (if it was on) */ | |
1064 | SYNC /* Some chip revs need this... */ | |
1065 | mtmsr r3 | |
1066 | SYNC | |
1067 | ||
1068 | mtlr r4 /* restore link register */ | |
1069 | blr | |
1070 | ||
06f60ae3 | 1071 | #endif /* !MINIMAL_SPL */ |
f046ccd1 | 1072 | |
6d0f6bcf | 1073 | #ifdef CONFIG_SYS_INIT_RAM_LOCK |
2688e2f9 KG |
1074 | lock_ram_in_cache: |
1075 | /* Allocate Initial RAM in data cache. | |
1076 | */ | |
6d0f6bcf JCPV |
1077 | lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h |
1078 | ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l | |
553f0982 | 1079 | li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ |
6d0f6bcf | 1080 | (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 |
ade50c7f | 1081 | mtctr r4 |
2688e2f9 KG |
1082 | 1: |
1083 | dcbz r0, r3 | |
1084 | addi r3, r3, 32 | |
1085 | bdnz 1b | |
1086 | ||
1087 | /* Lock the data cache */ | |
1088 | mfspr r0, HID0 | |
6eb2a44e | 1089 | ori r0, r0, HID0_DLOCK |
2688e2f9 KG |
1090 | sync |
1091 | mtspr HID0, r0 | |
1092 | sync | |
1093 | blr | |
1094 | ||
06f60ae3 | 1095 | #ifndef MINIMAL_SPL |
f046ccd1 EL |
1096 | .globl unlock_ram_in_cache |
1097 | unlock_ram_in_cache: | |
1098 | /* invalidate the INIT_RAM section */ | |
6d0f6bcf JCPV |
1099 | lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h |
1100 | ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l | |
553f0982 | 1101 | li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ |
6d0f6bcf | 1102 | (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 |
ade50c7f | 1103 | mtctr r4 |
f046ccd1 EL |
1104 | 1: icbi r0, r3 |
1105 | dcbi r0, r3 | |
1106 | addi r3, r3, 32 | |
1107 | bdnz 1b | |
1108 | sync /* Wait for all icbi to complete on bus */ | |
1109 | isync | |
2688e2f9 KG |
1110 | |
1111 | /* Unlock the data cache and invalidate it */ | |
1112 | mfspr r3, HID0 | |
1113 | li r5, HID0_DLOCK|HID0_DCFI | |
1114 | andc r3, r3, r5 /* no invalidate, unlock */ | |
1115 | ori r5, r3, HID0_DCFI /* invalidate, unlock */ | |
6eb2a44e | 1116 | sync |
2688e2f9 | 1117 | mtspr HID0, r5 /* invalidate, unlock */ |
2688e2f9 | 1118 | sync |
6eb2a44e | 1119 | mtspr HID0, r3 /* no invalidate, unlock */ |
f046ccd1 | 1120 | blr |
06f60ae3 | 1121 | #endif /* !MINIMAL_SPL */ |
6d0f6bcf | 1122 | #endif /* CONFIG_SYS_INIT_RAM_LOCK */ |
f046ccd1 | 1123 | |
6d0f6bcf | 1124 | #ifdef CONFIG_SYS_FLASHBOOT |
f046ccd1 EL |
1125 | map_flash_by_law1: |
1126 | /* When booting from ROM (Flash or EPROM), clear the */ | |
1127 | /* Address Mask in OR0 so ROM appears everywhere */ | |
1128 | /*----------------------------------------------------*/ | |
6d0f6bcf | 1129 | lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ |
de1d0a69 | 1130 | lwz r4, OR0@l(r3) |
f046ccd1 | 1131 | li r5, 0x7fff /* r5 <= 0x00007FFFF */ |
de1d0a69 | 1132 | and r4, r4, r5 |
f046ccd1 EL |
1133 | stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ |
1134 | ||
1135 | /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, | |
1136 | * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] | |
1137 | * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot | |
1138 | * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is | |
1139 | * 0xFF800. From the hard resetting to here, the processor fetched and | |
1140 | * executed the instructions one by one. There is not absolutely | |
1141 | * jumping happened. Laterly, the u-boot code has to do an absolutely | |
1142 | * jumping to tell the CPU instruction fetching component what the | |
1143 | * u-boot TEXT base address is. Because the TEXT base resides in the | |
1144 | * boot ROM memory space, to garantee the code can run smoothly after | |
1145 | * that jumping, we must map in the entire boot ROM by Local Access | |
1146 | * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting | |
1147 | * address for boot ROM, such as 0xFE000000. In this case, the default | |
1148 | * LBIU Local Access Widow 0 will not cover this memory space. So, we | |
1149 | * need another window to map in it. | |
1150 | */ | |
6d0f6bcf JCPV |
1151 | lis r4, (CONFIG_SYS_FLASH_BASE)@h |
1152 | ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l | |
1153 | stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ | |
31068b7c | 1154 | |
6d0f6bcf | 1155 | /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ |
31068b7c TT |
1156 | lis r4, (0x80000012)@h |
1157 | ori r4, r4, (0x80000012)@l | |
6d0f6bcf | 1158 | li r5, CONFIG_SYS_FLASH_SIZE |
31068b7c TT |
1159 | 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ |
1160 | addi r4, r4, 1 | |
1161 | bne 1b | |
1162 | ||
f046ccd1 | 1163 | stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ |
e45c98ad JT |
1164 | /* Wait for HW to catch up */ |
1165 | lwz r4, LBLAWAR1(r3) | |
1166 | twi 0,r4,0 | |
1167 | isync | |
f046ccd1 EL |
1168 | blr |
1169 | ||
1170 | /* Though all the LBIU Local Access Windows and LBC Banks will be | |
1171 | * initialized in the C code, we'd better configure boot ROM's | |
1172 | * window 0 and bank 0 correctly at here. | |
1173 | */ | |
1174 | remap_flash_by_law0: | |
1175 | /* Initialize the BR0 with the boot ROM starting address. */ | |
1176 | lwz r4, BR0(r3) | |
1177 | li r5, 0x7FFF | |
de1d0a69 | 1178 | and r4, r4, r5 |
6d0f6bcf JCPV |
1179 | lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h |
1180 | ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l | |
f046ccd1 | 1181 | or r5, r5, r4 |
6d0f6bcf | 1182 | stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ |
f046ccd1 EL |
1183 | |
1184 | lwz r4, OR0(r3) | |
6d0f6bcf | 1185 | lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) |
f046ccd1 | 1186 | or r4, r4, r5 |
31068b7c | 1187 | stw r4, OR0(r3) |
f046ccd1 | 1188 | |
6d0f6bcf JCPV |
1189 | lis r4, (CONFIG_SYS_FLASH_BASE)@h |
1190 | ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l | |
1191 | stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ | |
f046ccd1 | 1192 | |
6d0f6bcf | 1193 | /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ |
31068b7c TT |
1194 | lis r4, (0x80000012)@h |
1195 | ori r4, r4, (0x80000012)@l | |
6d0f6bcf | 1196 | li r5, CONFIG_SYS_FLASH_SIZE |
31068b7c TT |
1197 | 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ |
1198 | addi r4, r4, 1 | |
1199 | bne 1b | |
1200 | stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ | |
1201 | ||
f046ccd1 EL |
1202 | |
1203 | xor r4, r4, r4 | |
1204 | stw r4, LBLAWBAR1(r3) | |
1205 | stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ | |
e45c98ad JT |
1206 | /* Wait for HW to catch up */ |
1207 | lwz r4, LBLAWAR1(r3) | |
1208 | twi 0,r4,0 | |
1209 | isync | |
f046ccd1 | 1210 | blr |
6d0f6bcf | 1211 | #endif /* CONFIG_SYS_FLASHBOOT */ |