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[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc85xx / Makefile
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42d1f039 1#
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2# (C) Copyright 2006
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
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5# (C) Copyright 2002,2003 Motorola Inc.
6# Xianghua Xiao,X.Xiao@motorola.com
7#
1a459660 8# SPDX-License-Identifier: GPL-2.0+
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9#
10
11include $(TOPDIR)/config.mk
12
6d8962e8 13LIB = $(obj)lib$(CPU).o
42d1f039 14
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15MINIMAL=
16
17ifdef CONFIG_SPL_BUILD
18ifdef CONFIG_SPL_INIT_MINIMAL
19MINIMAL=y
20endif
21endif
22
23START = start.o resetvec.o
24
25ifdef MINIMAL
26
27COBJS-y += cpu_init_early.o tlb.o spl_minimal.o
28
29else
30
5052a771 31SOBJS-$(CONFIG_MP) += release.o
ec2b74ff 32SOBJS = $(SOBJS-y)
5052a771 33
79ee3448 34COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o
5052a771 35COBJS-$(CONFIG_CPM2) += commproc.o
58e5e9af 36
2a6c2d7a 37# supports ddr1
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38COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
39COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
40COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
41COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
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42
43# supports ddr1/2
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44COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
45COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
46COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
47
48# supports ddr1/2/3
49COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
50COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
22b6dbc1 51COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
b8cdd014 52COBJS-$(CONFIG_P1010) += ddr-gen3.o
a713ba92 53COBJS-$(CONFIG_P1011) += ddr-gen3.o
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54COBJS-$(CONFIG_P1012) += ddr-gen3.o
55COBJS-$(CONFIG_P1013) += ddr-gen3.o
b5debec5 56COBJS-$(CONFIG_P1014) += ddr-gen3.o
87c7661b 57COBJS-$(CONFIG_P1020) += ddr-gen3.o
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58COBJS-$(CONFIG_P1021) += ddr-gen3.o
59COBJS-$(CONFIG_P1022) += ddr-gen3.o
57072338 60COBJS-$(CONFIG_P1023) += ddr-gen3.o
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61COBJS-$(CONFIG_P1024) += ddr-gen3.o
62COBJS-$(CONFIG_P1025) += ddr-gen3.o
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63COBJS-$(CONFIG_P2010) += ddr-gen3.o
64COBJS-$(CONFIG_P2020) += ddr-gen3.o
1f97987a 65COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
c26de2d8 66COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
7e4259bb 67COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
19dbcc96 68COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
4905443f 69COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
9e758758 70COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o
b6240846 71COBJS-$(CONFIG_PPC_T4160) += ddr-gen3.o
e1dbdd81 72COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o
d2404141 73COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
19a8dbdc 74COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
35fe948e 75COBJS-$(CONFIG_BSC9132) += ddr-gen3.o
5f208d11 76COBJS-$(CONFIG_PPC_T1040) += ddr-gen3.o
58e5e9af 77
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78COBJS-$(CONFIG_CPM2) += ether_fcc.o
79COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
db977abf 80COBJS-$(CONFIG_FSL_CORENET) += liodn.o
5052a771 81COBJS-$(CONFIG_MP) += mp.o
5052a771 82COBJS-$(CONFIG_PCI) += pci.o
24995d82 83COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
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84
85# various SoC specific assignments
88b91f2d 86COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
d5d2cd43 87COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
db977abf 88COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
1eda59ff 89COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
4905443f 90COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
9e758758 91COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
b6240846 92COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o
e1dbdd81 93COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
d2404141 94COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
5f208d11 95COBJS-$(CONFIG_PPC_T1040) += t1040_ids.o
db977abf 96
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97COBJS-$(CONFIG_QE) += qe_io.o
98COBJS-$(CONFIG_CPM2) += serial_scc.o
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99COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
100COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
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101
102# SoC specific SERDES support
103COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
877a2611 104COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
bc48d0d5 105COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
5ba40eec 106COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
47567c26 107COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
af87cab6 108COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
28747f9b 109COBJS-$(CONFIG_P1010) += p1010_serdes.o
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110COBJS-$(CONFIG_P1011) += p1021_serdes.o
111COBJS-$(CONFIG_P1012) += p1021_serdes.o
04a641df 112COBJS-$(CONFIG_P1013) += p1022_serdes.o
28747f9b 113COBJS-$(CONFIG_P1014) += p1010_serdes.o
67a719da 114COBJS-$(CONFIG_P1017) += p1023_serdes.o
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115COBJS-$(CONFIG_P1020) += p1021_serdes.o
116COBJS-$(CONFIG_P1021) += p1021_serdes.o
c5780a6f 117COBJS-$(CONFIG_P1022) += p1022_serdes.o
67a719da 118COBJS-$(CONFIG_P1023) += p1023_serdes.o
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119COBJS-$(CONFIG_P1024) += p1021_serdes.o
120COBJS-$(CONFIG_P1025) += p1021_serdes.o
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121COBJS-$(CONFIG_P2010) += p2020_serdes.o
122COBJS-$(CONFIG_P2020) += p2020_serdes.o
1f97987a 123COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
d5d2cd43 124COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
34a8258f 125COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
1eda59ff 126COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
4905443f 127COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
9e758758 128COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
b6240846 129COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o
e1dbdd81 130COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
d2404141 131COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
35fe948e 132COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
5f208d11 133COBJS-$(CONFIG_PPC_T1040) += t1040_serdes.o
5052a771 134
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135COBJS-y += cpu.o
136COBJS-y += cpu_init.o
137COBJS-y += cpu_init_early.o
138COBJS-y += interrupts.o
139COBJS-y += speed.o
140COBJS-y += tlb.o
141COBJS-y += traps.o
42d1f039 142
25315683 143# Stub implementations of cache management functions for USB
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144COBJS-y += cache.o
145
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146endif # not minimal
147
a179eb0a 148COBJS = $(COBJS-y)
25315683 149
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150SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
151OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
152START := $(addprefix $(obj),$(START))
153
154all: $(obj).depend $(START) $(LIB)
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155
156$(LIB): $(OBJS)
6d8962e8 157 $(call cmd_link_o_target, $(OBJS))
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158
159#########################################################################
160
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161# defines $(obj).depend target
162include $(SRCTREE)/rules.mk
42d1f039 163
f9328639 164sinclude $(obj).depend
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165
166#########################################################################