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9f00409a | 1 | /* |
689f00fc | 2 | * Copyright 2009-2012 Freescale Semiconductor, Inc |
9f00409a KG |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <common.h> | |
21 | #include <asm/processor.h> | |
22 | #include <asm/mmu.h> | |
23 | #include <asm/fsl_law.h> | |
e8e6197a | 24 | #include <asm/io.h> |
9f00409a KG |
25 | |
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
74fa22ed | 28 | #ifdef CONFIG_A003399_NOR_WORKAROUND |
bc6bbd6b PA |
29 | void setup_ifc(void) |
30 | { | |
31 | struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; | |
32 | u32 _mas0, _mas1, _mas2, _mas3, _mas7; | |
33 | phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; | |
34 | ||
35 | /* | |
36 | * Adjust the TLB we were running out of to match the phys addr of the | |
37 | * chip select we are adjusting and will return to. | |
38 | */ | |
39 | flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; | |
40 | ||
41 | _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); | |
42 | _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | | |
43 | MAS1_TSIZE(BOOKE_PAGESZ_4M); | |
44 | _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); | |
45 | _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); | |
46 | _mas7 = FSL_BOOKE_MAS7(flash_phys); | |
47 | ||
48 | mtspr(MAS0, _mas0); | |
49 | mtspr(MAS1, _mas1); | |
50 | mtspr(MAS2, _mas2); | |
51 | mtspr(MAS3, _mas3); | |
52 | mtspr(MAS7, _mas7); | |
53 | ||
54 | asm volatile("isync;msync;tlbwe;isync"); | |
55 | ||
689f00fc PK |
56 | #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) |
57 | /* | |
58 | * TLB entry for debuggging in AS1 | |
59 | * Create temporary TLB entry in AS0 to handle debug exception | |
60 | * As on debug exception MSR is cleared i.e. Address space is changed | |
61 | * to 0. A TLB entry (in AS0) is required to handle debug exception generated | |
62 | * in AS1. | |
63 | * | |
64 | * TLB entry is created for IVPR + IVOR15 to map on valid OP code address | |
65 | * bacause flash's physical address is going to change as | |
66 | * CONFIG_SYS_FLASH_BASE_PHYS. | |
67 | */ | |
68 | _mas0 = MAS0_TLBSEL(1) | | |
69 | MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); | |
70 | _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | | |
71 | MAS1_TSIZE(BOOKE_PAGESZ_4M); | |
72 | _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); | |
73 | _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); | |
74 | _mas7 = FSL_BOOKE_MAS7(flash_phys); | |
75 | ||
76 | mtspr(MAS0, _mas0); | |
77 | mtspr(MAS1, _mas1); | |
78 | mtspr(MAS2, _mas2); | |
79 | mtspr(MAS3, _mas3); | |
80 | mtspr(MAS7, _mas7); | |
81 | ||
82 | asm volatile("isync;msync;tlbwe;isync"); | |
83 | #endif | |
84 | ||
85 | /* Change flash's physical address */ | |
bc6bbd6b PA |
86 | out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); |
87 | out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); | |
88 | out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); | |
89 | ||
90 | return ; | |
91 | } | |
92 | #endif | |
93 | ||
9f00409a KG |
94 | /* We run cpu_init_early_f in AS = 1 */ |
95 | void cpu_init_early_f(void) | |
96 | { | |
97 | u32 mas0, mas1, mas2, mas3, mas7; | |
98 | int i; | |
fb855f43 PA |
99 | #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
100 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
101 | #endif | |
74fa22ed | 102 | #ifdef CONFIG_A003399_NOR_WORKAROUND |
bc6bbd6b | 103 | ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; |
cfee584e | 104 | u32 *dst, *src; |
bc6bbd6b PA |
105 | void (*setup_ifc_sram)(void); |
106 | #endif | |
9f00409a KG |
107 | |
108 | /* Pointer is writable since we allocated a register for it */ | |
109 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); | |
110 | ||
111 | /* | |
112 | * Clear initial global data | |
113 | * we don't use memset so we can share this code with NAND_SPL | |
114 | */ | |
115 | for (i = 0; i < sizeof(gd_t); i++) | |
116 | ((char *)gd)[i] = 0; | |
117 | ||
e8e6197a PA |
118 | mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); |
119 | mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); | |
9f00409a KG |
120 | mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); |
121 | mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); | |
122 | mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); | |
123 | ||
124 | write_tlb(mas0, mas1, mas2, mas3, mas7); | |
125 | ||
fb855f43 PA |
126 | /* |
127 | * Work Around for IFC Erratum A-003549. This issue is P1010 | |
128 | * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC | |
129 | * Hence specifically selecting CS3. | |
130 | */ | |
131 | #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 | |
132 | setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); | |
133 | #endif | |
134 | ||
9f00409a | 135 | init_laws(); |
bc6bbd6b PA |
136 | |
137 | /* | |
138 | * Work Around for IFC Erratum A003399, issue will hit only when execution | |
139 | * from NOR Flash | |
140 | */ | |
74fa22ed | 141 | #ifdef CONFIG_A003399_NOR_WORKAROUND |
bc6bbd6b PA |
142 | #define SRAM_BASE_ADDR (0x00000000) |
143 | /* TLB for SRAM */ | |
144 | mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); | |
145 | mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | | |
146 | MAS1_TSIZE(BOOKE_PAGESZ_1M); | |
147 | mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); | |
148 | mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR); | |
149 | mas7 = FSL_BOOKE_MAS7(0); | |
150 | ||
151 | write_tlb(mas0, mas1, mas2, mas3, mas7); | |
152 | ||
153 | out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); | |
154 | ||
155 | out_be32(&l2cache->l2errdis, | |
156 | (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); | |
157 | ||
158 | out_be32(&l2cache->l2ctl, | |
159 | (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); | |
160 | ||
161 | /* | |
162 | * Copy the code in setup_ifc to L2SRAM. Do a word copy | |
163 | * because NOR Flash on P1010 does not support byte | |
164 | * access (Erratum IFC-A002769) | |
165 | */ | |
166 | setup_ifc_sram = (void *)SRAM_BASE_ADDR; | |
167 | dst = (u32 *) SRAM_BASE_ADDR; | |
168 | src = (u32 *) setup_ifc; | |
169 | for (i = 0; i < 1024; i++) | |
cfee584e | 170 | *dst++ = *src++; |
bc6bbd6b PA |
171 | |
172 | setup_ifc_sram(); | |
173 | ||
174 | /* CLEANUP */ | |
175 | clrbits_be32(&l2cache->l2ctl, | |
176 | (MPC85xx_L2CTL_L2E | | |
177 | MPC85xx_L2CTL_L2SRAM_ENTIRE)); | |
178 | out_be32(&l2cache->l2srbar0, 0x0); | |
179 | #endif | |
180 | ||
e8e6197a | 181 | invalidate_tlb(1); |
7065b7d4 | 182 | |
9f00409a KG |
183 | init_tlbs(); |
184 | } |