[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / mpc8544_serdes.c

/*
 * Copyright 2010 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>

#define SRDS1_MAX_LANES		8
#define SRDS2_MAX_LANES		4

static u32 serdes1_prtcl_map, serdes2_prtcl_map;

static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
	[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
	[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
	[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
	[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
	[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
	[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
};

static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
	[0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
	[0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
	[0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
	[0x6] = {PCIE3, NONE, NONE, NONE},
	[0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
};

int is_serdes_configured(enum srds_prtcl device)
{
	int ret;

	if (!(serdes1_prtcl_map & (1 << NONE)))
		fsl_serdes_init();

	ret = (1 << device) & serdes1_prtcl_map;

	if (ret)
		return ret;

	if (!(serdes2_prtcl_map & (1 << NONE)))
		fsl_serdes_init();

	return (1 << device) & serdes2_prtcl_map;
}

void fsl_serdes_init(void)
{
	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
	int lane;

	if (serdes1_prtcl_map & (1 << NONE) &&
	    serdes2_prtcl_map & (1 << NONE))
		return;

	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);

	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
		return;
	}
	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
		serdes1_prtcl_map |= (1 << lane_prtcl);
	}

	/* Set the first bit to indicate serdes has been initialized */
	serdes1_prtcl_map |= (1 << NONE);

	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
		return;
	}

	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
		enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
		serdes2_prtcl_map |= (1 << lane_prtcl);
	}

	if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
		serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);

	if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
		serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);

	/* Set the first bit to indicate serdes has been initialized */
	serdes2_prtcl_map |= (1 << NONE);
}
Commit	Line	Data
877a2611 KG	1	/*
	2	* Copyright 2010 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
877a2611 KG	5	*/
	6
	7	#include <config.h>
	8	#include <common.h>
	9	#include <asm/io.h>
	10	#include <asm/immap_85xx.h>
	11	#include <asm/fsl_serdes.h>
	12
	13	#define SRDS1_MAX_LANES 8
	14	#define SRDS2_MAX_LANES 4
	15
	16	static u32 serdes1_prtcl_map, serdes2_prtcl_map;
	17
	18	static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
	19	[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
	20	[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
	21	[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
	22	[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
	23	[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
	24	[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
	25	};
	26
	27	static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
	28	[0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
	29	[0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
	30	[0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
	31	[0x6] = {PCIE3, NONE, NONE, NONE},
	32	[0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
	33	};
	34
	35	int is_serdes_configured(enum srds_prtcl device)
	36	{
71fe2225 HZ	37	int ret;
	38
	39	if (!(serdes1_prtcl_map & (1 << NONE)))
	40	fsl_serdes_init();
	41
	42	ret = (1 << device) & serdes1_prtcl_map;
877a2611 KG	43
	44	if (ret)
	45	return ret;
	46
71fe2225 HZ	47	if (!(serdes2_prtcl_map & (1 << NONE)))
	48	fsl_serdes_init();
	49
877a2611 KG	50	return (1 << device) & serdes2_prtcl_map;
	51	}
	52
	53	void fsl_serdes_init(void)
	54	{
	55	ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	56	u32 pordevsr = in_be32(&gur->pordevsr);
	57	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
	58	MPC85xx_PORDEVSR_IO_SEL_SHIFT;
	59	int lane;
	60
71fe2225 HZ	61	if (serdes1_prtcl_map & (1 << NONE) &&
	62	serdes2_prtcl_map & (1 << NONE))
	63	return;
	64
877a2611 KG	65	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
877a2611 KG	66
e51e47d3	67	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
877a2611 KG	68	printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
	69	return;
	70	}
	71	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
	72	enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
	73	serdes1_prtcl_map \|= (1 << lane_prtcl);
	74	}
	75
71fe2225 HZ	76	/* Set the first bit to indicate serdes has been initialized */
	77	serdes1_prtcl_map \|= (1 << NONE);
	78
e51e47d3	79	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
877a2611 KG	80	printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
	81	return;
	82	}
	83
	84	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
	85	enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
	86	serdes2_prtcl_map \|= (1 << lane_prtcl);
	87	}
	88
	89	if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
	90	serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
	91
	92	if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
	93	serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
71fe2225 HZ	94
	95	/* Set the first bit to indicate serdes has been initialized */
	96	serdes2_prtcl_map \|= (1 << NONE);
877a2611	97	}