[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / p1010_serdes.c

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>

#define SRDS1_MAX_LANES		4
#define SRDS2_MAX_LANES		2

static u32 serdes1_prtcl_map, serdes2_prtcl_map;

static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
	[0x00] = {NONE, NONE, NONE, NONE},
	[0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
	[0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
	[0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
};

static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
	[0x00] = {NONE, NONE},
	[0x01] = {SATA1, SATA2},
	[0x02] = {SATA1, SATA2},
	[0x03] = {PCIE1, PCIE2},
};


int is_serdes_configured(enum srds_prtcl device)
{
	int ret = (1 << device) & serdes1_prtcl_map;

	if (ret)
		return ret;

	return (1 << device) & serdes2_prtcl_map;
}

void fsl_serdes_init(void)
{
	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
	int lane;

	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);

	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
		return;
	}
	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
		enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
		serdes1_prtcl_map |= (1 << lane_prtcl);
	}

	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
		return;
	}

	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
		enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
		serdes2_prtcl_map |= (1 << lane_prtcl);
	}
}
Commit	Line	Data
28747f9b PK	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
28747f9b PK	6	*/
	7
	8	#include <config.h>
	9	#include <common.h>
	10	#include <asm/io.h>
	11	#include <asm/immap_85xx.h>
	12	#include <asm/fsl_serdes.h>
	13
	14	#define SRDS1_MAX_LANES 4
	15	#define SRDS2_MAX_LANES 2
	16
	17	static u32 serdes1_prtcl_map, serdes2_prtcl_map;
	18
	19	static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
	20	[0x00] = {NONE, NONE, NONE, NONE},
	21	[0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
	22	[0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
	23	[0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
	24	};
	25
	26	static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
	27	[0x00] = {NONE, NONE},
	28	[0x01] = {SATA1, SATA2},
	29	[0x02] = {SATA1, SATA2},
	30	[0x03] = {PCIE1, PCIE2},
	31	};
	32
	33
	34	int is_serdes_configured(enum srds_prtcl device)
	35	{
	36	int ret = (1 << device) & serdes1_prtcl_map;
	37
	38	if (ret)
	39	return ret;
	40
	41	return (1 << device) & serdes2_prtcl_map;
	42	}
	43
	44	void fsl_serdes_init(void)
	45	{
	46	ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	47	u32 pordevsr = in_be32(&gur->pordevsr);
	48	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
	49	MPC85xx_PORDEVSR_IO_SEL_SHIFT;
	50	int lane;
	51
	52	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
	53
e51e47d3	54	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
28747f9b PK	55	printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
	56	return;
	57	}
	58	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
	59	enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
	60	serdes1_prtcl_map \|= (1 << lane_prtcl);
	61	}
	62
e51e47d3	63	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
28747f9b PK	64	printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
	65	return;
	66	}
	67
	68	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
	69	enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
	70	serdes2_prtcl_map \|= (1 << lane_prtcl);
	71	}
	72	}