[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / release.S

/*
 * Copyright 2008-2012 Freescale Semiconductor, Inc.
 * Kumar Gala <kumar.gala@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

/* To boot secondary cpus, we need a place for them to start up.
 * Normally, they start at 0xfffffffc, but that's usually the
 * firmware, and we don't want to have to run the firmware again.
 * Instead, the primary cpu will set the BPTR to point here to
 * this page.  We then set up the core, and head to
 * start_secondary.  Note that this means that the code below
 * must never exceed 1023 instructions (the branch at the end
 * would then be the 1024th).
 */
	.globl	__secondary_start_page
	.align	12
__secondary_start_page:
/* First do some preliminary setup */
	lis	r3, HID0_EMCP@h		/* enable machine check */
#ifndef CONFIG_E500MC
	ori	r3,r3,HID0_TBEN@l	/* enable Timebase */
#endif
#ifdef CONFIG_PHYS_64BIT
	ori	r3,r3,HID0_ENMAS7@l	/* enable MAS7 updates */
#endif
	mtspr	SPRN_HID0,r3

#ifndef CONFIG_E500MC
	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
	mfspr   r0,PVR
	andi.	r0,r0,0xff
	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
	blt 1f
	/* Set MBDD bit also */
	ori r3, r3, HID1_MBDD@l
1:
	mtspr	SPRN_HID1,r3
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
	mfspr	r3,SPRN_HDBCR1
	oris	r3,r3,0x0100
	mtspr	SPRN_HDBCR1,r3
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
	mfspr	r3,SPRN_SVR
	rlwinm	r3,r3,0,0xff
	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
	cmpw	r3,r4
	beq	1f

#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
	li	r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
	cmpw	r3,r4
	beq	1f
#endif

	/* Not a supported revision affected by erratum */
	b	2f

1:	/* Erratum says set bits 55:60 to 001001 */
	msync
	isync
	mfspr	r3,SPRN_HDBCR0
	li	r4,0x48
	rlwimi	r3,r4,0,0x1f8
	mtspr	SPRN_HDBCR0,r3
	isync
2:
#endif

	/* Enable branch prediction */
	lis	r3,BUCSR_ENABLE@h
	ori	r3,r3,BUCSR_ENABLE@l
	mtspr	SPRN_BUCSR,r3

	/* Ensure TB is 0 */
	li	r3,0
	mttbl	r3
	mttbu	r3

	/* Enable/invalidate the I-Cache */
	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
	mtspr	SPRN_L1CSR1,r2
1:
	mfspr	r3,SPRN_L1CSR1
	and.	r1,r3,r2
	bne	1b

	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
	mtspr	SPRN_L1CSR1,r3
	isync
2:
	mfspr	r3,SPRN_L1CSR1
	andi.	r1,r3,L1CSR1_ICE@l
	beq	2b

	/* Enable/invalidate the D-Cache */
	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
	mtspr	SPRN_L1CSR0,r2
1:
	mfspr	r3,SPRN_L1CSR0
	and.	r1,r3,r2
	bne	1b

	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
	mtspr	SPRN_L1CSR0,r3
	isync
2:
	mfspr	r3,SPRN_L1CSR0
	andi.	r1,r3,L1CSR0_DCE@l
	beq	2b

#define toreset(x) (x - __secondary_start_page + 0xfffff000)

	/* get our PIR to figure out our table entry */
	lis	r3,toreset(__spin_table_addr)@h
	ori	r3,r3,toreset(__spin_table_addr)@l
	lwz	r3,0(r3)

	mfspr	r0,SPRN_PIR
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
 * PIR definition for Chassis 2
 * 0-17 Reserved (logic 0s)
 * 18-19 CHIP_ID,    2'b00      - SoC 1
 *                  all others - reserved
 * 20-24 CLUSTER_ID 5'b00000   - CCM 1
 *                  all others - reserved
 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
 *                       2'b01 - cluster 2
 *                       2'b10 - cluster 3
 *                       2'b11 - cluster 4
 * 27-28 CORE_ID         2'b00 - core 0
 *                       2'b01 - core 1
 *                       2'b10 - core 2
 *                       2'b11 - core 3
 * 29-31 THREAD_ID       3'b000 - thread 0
 *                       3'b001 - thread 1
 *
 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
 * and clusters by 0x20.
 *
 * We renumber PIR so that all threads in the system are consecutive.
 */

	rlwinm	r8,r0,29,0x03	/* r8 = core within cluster */
	srwi	r10,r0,5	/* r10 = cluster */

	mulli	r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
	add	r5,r5,r8	/* for spin table index */
	mulli	r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE	/* for PIR */
#elif	defined(CONFIG_E500MC)
	rlwinm	r4,r0,27,27,31
	mr	r5,r4
#else
	mr	r4,r0
	mr	r5,r4
#endif

	/*
	 * r10 has the base address for the entry.
	 * we cannot access it yet before setting up a new TLB
	 */
	slwi	r8,r5,6	/* spin table is padded to 64 byte */
	add	r10,r3,r8

	mtspr	SPRN_PIR,r4	/* write to PIR register */

#ifdef CONFIG_SYS_CACHE_STASHING
	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
	slwi	r8,r4,1
	addi	r8,r8,32
	mtspr	L1CSR2,r8
#endif

#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
	/*
	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
	 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
	 */
	mfspr   r3,SPRN_SVR
	rlwinm	r6,r3,24,~0x800		/* clear E bit */

	lis	r5,SVR_P4080@h
	ori	r5,r5,SVR_P4080@l
	cmpw	r6,r5
	bne	1f

	rlwinm  r3,r3,0,0xf0
	li      r5,0x30
	cmpw    r3,r5
	bge     2f
1:
#ifdef	CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
	lis	r3,toreset(enable_cpu_a011_workaround)@ha
	lwz	r3,toreset(enable_cpu_a011_workaround)@l(r3)
	cmpwi	r3,0
	beq	2f
#endif
	mfspr	r3,L1CSR2
	oris	r3,r3,(L1CSR2_DCWS)@h
	mtspr	L1CSR2,r3
2:
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
	/*
	 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
	 * write shadow mode. This code should run after other code setting
	 * DCWS.
	 */
	mfspr	r3,L1CSR2
	andis.	r3,r3,(L1CSR2_DCWS)@h
	beq	1f
	mfspr	r3, SPRN_HDBCR0
	oris	r3, r3, 0x8000
	mtspr	SPRN_HDBCR0, r3
1:
#endif

#ifdef CONFIG_BACKSIDE_L2_CACHE
	/* skip L2 setup on P2040/P2040E as they have no L2 */
	mfspr	r3,SPRN_SVR
	rlwinm	r6,r3,24,~0x800		/* clear E bit of SVR */

	lis	r3,SVR_P2040@h
	ori	r3,r3,SVR_P2040@l
	cmpw	r6,r3
	beq 3f

	/* Enable/invalidate the L2 cache */
	msync
	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
	mtspr	SPRN_L2CSR0,r2
1:
	mfspr	r3,SPRN_L2CSR0
	and.	r1,r3,r2
	bne	1b

#ifdef CONFIG_SYS_CACHE_STASHING
	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	addi	r3,r8,1
	mtspr	SPRN_L2CSR1,r3
#endif

	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
	mtspr	SPRN_L2CSR0,r3
	isync
2:
	mfspr	r3,SPRN_L2CSR0
	andis.	r1,r3,L2CSR0_L2E@h
	beq	2b
#endif
3:
	/* setup mapping for the spin table, WIMGE=0b00100 */
	lis	r13,toreset(__spin_table_addr)@h
	ori	r13,r13,toreset(__spin_table_addr)@l
	lwz	r13,0(r13)
	/* mask by 4K */
	rlwinm	r13,r13,0,0,19

	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
	mtspr	SPRN_MAS0,r11
	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
	mtspr	SPRN_MAS1,r11
	oris	r11,r13,(MAS2_M|MAS2_G)@h
	ori	r11,r13,(MAS2_M|MAS2_G)@l
	mtspr	SPRN_MAS2,r11
	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
	mtspr	SPRN_MAS3,r11
	li	r11,0
	mtspr	SPRN_MAS7,r11
	tlbwe

	/*
	 * __bootpg_addr has the address of __second_half_boot_page
	 * jump there in AS=1 space with cache enabled
	 */
	lis	r13,toreset(__bootpg_addr)@h
	ori	r13,r13,toreset(__bootpg_addr)@l
	lwz	r11,0(r13)
	mtspr	SPRN_SRR0,r11
	mfmsr	r13
	ori	r12,r13,MSR_IS|MSR_DS@l
	mtspr	SPRN_SRR1,r12
	rfi

	/*
	 * Allocate some space for the SDRAM address of the bootpg.
	 * This variable has to be in the boot page so that it can
	 * be accessed by secondary cores when they come out of reset.
	 */
	.align L1_CACHE_SHIFT
	.globl __bootpg_addr
__bootpg_addr:
	.long	0

	.global __spin_table_addr
__spin_table_addr:
	.long	0

	/*
	 * This variable is set by cpu_init_r() after parsing hwconfig
	 * to enable workaround for erratum NMG_CPU_A011.
	 */
	.align L1_CACHE_SHIFT
	.global enable_cpu_a011_workaround
enable_cpu_a011_workaround:
	.long	1

	/* Fill in the empty space.  The actual reset vector is
	 * the last word of the page */
__secondary_start_code_end:
	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
__secondary_reset_vector:
	b	__secondary_start_page


/* this is a separated page for the spin table and cacheable boot code */
	.align L1_CACHE_SHIFT
	.global __second_half_boot_page
__second_half_boot_page:
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
	lis	r3,(spin_table_compat - __second_half_boot_page)@h
	ori	r3,r3,(spin_table_compat - __second_half_boot_page)@l
	add	r3,r3,r11 /* r11 has the address of __second_half_boot_page */
	lwz	r14,0(r3)
#endif

#define ENTRY_ADDR_UPPER	0
#define ENTRY_ADDR_LOWER	4
#define ENTRY_R3_UPPER		8
#define ENTRY_R3_LOWER		12
#define ENTRY_RESV		16
#define ENTRY_PIR		20
#define ENTRY_SIZE		64
	/*
	 * setup the entry
	 * r10 has the base address of the spin table.
	 * spin table is defined as
	 * struct {
	 *	uint64_t entry_addr;
	 *	uint64_t r3;
	 *	uint32_t rsvd1;
	 *	uint32_t pir;
	 * };
	 * we pad this struct to 64 bytes so each entry is in its own cacheline
	 */
	li	r3,0
	li	r8,1
	mfspr	r4,SPRN_PIR
	stw	r3,ENTRY_ADDR_UPPER(r10)
	stw	r3,ENTRY_R3_UPPER(r10)
	stw	r4,ENTRY_R3_LOWER(r10)
	stw	r3,ENTRY_RESV(r10)
	stw	r4,ENTRY_PIR(r10)
	msync
	stw	r8,ENTRY_ADDR_LOWER(r10)

	/* spin waiting for addr */
3:
/*
 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
 * memory. Old OS may not work with this change. A patch is waiting to be
 * accepted for Linux kernel. Other OS needs similar fix to spin table.
 * For OSes with old spin table code, we can enable this temporary fix by
 * setting environmental variable "spin_table_compat". For new OSes, set
 * "spin_table_compat=no". After Linux is fixed, we can remove this macro
 * and related code. For now, it is enabled by default.
 */
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
	cmpwi   r14,0
	beq     4f
	dcbf    0, r10
	sync
4:
#endif
	lwz	r4,ENTRY_ADDR_LOWER(r10)
	andi.	r11,r4,1
	bne	3b
	isync

	/* get the upper bits of the addr */
	lwz	r11,ENTRY_ADDR_UPPER(r10)

	/* setup branch addr */
	mtspr	SPRN_SRR0,r4

	/* mark the entry as released */
	li	r8,3
	stw	r8,ENTRY_ADDR_LOWER(r10)

	/* mask by ~64M to setup our tlb we will jump to */
	rlwinm	r12,r4,0,0,5

	/*
	 * setup r3, r4, r5, r6, r7, r8, r9
	 * r3 contains the value to put in the r3 register at secondary cpu
	 * entry. The high 32-bits are ignored on 32-bit chip implementations.
	 * 64-bit chip implementations however shall load all 64-bits
	 */
#ifdef CONFIG_SYS_PPC64
	ld	r3,ENTRY_R3_UPPER(r10)
#else
	lwz	r3,ENTRY_R3_LOWER(r10)
#endif
	li	r4,0
	li	r5,0
	li	r6,0
	lis	r7,(64*1024*1024)@h
	li	r8,0
	li	r9,0

	/* load up the pir */
	lwz	r0,ENTRY_PIR(r10)
	mtspr	SPRN_PIR,r0
	mfspr	r0,SPRN_PIR
	stw	r0,ENTRY_PIR(r10)

	mtspr	IVPR,r12
/*
 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
 * which maps 0xfffff000-0xffffffff one-to-one.  We set up a
 * second mapping that maps addr 1:1 for 64M, and then we jump to
 * addr
 */
	lis	r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
	mtspr	SPRN_MAS0,r10
	lis	r10,(MAS1_VALID|MAS1_IPROT)@h
	ori	r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
	mtspr	SPRN_MAS1,r10
	/* WIMGE = 0b00000 for now */
	mtspr	SPRN_MAS2,r12
	ori	r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
	mtspr	SPRN_MAS3,r12
#ifdef CONFIG_ENABLE_36BIT_PHYS
	mtspr	SPRN_MAS7,r11
#endif
	tlbwe

/* Now we have another mapping for this page, so we jump to that
 * mapping
 */
	mtspr	SPRN_SRR1,r13
	rfi


	.align 6
	.globl __spin_table
__spin_table:
	.space CONFIG_MAX_CPUS*ENTRY_SIZE

#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
	.align L1_CACHE_SHIFT
	.global spin_table_compat
spin_table_compat:
	.long	1

#endif

__spin_table_end:
	.space 4096 - (__spin_table_end - __spin_table)
Commit	Line	Data
0e870980	1	/*
709389b6	2	* Copyright 2008-2012 Freescale Semiconductor, Inc.
0e870980 PA	3	* Kumar Gala <kumar.gala@freescale.com>
0e870980 PA	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
0e870980 PA	6	*/
0e870980 PA	7
25ddd1fb	8	#include <asm-offsets.h>
ec2b74ff KG	9	#include <config.h>
ec2b74ff KG	10	#include <mpc85xx.h>
ec2b74ff	11
ec2b74ff KG	12	#include <ppc_asm.tmpl>
	13	#include <ppc_defs.h>
	14
	15	#include <asm/cache.h>
	16	#include <asm/mmu.h>
	17
	18	/* To boot secondary cpus, we need a place for them to start up.
	19	* Normally, they start at 0xfffffffc, but that's usually the
	20	* firmware, and we don't want to have to run the firmware again.
	21	* Instead, the primary cpu will set the BPTR to point here to
	22	* this page. We then set up the core, and head to
	23	* start_secondary. Note that this means that the code below
	24	* must never exceed 1023 instructions (the branch at the end
	25	* would then be the 1024th).
	26	*/
	27	.globl __secondary_start_page
	28	.align 12
	29	__secondary_start_page:
	30	/* First do some preliminary setup */
	31	lis r3, HID0_EMCP@h /* enable machine check */
0f060c3b	32	#ifndef CONFIG_E500MC
ec2b74ff	33	ori r3,r3,HID0_TBEN@l /* enable Timebase */
0f060c3b	34	#endif
ec2b74ff KG	35	#ifdef CONFIG_PHYS_64BIT
	36	ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
	37	#endif
	38	mtspr SPRN_HID0,r3
	39
0f060c3b	40	#ifndef CONFIG_E500MC
ec2b74ff	41	li r3,(HID1_ASTME\|HID1_ABE)@l /* Addr streaming & broadcast */
ff8473e9 SG	42	mfspr r0,PVR
	43	andi. r0,r0,0xff
	44	cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
	45	blt 1f
	46	/* Set MBDD bit also */
	47	ori r3, r3, HID1_MBDD@l
	48	1:
ec2b74ff	49	mtspr SPRN_HID1,r3
0f060c3b	50	#endif
ec2b74ff	51
43f082bb	52	#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
cd7ad629	53	mfspr r3,SPRN_HDBCR1
43f082bb	54	oris r3,r3,0x0100
cd7ad629	55	mtspr SPRN_HDBCR1,r3
43f082bb KG	56	#endif
43f082bb KG	57
33eee330 SW	58	#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
	59	mfspr r3,SPRN_SVR
	60	rlwinm r3,r3,0,0xff
	61	li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
	62	cmpw r3,r4
	63	beq 1f
	64
	65	#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
	66	li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
	67	cmpw r3,r4
	68	beq 1f
	69	#endif
	70
	71	/* Not a supported revision affected by erratum */
	72	b 2f
	73
	74	1: /* Erratum says set bits 55:60 to 001001 */
	75	msync
	76	isync
cd7ad629	77	mfspr r3,SPRN_HDBCR0
33eee330 SW	78	li r4,0x48
33eee330 SW	79	rlwimi r3,r4,0,0x1f8
cd7ad629	80	mtspr SPRN_HDBCR0,r3
33eee330 SW	81	isync
	82	2:
	83	#endif
	84
ec2b74ff	85	/* Enable branch prediction */
69bcf5bc KG	86	lis r3,BUCSR_ENABLE@h
69bcf5bc KG	87	ori r3,r3,BUCSR_ENABLE@l
ec2b74ff KG	88	mtspr SPRN_BUCSR,r3
ec2b74ff KG	89
e0ff3d35 KG	90	/* Ensure TB is 0 */
	91	li r3,0
	92	mttbl r3
	93	mttbu r3
	94
ec2b74ff	95	/* Enable/invalidate the I-Cache */
33f57bd5 KG	96	lis r2,(L1CSR1_ICFI\|L1CSR1_ICLFR)@h
	97	ori r2,r2,(L1CSR1_ICFI\|L1CSR1_ICLFR)@l
	98	mtspr SPRN_L1CSR1,r2
	99	1:
	100	mfspr r3,SPRN_L1CSR1
	101	and. r1,r3,r2
	102	bne 1b
	103
	104	lis r3,(L1CSR1_CPE\|L1CSR1_ICE)@h
	105	ori r3,r3,(L1CSR1_CPE\|L1CSR1_ICE)@l
	106	mtspr SPRN_L1CSR1,r3
ec2b74ff	107	isync
33f57bd5 KG	108	2:
	109	mfspr r3,SPRN_L1CSR1
	110	andi. r1,r3,L1CSR1_ICE@l
	111	beq 2b
ec2b74ff KG	112
ec2b74ff KG	113	/* Enable/invalidate the D-Cache */
33f57bd5 KG	114	lis r2,(L1CSR0_DCFI\|L1CSR0_DCLFR)@h
	115	ori r2,r2,(L1CSR0_DCFI\|L1CSR0_DCLFR)@l
	116	mtspr SPRN_L1CSR0,r2
	117	1:
	118	mfspr r3,SPRN_L1CSR0
	119	and. r1,r3,r2
	120	bne 1b
	121
	122	lis r3,(L1CSR0_CPE\|L1CSR0_DCE)@h
	123	ori r3,r3,(L1CSR0_CPE\|L1CSR0_DCE)@l
	124	mtspr SPRN_L1CSR0,r3
ec2b74ff	125	isync
33f57bd5 KG	126	2:
	127	mfspr r3,SPRN_L1CSR0
	128	andi. r1,r3,L1CSR0_DCE@l
	129	beq 2b
ec2b74ff KG	130
	131	#define toreset(x) (x - __secondary_start_page + 0xfffff000)
	132
	133	/* get our PIR to figure out our table entry */
ffd06e02 YS	134	lis r3,toreset(__spin_table_addr)@h
	135	ori r3,r3,toreset(__spin_table_addr)@l
	136	lwz r3,0(r3)
ec2b74ff	137
ec2b74ff	138	mfspr r0,SPRN_PIR
615f0cba	139	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
709389b6	140	/*
615f0cba	141	* PIR definition for Chassis 2
709389b6	142	* 0-17 Reserved (logic 0s)
f6981439	143	* 18-19 CHIP_ID, 2'b00 - SoC 1
709389b6	144	* all others - reserved
0c7e65f3	145	* 20-24 CLUSTER_ID 5'b00000 - CCM 1
709389b6	146	* all others - reserved
0c7e65f3 TT	147	* 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
	148	* 2'b01 - cluster 2
	149	* 2'b10 - cluster 3
	150	* 2'b11 - cluster 4
	151	* 27-28 CORE_ID 2'b00 - core 0
	152	* 2'b01 - core 1
	153	* 2'b10 - core 2
	154	* 2'b11 - core 3
	155	* 29-31 THREAD_ID 3'b000 - thread 0
	156	* 3'b001 - thread 1
f6981439 YS	157	*
	158	* Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
	159	* and clusters by 0x20.
	160	*
	161	* We renumber PIR so that all threads in the system are consecutive.
709389b6	162	*/
f6981439 YS	163
	164	rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
	165	srwi r10,r0,5 /* r10 = cluster */
	166
	167	mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
	168	add r5,r5,r8 /* for spin table index */
	169	mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */
709389b6	170	#elif defined(CONFIG_E500MC)
0f060c3b	171	rlwinm r4,r0,27,27,31
f6981439	172	mr r5,r4
0f060c3b	173	#else
ec2b74ff	174	mr r4,r0
f6981439	175	mr r5,r4
0f060c3b	176	#endif
79679d80	177
709389b6	178	/*
f6981439 YS	179	* r10 has the base address for the entry.
f6981439 YS	180	* we cannot access it yet before setting up a new TLB
709389b6	181	*/
f6981439 YS	182	slwi r8,r5,6 /* spin table is padded to 64 byte */
f6981439 YS	183	add r10,r3,r8
709389b6 YS	184
	185	mtspr SPRN_PIR,r4 /* write to PIR register */
	186
6d2b9da1 YS	187	#ifdef CONFIG_SYS_CACHE_STASHING
	188	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
	189	slwi r8,r4,1
	190	addi r8,r8,32
	191	mtspr L1CSR2,r8
	192	#endif
	193
5e23ab0a YS	194	#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) \|\| \
	195	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
	196	/*
	197	* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
	198	* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
	199	* also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
	200	*/
1e9ea85f	201	mfspr r3,SPRN_SVR
5e23ab0a YS	202	rlwinm r6,r3,24,~0x800 /* clear E bit */
	203
	204	lis r5,SVR_P4080@h
	205	ori r5,r5,SVR_P4080@l
	206	cmpw r6,r5
	207	bne 1f
	208
1e9ea85f	209	rlwinm r3,r3,0,0xf0
5e23ab0a YS	210	li r5,0x30
5e23ab0a YS	211	cmpw r3,r5
1e9ea85f	212	bge 2f
5e23ab0a	213	1:
57125f22 YS	214	#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
	215	lis r3,toreset(enable_cpu_a011_workaround)@ha
	216	lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
	217	cmpwi r3,0
	218	beq 2f
	219	#endif
5e23ab0a YS	220	mfspr r3,L1CSR2
	221	oris r3,r3,(L1CSR2_DCWS)@h
	222	mtspr L1CSR2,r3
1e9ea85f	223	2:
fd3c9bef KG	224	#endif
fd3c9bef KG	225
d217a9ad YS	226	#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
	227	/*
	228	* A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
	229	* write shadow mode. This code should run after other code setting
	230	* DCWS.
	231	*/
	232	mfspr r3,L1CSR2
	233	andis. r3,r3,(L1CSR2_DCWS)@h
	234	beq 1f
	235	mfspr r3, SPRN_HDBCR0
	236	oris r3, r3, 0x8000
	237	mtspr SPRN_HDBCR0, r3
	238	1:
	239	#endif
	240
1b3e4044	241	#ifdef CONFIG_BACKSIDE_L2_CACHE
acf3f8da	242	/* skip L2 setup on P2040/P2040E as they have no L2 */
feae3424 YS	243	mfspr r3,SPRN_SVR
	244	rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
	245
acf3f8da KG	246	lis r3,SVR_P2040@h
acf3f8da KG	247	ori r3,r3,SVR_P2040@l
feae3424	248	cmpw r6,r3
acf3f8da KG	249	beq 3f
acf3f8da KG	250
1b3e4044 KG	251	/* Enable/invalidate the L2 cache */
1b3e4044 KG	252	msync
ff882295 DL	253	lis r2,(L2CSR0_L2FI\|L2CSR0_L2LFC)@h
	254	ori r2,r2,(L2CSR0_L2FI\|L2CSR0_L2LFC)@l
	255	mtspr SPRN_L2CSR0,r2
1b3e4044 KG	256	1:
1b3e4044 KG	257	mfspr r3,SPRN_L2CSR0
ff882295	258	and. r1,r3,r2
1b3e4044 KG	259	bne 1b
1b3e4044 KG	260
82fd1f8d KG	261	#ifdef CONFIG_SYS_CACHE_STASHING
	262	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	263	addi r3,r8,1
	264	mtspr SPRN_L2CSR1,r3
	265	#endif
	266
1b3e4044 KG	267	lis r3,CONFIG_SYS_INIT_L2CSR0@h
	268	ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
	269	mtspr SPRN_L2CSR0,r3
	270	isync
ff882295 DL	271	2:
	272	mfspr r3,SPRN_L2CSR0
	273	andis. r1,r3,L2CSR0_L2E@h
	274	beq 2b
1b3e4044	275	#endif
acf3f8da	276	3:
ffd06e02 YS	277	/* setup mapping for the spin table, WIMGE=0b00100 */
	278	lis r13,toreset(__spin_table_addr)@h
	279	ori r13,r13,toreset(__spin_table_addr)@l
5ccd29c3	280	lwz r13,0(r13)
ffd06e02 YS	281	/* mask by 4K */
ffd06e02 YS	282	rlwinm r13,r13,0,0,19
5ccd29c3	283
79679d80 KG	284	lis r11,(MAS0_TLBSEL(1)\|MAS0_ESEL(1))@h
	285	mtspr SPRN_MAS0,r11
	286	lis r11,(MAS1_VALID\|MAS1_IPROT)@h
	287	ori r11,r11,(MAS1_TS\|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
	288	mtspr SPRN_MAS1,r11
ffd06e02 YS	289	oris r11,r13,(MAS2_M\|MAS2_G)@h
ffd06e02 YS	290	ori r11,r13,(MAS2_M\|MAS2_G)@l
79679d80	291	mtspr SPRN_MAS2,r11
5ccd29c3 PT	292	oris r11,r13,(MAS3_SX\|MAS3_SW\|MAS3_SR)@h
5ccd29c3 PT	293	ori r11,r13,(MAS3_SX\|MAS3_SW\|MAS3_SR)@l
79679d80	294	mtspr SPRN_MAS3,r11
ffd06e02 YS	295	li r11,0
ffd06e02 YS	296	mtspr SPRN_MAS7,r11
79679d80 KG	297	tlbwe
79679d80 KG	298
5ccd29c3	299	/*
ffd06e02 YS	300	* __bootpg_addr has the address of __second_half_boot_page
ffd06e02 YS	301	* jump there in AS=1 space with cache enabled
5ccd29c3	302	*/
ffd06e02 YS	303	lis r13,toreset(__bootpg_addr)@h
	304	ori r13,r13,toreset(__bootpg_addr)@l
	305	lwz r11,0(r13)
	306	mtspr SPRN_SRR0,r11
79679d80 KG	307	mfmsr r13
79679d80 KG	308	ori r12,r13,MSR_IS\|MSR_DS@l
79679d80 KG	309	mtspr SPRN_SRR1,r12
79679d80 KG	310	rfi
ec2b74ff	311
ffd06e02 YS	312	/*
	313	* Allocate some space for the SDRAM address of the bootpg.
	314	* This variable has to be in the boot page so that it can
	315	* be accessed by secondary cores when they come out of reset.
	316	*/
	317	.align L1_CACHE_SHIFT
	318	.globl __bootpg_addr
	319	__bootpg_addr:
	320	.long 0
	321
	322	.global __spin_table_addr
	323	__spin_table_addr:
	324	.long 0
	325
	326	/*
	327	* This variable is set by cpu_init_r() after parsing hwconfig
	328	* to enable workaround for erratum NMG_CPU_A011.
	329	*/
	330	.align L1_CACHE_SHIFT
	331	.global enable_cpu_a011_workaround
	332	enable_cpu_a011_workaround:
	333	.long 1
	334
	335	/* Fill in the empty space. The actual reset vector is
	336	* the last word of the page */
	337	__secondary_start_code_end:
	338	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
	339	__secondary_reset_vector:
	340	b __secondary_start_page
	341
	342
	343	/* this is a separated page for the spin table and cacheable boot code */
	344	.align L1_CACHE_SHIFT
	345	.global __second_half_boot_page
	346	__second_half_boot_page:
2a5fcb83 YS	347	#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
	348	lis r3,(spin_table_compat - __second_half_boot_page)@h
	349	ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
	350	add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
	351	lwz r14,0(r3)
	352	#endif
	353
ffd06e02 YS	354	#define ENTRY_ADDR_UPPER 0
	355	#define ENTRY_ADDR_LOWER 4
	356	#define ENTRY_R3_UPPER 8
	357	#define ENTRY_R3_LOWER 12
	358	#define ENTRY_RESV 16
	359	#define ENTRY_PIR 20
	360	#define ENTRY_SIZE 64
	361	/*
	362	* setup the entry
	363	* r10 has the base address of the spin table.
	364	* spin table is defined as
	365	* struct {
	366	* uint64_t entry_addr;
	367	* uint64_t r3;
	368	* uint32_t rsvd1;
	369	* uint32_t pir;
	370	* };
	371	* we pad this struct to 64 bytes so each entry is in its own cacheline
	372	*/
	373	li r3,0
	374	li r8,1
	375	mfspr r4,SPRN_PIR
	376	stw r3,ENTRY_ADDR_UPPER(r10)
	377	stw r3,ENTRY_R3_UPPER(r10)
	378	stw r4,ENTRY_R3_LOWER(r10)
	379	stw r3,ENTRY_RESV(r10)
	380	stw r4,ENTRY_PIR(r10)
	381	msync
	382	stw r8,ENTRY_ADDR_LOWER(r10)
	383
ec2b74ff	384	/* spin waiting for addr */
2a5fcb83 YS	385	3:
	386	/*
	387	* To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
	388	* memory. Old OS may not work with this change. A patch is waiting to be
	389	* accepted for Linux kernel. Other OS needs similar fix to spin table.
	390	* For OSes with old spin table code, we can enable this temporary fix by
	391	* setting environmental variable "spin_table_compat". For new OSes, set
	392	* "spin_table_compat=no". After Linux is fixed, we can remove this macro
	393	* and related code. For now, it is enabled by default.
	394	*/
	395	#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
	396	cmpwi r14,0
	397	beq 4f
	398	dcbf 0, r10
	399	sync
	400	4:
	401	#endif
	402	lwz r4,ENTRY_ADDR_LOWER(r10)
ec2b74ff	403	andi. r11,r4,1
ffd06e02	404	bne 3b
cf6cc014	405	isync
79679d80 KG	406
	407	/* get the upper bits of the addr */
	408	lwz r11,ENTRY_ADDR_UPPER(r10)
ec2b74ff KG	409
ec2b74ff KG	410	/* setup branch addr */
79679d80	411	mtspr SPRN_SRR0,r4
ec2b74ff KG	412
	413	/* mark the entry as released */
	414	li r8,3
79679d80	415	stw r8,ENTRY_ADDR_LOWER(r10)
ec2b74ff KG	416
ec2b74ff KG	417	/* mask by ~64M to setup our tlb we will jump to */
79679d80	418	rlwinm r12,r4,0,0,5
ec2b74ff	419
ffd06e02 YS	420	/*
	421	* setup r3, r4, r5, r6, r7, r8, r9
	422	* r3 contains the value to put in the r3 register at secondary cpu
	423	* entry. The high 32-bits are ignored on 32-bit chip implementations.
	424	* 64-bit chip implementations however shall load all 64-bits
	425	*/
	426	#ifdef CONFIG_SYS_PPC64
	427	ld r3,ENTRY_R3_UPPER(r10)
	428	#else
79679d80	429	lwz r3,ENTRY_R3_LOWER(r10)
ffd06e02	430	#endif
79679d80	431	li r4,0
ec2b74ff	432	li r5,0
3f0997b3	433	li r6,0
79679d80 KG	434	lis r7,(6410241024)@h
	435	li r8,0
	436	li r9,0
ec2b74ff KG	437
ec2b74ff KG	438	/* load up the pir */
79679d80	439	lwz r0,ENTRY_PIR(r10)
ec2b74ff KG	440	mtspr SPRN_PIR,r0
ec2b74ff KG	441	mfspr r0,SPRN_PIR
79679d80	442	stw r0,ENTRY_PIR(r10)
ec2b74ff	443
181a3650	444	mtspr IVPR,r12
ec2b74ff KG	445	/*
	446	* Coming here, we know the cpu has one TLB mapping in TLB1[0]
	447	* which maps 0xfffff000-0xffffffff one-to-one. We set up a
	448	* second mapping that maps addr 1:1 for 64M, and then we jump to
	449	* addr
	450	*/
79679d80 KG	451	lis r10,(MAS0_TLBSEL(1)\|MAS0_ESEL(0))@h
	452	mtspr SPRN_MAS0,r10
	453	lis r10,(MAS1_VALID\|MAS1_IPROT)@h
	454	ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
	455	mtspr SPRN_MAS1,r10
ec2b74ff	456	/* WIMGE = 0b00000 for now */
79679d80 KG	457	mtspr SPRN_MAS2,r12
	458	ori r12,r12,(MAS3_SX\|MAS3_SW\|MAS3_SR)
	459	mtspr SPRN_MAS3,r12
	460	#ifdef CONFIG_ENABLE_36BIT_PHYS
	461	mtspr SPRN_MAS7,r11
	462	#endif
ec2b74ff KG	463	tlbwe
	464
	465	/* Now we have another mapping for this page, so we jump to that
	466	* mapping
	467	*/
79679d80 KG	468	mtspr SPRN_SRR1,r13
79679d80 KG	469	rfi
ec2b74ff	470
5ccd29c3	471
ffd06e02	472	.align 6
ec2b74ff KG	473	.globl __spin_table
ec2b74ff KG	474	__spin_table:
0e870980	475	.space CONFIG_MAX_CPUS*ENTRY_SIZE
2a5fcb83 YS	476
	477	#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
	478	.align L1_CACHE_SHIFT
	479	.global spin_table_compat
	480	spin_table_compat:
	481	.long 1
	482
	483	#endif
	484
ffd06e02 YS	485	__spin_table_end:
ffd06e02 YS	486	.space 4096 - (__spin_table_end - __spin_table)