[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

/*
 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* --------------------------------------------------------------- */

void get_sys_info (sys_info_t * sysInfo)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
	unsigned int cpu;

	const u8 core_cplx_PLL[16] = {
		[ 0] = 0,	/* CC1 PPL / 1 */
		[ 1] = 0,	/* CC1 PPL / 2 */
		[ 2] = 0,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 1,	/* CC2 PPL / 2 */
		[ 6] = 1,	/* CC2 PPL / 4 */
		[ 8] = 2,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_PLL_div[16] = {
		[ 0] = 1,	/* CC1 PPL / 1 */
		[ 1] = 2,	/* CC1 PPL / 2 */
		[ 2] = 4,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 2,	/* CC2 PPL / 2 */
		[ 6] = 4,	/* CC2 PPL / 4 */
		[ 8] = 1,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};
	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
	uint ratio[4];
	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
	uint mem_pll_rat;

	sysInfo->freqSystemBus = sysclk;
	sysInfo->freqDDRBus = sysclk;

	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
	if (mem_pll_rat > 2)
		sysInfo->freqDDRBus *= mem_pll_rat;
	else
		sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;

	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
	for (i = 0; i < 4; i++) {
		if (ratio[i] > 4)
			freqCC_PLL[i] = sysclk * ratio[i];
		else
			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
	}
	rcw_tmp = in_be32(&gur->rcwsr[3]);
	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];

		sysInfo->freqProcessor[cpu] =
			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	}

#define PME_CLK_SEL	0x80000000
#define FM1_CLK_SEL	0x40000000
#define FM2_CLK_SEL	0x20000000
#define HWA_ASYNC_DIV	0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL	1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL	2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	if (rcw_tmp & PME_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
	}
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	if (rcw_tmp & FM1_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
	if (rcw_tmp & FM2_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
	}
#endif
#endif

#else
	uint plat_ratio,e500_ratio,half_freqSystemBus;
#if defined(CONFIG_FSL_LBC)
	uint lcrr_div;
#endif
	int i;
#ifdef CONFIG_QE
	__maybe_unused u32 qe_ratio;
#endif

	plat_ratio = (gur->porpllsr) & 0x0000003e;
	plat_ratio >>= 1;
	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;

	/* Divide before multiply to avoid integer
	 * overflow for processor speeds above 2GHz */
	half_freqSystemBus = sysInfo->freqSystemBus/2;
	for (i = 0; i < cpu_numcores(); i++) {
		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
		sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
	}

	/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
	sysInfo->freqDDRBus = sysInfo->freqSystemBus;

#ifdef CONFIG_DDR_CLK_FREQ
	{
		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
		if (ddr_ratio != 0x7)
			sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	}
#endif

#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
	sysInfo->freqQE =  sysInfo->freqSystemBus;
#else
	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
#endif

#endif /* CONFIG_FSL_CORENET */

#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
	/* We will program LCRR to this value later */
	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
		/* If this is corenet based SoC, bit-representation
		 * for four times the clock divider values.
		 */
		lcrr_div *= 4;
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		lcrr_div *= 2;
#endif
		sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
	} else {
		/* In case anyone cares what the unknown value is */
		sysInfo->freqLocalBus = lcrr_div;
	}
#endif
}


int get_clocks (void)
{
	sys_info_t sys_info;
#ifdef CONFIG_MPC8544
	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint sccr, dfbrg;

	/* set VCO = 4 * BRG */
	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
	sccr = cpm->im_cpm_intctl.sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freqProcessor[0];
	gd->bus_clk = sys_info.freqSystemBus;
	gd->mem_clk = sys_info.freqDDRBus;
	gd->lbc_clk = sys_info.freqLocalBus;

#ifdef CONFIG_QE
	gd->qe_clk = sys_info.freqQE;
	gd->brg_clk = gd->qe_clk / 2;
#endif
	/*
	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
	 * there is no pattern that can be used to determine the frequency, so
	 * the only choice is to look up the actual SOC number and use the value
	 * for that SOC. This information is taken from application note
	 * AN2919.
	 */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
	gd->i2c1_clk = sys_info.freqSystemBus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->i2c1_clk = sys_info.freqSystemBus / 3;
	else
		gd->i2c1_clk = sys_info.freqSystemBus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->i2c1_clk = sys_info.freqSystemBus / 2;
#endif
	gd->i2c2_clk = gd->i2c1_clk;

#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
       defined(CONFIG_P1014)
	gd->sdhc_clk = gd->bus_clk;
#else
	gd->sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2)
	gd->vco_out = 2*sys_info.freqSystemBus;
	gd->cpm_clk = gd->vco_out / 2;
	gd->scc_clk = gd->vco_out / 4;
	gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
#endif

	if(gd->cpu_clk != 0) return (0);
	else return (1);
}


/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq (ulong dummy)
{
	return gd->mem_clk;
}
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Xianghua Xiao, (X.Xiao@motorola.com)
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <ppc_asm.tmpl>
a52d2f81	31	#include <linux/compiler.h>
42d1f039	32	#include <asm/processor.h>
ada591d2	33	#include <asm/io.h>
42d1f039	34
d87080b7 WD	35	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	36
42d1f039 WD	37	/* --------------------------------------------------------------- */
42d1f039 WD	38
42d1f039 WD	39	void get_sys_info (sys_info_t * sysInfo)
42d1f039 WD	40	{
6d0f6bcf	41	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
39aaca1f KG	42	#ifdef CONFIG_FSL_CORENET
39aaca1f KG	43	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7	44	unsigned int cpu;
39aaca1f KG	45
	46	const u8 core_cplx_PLL[16] = {
	47	[ 0] = 0, /* CC1 PPL / 1 */
	48	[ 1] = 0, /* CC1 PPL / 2 */
	49	[ 2] = 0, /* CC1 PPL / 4 */
	50	[ 4] = 1, /* CC2 PPL / 1 */
	51	[ 5] = 1, /* CC2 PPL / 2 */
	52	[ 6] = 1, /* CC2 PPL / 4 */
	53	[ 8] = 2, /* CC3 PPL / 1 */
	54	[ 9] = 2, /* CC3 PPL / 2 */
	55	[10] = 2, /* CC3 PPL / 4 */
	56	[12] = 3, /* CC4 PPL / 1 */
	57	[13] = 3, /* CC4 PPL / 2 */
	58	[14] = 3, /* CC4 PPL / 4 */
	59	};
	60
	61	const u8 core_cplx_PLL_div[16] = {
	62	[ 0] = 1, /* CC1 PPL / 1 */
	63	[ 1] = 2, /* CC1 PPL / 2 */
	64	[ 2] = 4, /* CC1 PPL / 4 */
	65	[ 4] = 1, /* CC2 PPL / 1 */
	66	[ 5] = 2, /* CC2 PPL / 2 */
	67	[ 6] = 4, /* CC2 PPL / 4 */
	68	[ 8] = 1, /* CC3 PPL / 1 */
	69	[ 9] = 2, /* CC3 PPL / 2 */
	70	[10] = 4, /* CC3 PPL / 4 */
	71	[12] = 1, /* CC4 PPL / 1 */
	72	[13] = 2, /* CC4 PPL / 2 */
	73	[14] = 4, /* CC4 PPL / 4 */
	74	};
	75	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
ab48ca1a	76	uint ratio[4];
39aaca1f	77	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a	78	uint mem_pll_rat;
39aaca1f KG	79
	80	sysInfo->freqSystemBus = sysclk;
	81	sysInfo->freqDDRBus = sysclk;
39aaca1f	82
93cedc71	83	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ab48ca1a SS	84	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
	85	if (mem_pll_rat > 2)
	86	sysInfo->freqDDRBus *= mem_pll_rat;
	87	else
	88	sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
39aaca1f	89
ab48ca1a SS	90	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
	91	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
	92	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
	93	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
	94	for (i = 0; i < 4; i++) {
	95	if (ratio[i] > 4)
	96	freqCC_PLL[i] = sysclk * ratio[i];
	97	else
	98	freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
	99	}
39aaca1f	100	rcw_tmp = in_be32(&gur->rcwsr[3]);
fbb9ecf7 TT	101	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
fbb9ecf7 TT	102	u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
39aaca1f KG	103	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
39aaca1f KG	104
fbb9ecf7	105	sysInfo->freqProcessor[cpu] =
39aaca1f KG	106	freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	107	}
	108
	109	#define PME_CLK_SEL 0x80000000
	110	#define FM1_CLK_SEL 0x40000000
	111	#define FM2_CLK_SEL 0x20000000
b5c8753f KG	112	#define HWA_ASYNC_DIV 0x04000000
	113	#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
	114	#define HWA_CC_PLL 1
	115	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5	116	#define HWA_CC_PLL 2
b5c8753f KG	117	#else
	118	#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
	119	#endif
39aaca1f KG	120	rcw_tmp = in_be32(&gur->rcwsr[7]);
	121
	122	#ifdef CONFIG_SYS_DPAA_PME
b5c8753f KG	123	if (rcw_tmp & PME_CLK_SEL) {
	124	if (rcw_tmp & HWA_ASYNC_DIV)
	125	sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
	126	else
	127	sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
	128	} else {
693416fe	129	sysInfo->freqPME = sysInfo->freqSystemBus / 2;
b5c8753f	130	}
39aaca1f KG	131	#endif
	132
	133	#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f KG	134	if (rcw_tmp & FM1_CLK_SEL) {
	135	if (rcw_tmp & HWA_ASYNC_DIV)
	136	sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
	137	else
	138	sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
	139	} else {
693416fe	140	sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
b5c8753f	141	}
39aaca1f	142	#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f KG	143	if (rcw_tmp & FM2_CLK_SEL) {
	144	if (rcw_tmp & HWA_ASYNC_DIV)
	145	sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
	146	else
	147	sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
	148	} else {
693416fe	149	sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
b5c8753f	150	}
39aaca1f KG	151	#endif
	152	#endif
	153
	154	#else
66ed6cca	155	uint plat_ratio,e500_ratio,half_freqSystemBus;
beba93ed	156	#if defined(CONFIG_FSL_LBC)
ada591d2	157	uint lcrr_div;
beba93ed	158	#endif
2fc7eb0c	159	int i;
b3d7f20f	160	#ifdef CONFIG_QE
a52d2f81	161	__maybe_unused u32 qe_ratio;
b3d7f20f	162	#endif
42d1f039 WD	163
	164	plat_ratio = (gur->porpllsr) & 0x0000003e;
	165	plat_ratio >>= 1;
66ed6cca	166	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca AF	167
	168	/* Divide before multiply to avoid integer
	169	* overflow for processor speeds above 2GHz */
	170	half_freqSystemBus = sysInfo->freqSystemBus/2;
0e870980	171	for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c HW	172	e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
	173	sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
	174	}
a3e77fa5 JY	175
a3e77fa5 JY	176	/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
d4357932 KG	177	sysInfo->freqDDRBus = sysInfo->freqSystemBus;
	178
	179	#ifdef CONFIG_DDR_CLK_FREQ
	180	{
c0391111 JJ	181	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	182	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932 KG	183	if (ddr_ratio != 0x7)
	184	sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	185	}
	186	#endif
ada591d2	187
b3d7f20f	188	#ifdef CONFIG_QE
be7bebea	189	#if defined(CONFIG_P1012) \|\| defined(CONFIG_P1021) \|\| defined(CONFIG_P1025)
a52d2f81 HW	190	sysInfo->freqQE = sysInfo->freqSystemBus;
a52d2f81 HW	191	#else
b3d7f20f HW	192	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
	193	>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	194	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
	195	#endif
a52d2f81	196	#endif
b3d7f20f	197
24995d82	198	#ifdef CONFIG_SYS_DPAA_FMAN
939cdcdc	199	sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
24995d82 HW	200	#endif
	201
	202	#endif /* CONFIG_FSL_CORENET */
	203
beba93ed	204	#if defined(CONFIG_FSL_LBC)
ada591d2 TP	205	#if defined(CONFIG_SYS_LBC_LCRR)
	206	/* We will program LCRR to this value later */
	207	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
	208	#else
f51cdaf1	209	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2 TP	210	#endif
ada591d2 TP	211	if (lcrr_div == 2 \|\| lcrr_div == 4 \|\| lcrr_div == 8) {
0fd2fa6c DL	212	#if defined(CONFIG_FSL_CORENET)
	213	/* If this is corenet based SoC, bit-representation
	214	* for four times the clock divider values.
	215	*/
	216	lcrr_div *= 4;
	217	#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
ada591d2 TP	218	!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
	219	/*
	220	* Yes, the entire PQ38 family use the same
	221	* bit-representation for twice the clock divider values.
	222	*/
	223	lcrr_div *= 2;
	224	#endif
	225	sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
	226	} else {
	227	/* In case anyone cares what the unknown value is */
	228	sysInfo->freqLocalBus = lcrr_div;
	229	}
beba93ed	230	#endif
42d1f039 WD	231	}
42d1f039 WD	232
66ed6cca	233
42d1f039 WD	234	int get_clocks (void)
42d1f039 WD	235	{
42d1f039	236	sys_info_t sys_info;
88353a98	237	#ifdef CONFIG_MPC8544
6d0f6bcf	238	volatile ccsr_gur_t gur = (void ) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98	239	#endif
9c4c5ae3	240	#if defined(CONFIG_CPM2)
6d0f6bcf	241	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	242	uint sccr, dfbrg;
	243
	244	/* set VCO = 4 * BRG */
aafeefbd KG	245	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
aafeefbd KG	246	sccr = cpm->im_cpm_intctl.sccr;
42d1f039 WD	247	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	248	#endif
	249	get_sys_info (&sys_info);
2fc7eb0c	250	gd->cpu_clk = sys_info.freqProcessor[0];
42d1f039	251	gd->bus_clk = sys_info.freqSystemBus;
a3e77fa5	252	gd->mem_clk = sys_info.freqDDRBus;
ada591d2	253	gd->lbc_clk = sys_info.freqLocalBus;
88353a98	254
b3d7f20f HW	255	#ifdef CONFIG_QE
	256	gd->qe_clk = sys_info.freqQE;
	257	gd->brg_clk = gd->qe_clk / 2;
	258	#endif
88353a98 TT	259	/*
	260	* The base clock for I2C depends on the actual SOC. Unfortunately,
	261	* there is no pattern that can be used to determine the frequency, so
	262	* the only choice is to look up the actual SOC number and use the value
	263	* for that SOC. This information is taken from application note
	264	* AN2919.
	265	*/
	266	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
	267	defined(CONFIG_MPC8560) \|\| defined(CONFIG_MPC8555)
943afa22	268	gd->i2c1_clk = sys_info.freqSystemBus;
88353a98 TT	269	#elif defined(CONFIG_MPC8544)
	270	/*
	271	* On the 8544, the I2C clock is the same as the SEC clock. This can be
	272	* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	273	* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
	274	* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	275	* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	276	*/
	277	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
dffd2446	278	gd->i2c1_clk = sys_info.freqSystemBus / 3;
42653b82 KG	279	else
42653b82 KG	280	gd->i2c1_clk = sys_info.freqSystemBus / 2;
88353a98 TT	281	#else
	282	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	283	gd->i2c1_clk = sys_info.freqSystemBus / 2;
	284	#endif
	285	gd->i2c2_clk = gd->i2c1_clk;
943afa22	286
6b9ea08c	287	#if defined(CONFIG_FSL_ESDHC)
7d640e9b PJ	288	#if defined(CONFIG_MPC8569) \|\| defined(CONFIG_P1010) \|\|\
7d640e9b PJ	289	defined(CONFIG_P1014)
7f52ed5e AV	290	gd->sdhc_clk = gd->bus_clk;
7f52ed5e AV	291	#else
ef50d6c0 KG	292	gd->sdhc_clk = gd->bus_clk / 2;
ef50d6c0 KG	293	#endif
7f52ed5e	294	#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0	295
9c4c5ae3	296	#if defined(CONFIG_CPM2)
42d1f039 WD	297	gd->vco_out = 2*sys_info.freqSystemBus;
	298	gd->cpm_clk = gd->vco_out / 2;
	299	gd->scc_clk = gd->vco_out / 4;
	300	gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
	301	#endif
	302
	303	if(gd->cpu_clk != 0) return (0);
	304	else return (1);
	305	}
	306
	307
	308	/********************************************
	309	* get_bus_freq
	310	* return system bus freq in Hz
	311	*********************************************/
	312	ulong get_bus_freq (ulong dummy)
	313	{
a3e77fa5	314	return gd->bus_clk;
42d1f039	315	}
d4357932 KG	316
	317	/********************************************
	318	* get_ddr_freq
	319	* return ddr bus freq in Hz
	320	*********************************************/
	321	ulong get_ddr_freq (ulong dummy)
	322	{
a3e77fa5	323	return gd->mem_clk;
d4357932	324	}