[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

/*
 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* --------------------------------------------------------------- */

void get_sys_info (sys_info_t * sysInfo)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
	u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
	unsigned int cpu;

	const u8 core_cplx_PLL[16] = {
		[ 0] = 0,	/* CC1 PPL / 1 */
		[ 1] = 0,	/* CC1 PPL / 2 */
		[ 2] = 0,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 1,	/* CC2 PPL / 2 */
		[ 6] = 1,	/* CC2 PPL / 4 */
		[ 8] = 2,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_PLL_div[16] = {
		[ 0] = 1,	/* CC1 PPL / 1 */
		[ 1] = 2,	/* CC1 PPL / 2 */
		[ 2] = 4,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 2,	/* CC2 PPL / 2 */
		[ 6] = 4,	/* CC2 PPL / 4 */
		[ 8] = 1,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};
	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
	uint ratio[4];
	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
	uint mem_pll_rat;

	sysInfo->freqSystemBus = sysclk;
	sysInfo->freqDDRBus = sysclk;

	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
	if (mem_pll_rat > 2)
		sysInfo->freqDDRBus *= mem_pll_rat;
	else
		sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;

	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
	for (i = 0; i < 4; i++) {
		if (ratio[i] > 4)
			freqCC_PLL[i] = sysclk * ratio[i];
		else
			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
	}
	rcw_tmp = in_be32(&gur->rcwsr[3]);
	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];

		sysInfo->freqProcessor[cpu] =
			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	}

#define PME_CLK_SEL	0x80000000
#define FM1_CLK_SEL	0x40000000
#define FM2_CLK_SEL	0x20000000
#define HWA_ASYNC_DIV	0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL	1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
#define HWA_CC_PLL	2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL	2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	if (rcw_tmp & PME_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
	}
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	if (rcw_tmp & FM1_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
	if (rcw_tmp & FM2_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
	}
#endif
#endif

#else
	uint plat_ratio,e500_ratio,half_freqSystemBus;
#if defined(CONFIG_FSL_LBC)
	uint lcrr_div;
#endif
	int i;
#ifdef CONFIG_QE
	__maybe_unused u32 qe_ratio;
#endif

	plat_ratio = (gur->porpllsr) & 0x0000003e;
	plat_ratio >>= 1;
	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;

	/* Divide before multiply to avoid integer
	 * overflow for processor speeds above 2GHz */
	half_freqSystemBus = sysInfo->freqSystemBus/2;
	for (i = 0; i < cpu_numcores(); i++) {
		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
		sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
	}

	/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
	sysInfo->freqDDRBus = sysInfo->freqSystemBus;

#ifdef CONFIG_DDR_CLK_FREQ
	{
		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
		if (ddr_ratio != 0x7)
			sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	}
#endif

#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
	sysInfo->freqQE =  sysInfo->freqSystemBus;
#else
	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
#endif

#endif /* CONFIG_FSL_CORENET */

#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
	/* We will program LCRR to this value later */
	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
		/* If this is corenet based SoC, bit-representation
		 * for four times the clock divider values.
		 */
		lcrr_div *= 4;
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		lcrr_div *= 2;
#endif
		sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
	} else {
		/* In case anyone cares what the unknown value is */
		sysInfo->freqLocalBus = lcrr_div;
	}
#endif

#if defined(CONFIG_FSL_IFC)
	ccr = in_be32(&ifc_regs->ifc_ccr);
	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;

	sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
#endif
}


int get_clocks (void)
{
	sys_info_t sys_info;
#ifdef CONFIG_MPC8544
	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint sccr, dfbrg;

	/* set VCO = 4 * BRG */
	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
	sccr = cpm->im_cpm_intctl.sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freqProcessor[0];
	gd->bus_clk = sys_info.freqSystemBus;
	gd->mem_clk = sys_info.freqDDRBus;
	gd->lbc_clk = sys_info.freqLocalBus;

#ifdef CONFIG_QE
	gd->qe_clk = sys_info.freqQE;
	gd->brg_clk = gd->qe_clk / 2;
#endif
	/*
	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
	 * there is no pattern that can be used to determine the frequency, so
	 * the only choice is to look up the actual SOC number and use the value
	 * for that SOC. This information is taken from application note
	 * AN2919.
	 */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
	gd->i2c1_clk = sys_info.freqSystemBus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->i2c1_clk = sys_info.freqSystemBus / 3;
	else
		gd->i2c1_clk = sys_info.freqSystemBus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->i2c1_clk = sys_info.freqSystemBus / 2;
#endif
	gd->i2c2_clk = gd->i2c1_clk;

#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
       defined(CONFIG_P1014)
	gd->sdhc_clk = gd->bus_clk;
#else
	gd->sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2)
	gd->vco_out = 2*sys_info.freqSystemBus;
	gd->cpm_clk = gd->vco_out / 2;
	gd->scc_clk = gd->vco_out / 4;
	gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
#endif

	if(gd->cpu_clk != 0) return (0);
	else return (1);
}


/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq (ulong dummy)
{
	return gd->mem_clk;
}
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Xianghua Xiao, (X.Xiao@motorola.com)
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <ppc_asm.tmpl>
a52d2f81	31	#include <linux/compiler.h>
42d1f039	32	#include <asm/processor.h>
ada591d2	33	#include <asm/io.h>
42d1f039	34
d87080b7 WD	35	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	36
42d1f039 WD	37	/* --------------------------------------------------------------- */
42d1f039 WD	38
42d1f039 WD	39	void get_sys_info (sys_info_t * sysInfo)
42d1f039 WD	40	{
6d0f6bcf	41	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
800c73c4 KG	42	#ifdef CONFIG_FSL_IFC
	43	struct fsl_ifc ifc_regs = (void )CONFIG_SYS_IFC_ADDR;
	44	u32 ccr;
	45	#endif
39aaca1f KG	46	#ifdef CONFIG_FSL_CORENET
39aaca1f KG	47	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7	48	unsigned int cpu;
39aaca1f KG	49
	50	const u8 core_cplx_PLL[16] = {
	51	[ 0] = 0, /* CC1 PPL / 1 */
	52	[ 1] = 0, /* CC1 PPL / 2 */
	53	[ 2] = 0, /* CC1 PPL / 4 */
	54	[ 4] = 1, /* CC2 PPL / 1 */
	55	[ 5] = 1, /* CC2 PPL / 2 */
	56	[ 6] = 1, /* CC2 PPL / 4 */
	57	[ 8] = 2, /* CC3 PPL / 1 */
	58	[ 9] = 2, /* CC3 PPL / 2 */
	59	[10] = 2, /* CC3 PPL / 4 */
	60	[12] = 3, /* CC4 PPL / 1 */
	61	[13] = 3, /* CC4 PPL / 2 */
	62	[14] = 3, /* CC4 PPL / 4 */
	63	};
	64
	65	const u8 core_cplx_PLL_div[16] = {
	66	[ 0] = 1, /* CC1 PPL / 1 */
	67	[ 1] = 2, /* CC1 PPL / 2 */
	68	[ 2] = 4, /* CC1 PPL / 4 */
	69	[ 4] = 1, /* CC2 PPL / 1 */
	70	[ 5] = 2, /* CC2 PPL / 2 */
	71	[ 6] = 4, /* CC2 PPL / 4 */
	72	[ 8] = 1, /* CC3 PPL / 1 */
	73	[ 9] = 2, /* CC3 PPL / 2 */
	74	[10] = 4, /* CC3 PPL / 4 */
	75	[12] = 1, /* CC4 PPL / 1 */
	76	[13] = 2, /* CC4 PPL / 2 */
	77	[14] = 4, /* CC4 PPL / 4 */
	78	};
	79	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
ab48ca1a	80	uint ratio[4];
39aaca1f	81	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a	82	uint mem_pll_rat;
39aaca1f KG	83
	84	sysInfo->freqSystemBus = sysclk;
	85	sysInfo->freqDDRBus = sysclk;
39aaca1f	86
93cedc71	87	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ab48ca1a SS	88	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
	89	if (mem_pll_rat > 2)
	90	sysInfo->freqDDRBus *= mem_pll_rat;
	91	else
	92	sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
39aaca1f	93
ab48ca1a SS	94	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
	95	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
	96	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
	97	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
	98	for (i = 0; i < 4; i++) {
	99	if (ratio[i] > 4)
	100	freqCC_PLL[i] = sysclk * ratio[i];
	101	else
	102	freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
	103	}
39aaca1f	104	rcw_tmp = in_be32(&gur->rcwsr[3]);
fbb9ecf7 TT	105	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
fbb9ecf7 TT	106	u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
39aaca1f KG	107	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
39aaca1f KG	108
fbb9ecf7	109	sysInfo->freqProcessor[cpu] =
39aaca1f KG	110	freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	111	}
	112
	113	#define PME_CLK_SEL 0x80000000
	114	#define FM1_CLK_SEL 0x40000000
	115	#define FM2_CLK_SEL 0x20000000
b5c8753f KG	116	#define HWA_ASYNC_DIV 0x04000000
	117	#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
	118	#define HWA_CC_PLL 1
4905443f TT	119	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
4905443f TT	120	#define HWA_CC_PLL 2
b5c8753f	121	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5	122	#define HWA_CC_PLL 2
b5c8753f KG	123	#else
	124	#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
	125	#endif
39aaca1f KG	126	rcw_tmp = in_be32(&gur->rcwsr[7]);
	127
	128	#ifdef CONFIG_SYS_DPAA_PME
b5c8753f KG	129	if (rcw_tmp & PME_CLK_SEL) {
	130	if (rcw_tmp & HWA_ASYNC_DIV)
	131	sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
	132	else
	133	sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
	134	} else {
693416fe	135	sysInfo->freqPME = sysInfo->freqSystemBus / 2;
b5c8753f	136	}
39aaca1f KG	137	#endif
	138
	139	#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f KG	140	if (rcw_tmp & FM1_CLK_SEL) {
	141	if (rcw_tmp & HWA_ASYNC_DIV)
	142	sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
	143	else
	144	sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
	145	} else {
693416fe	146	sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
b5c8753f	147	}
39aaca1f	148	#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f KG	149	if (rcw_tmp & FM2_CLK_SEL) {
	150	if (rcw_tmp & HWA_ASYNC_DIV)
	151	sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
	152	else
	153	sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
	154	} else {
693416fe	155	sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
b5c8753f	156	}
39aaca1f KG	157	#endif
	158	#endif
	159
	160	#else
66ed6cca	161	uint plat_ratio,e500_ratio,half_freqSystemBus;
beba93ed	162	#if defined(CONFIG_FSL_LBC)
ada591d2	163	uint lcrr_div;
beba93ed	164	#endif
2fc7eb0c	165	int i;
b3d7f20f	166	#ifdef CONFIG_QE
a52d2f81	167	__maybe_unused u32 qe_ratio;
b3d7f20f	168	#endif
42d1f039 WD	169
	170	plat_ratio = (gur->porpllsr) & 0x0000003e;
	171	plat_ratio >>= 1;
66ed6cca	172	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca AF	173
	174	/* Divide before multiply to avoid integer
	175	* overflow for processor speeds above 2GHz */
	176	half_freqSystemBus = sysInfo->freqSystemBus/2;
0e870980	177	for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c HW	178	e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
	179	sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
	180	}
a3e77fa5 JY	181
a3e77fa5 JY	182	/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
d4357932 KG	183	sysInfo->freqDDRBus = sysInfo->freqSystemBus;
	184
	185	#ifdef CONFIG_DDR_CLK_FREQ
	186	{
c0391111 JJ	187	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	188	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932 KG	189	if (ddr_ratio != 0x7)
	190	sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	191	}
	192	#endif
ada591d2	193
b3d7f20f	194	#ifdef CONFIG_QE
be7bebea	195	#if defined(CONFIG_P1012) \|\| defined(CONFIG_P1021) \|\| defined(CONFIG_P1025)
a52d2f81 HW	196	sysInfo->freqQE = sysInfo->freqSystemBus;
a52d2f81 HW	197	#else
b3d7f20f HW	198	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
	199	>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	200	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
	201	#endif
a52d2f81	202	#endif
b3d7f20f	203
24995d82	204	#ifdef CONFIG_SYS_DPAA_FMAN
939cdcdc	205	sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
24995d82 HW	206	#endif
	207
	208	#endif /* CONFIG_FSL_CORENET */
	209
beba93ed	210	#if defined(CONFIG_FSL_LBC)
ada591d2 TP	211	#if defined(CONFIG_SYS_LBC_LCRR)
	212	/* We will program LCRR to this value later */
	213	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
	214	#else
f51cdaf1	215	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2 TP	216	#endif
ada591d2 TP	217	if (lcrr_div == 2 \|\| lcrr_div == 4 \|\| lcrr_div == 8) {
0fd2fa6c DL	218	#if defined(CONFIG_FSL_CORENET)
	219	/* If this is corenet based SoC, bit-representation
	220	* for four times the clock divider values.
	221	*/
	222	lcrr_div *= 4;
	223	#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
ada591d2 TP	224	!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
	225	/*
	226	* Yes, the entire PQ38 family use the same
	227	* bit-representation for twice the clock divider values.
	228	*/
	229	lcrr_div *= 2;
	230	#endif
	231	sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
	232	} else {
	233	/* In case anyone cares what the unknown value is */
	234	sysInfo->freqLocalBus = lcrr_div;
	235	}
beba93ed	236	#endif
800c73c4 KG	237
	238	#if defined(CONFIG_FSL_IFC)
	239	ccr = in_be32(&ifc_regs->ifc_ccr);
	240	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
	241
	242	sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
	243	#endif
42d1f039 WD	244	}
42d1f039 WD	245
66ed6cca	246
42d1f039 WD	247	int get_clocks (void)
42d1f039 WD	248	{
42d1f039	249	sys_info_t sys_info;
88353a98	250	#ifdef CONFIG_MPC8544
6d0f6bcf	251	volatile ccsr_gur_t gur = (void ) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98	252	#endif
9c4c5ae3	253	#if defined(CONFIG_CPM2)
6d0f6bcf	254	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	255	uint sccr, dfbrg;
	256
	257	/* set VCO = 4 * BRG */
aafeefbd KG	258	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
aafeefbd KG	259	sccr = cpm->im_cpm_intctl.sccr;
42d1f039 WD	260	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	261	#endif
	262	get_sys_info (&sys_info);
2fc7eb0c	263	gd->cpu_clk = sys_info.freqProcessor[0];
42d1f039	264	gd->bus_clk = sys_info.freqSystemBus;
a3e77fa5	265	gd->mem_clk = sys_info.freqDDRBus;
ada591d2	266	gd->lbc_clk = sys_info.freqLocalBus;
88353a98	267
b3d7f20f HW	268	#ifdef CONFIG_QE
	269	gd->qe_clk = sys_info.freqQE;
	270	gd->brg_clk = gd->qe_clk / 2;
	271	#endif
88353a98 TT	272	/*
	273	* The base clock for I2C depends on the actual SOC. Unfortunately,
	274	* there is no pattern that can be used to determine the frequency, so
	275	* the only choice is to look up the actual SOC number and use the value
	276	* for that SOC. This information is taken from application note
	277	* AN2919.
	278	*/
	279	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
	280	defined(CONFIG_MPC8560) \|\| defined(CONFIG_MPC8555)
943afa22	281	gd->i2c1_clk = sys_info.freqSystemBus;
88353a98 TT	282	#elif defined(CONFIG_MPC8544)
	283	/*
	284	* On the 8544, the I2C clock is the same as the SEC clock. This can be
	285	* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	286	* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
	287	* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	288	* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	289	*/
	290	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
dffd2446	291	gd->i2c1_clk = sys_info.freqSystemBus / 3;
42653b82 KG	292	else
42653b82 KG	293	gd->i2c1_clk = sys_info.freqSystemBus / 2;
88353a98 TT	294	#else
	295	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	296	gd->i2c1_clk = sys_info.freqSystemBus / 2;
	297	#endif
	298	gd->i2c2_clk = gd->i2c1_clk;
943afa22	299
6b9ea08c	300	#if defined(CONFIG_FSL_ESDHC)
7d640e9b PJ	301	#if defined(CONFIG_MPC8569) \|\| defined(CONFIG_P1010) \|\|\
7d640e9b PJ	302	defined(CONFIG_P1014)
7f52ed5e AV	303	gd->sdhc_clk = gd->bus_clk;
7f52ed5e AV	304	#else
ef50d6c0 KG	305	gd->sdhc_clk = gd->bus_clk / 2;
ef50d6c0 KG	306	#endif
7f52ed5e	307	#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0	308
9c4c5ae3	309	#if defined(CONFIG_CPM2)
42d1f039 WD	310	gd->vco_out = 2*sys_info.freqSystemBus;
	311	gd->cpm_clk = gd->vco_out / 2;
	312	gd->scc_clk = gd->vco_out / 4;
	313	gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
	314	#endif
	315
	316	if(gd->cpu_clk != 0) return (0);
	317	else return (1);
	318	}
	319
	320
	321	/********************************************
	322	* get_bus_freq
	323	* return system bus freq in Hz
	324	*********************************************/
	325	ulong get_bus_freq (ulong dummy)
	326	{
a3e77fa5	327	return gd->bus_clk;
42d1f039	328	}
d4357932 KG	329
	330	/********************************************
	331	* get_ddr_freq
	332	* return ddr bus freq in Hz
	333	*********************************************/
	334	ulong get_ddr_freq (ulong dummy)
	335	{
a3e77fa5	336	return gd->mem_clk;
d4357932	337	}