[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / tlb.c

/*
 * Copyright 2008-2009 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

void invalidate_tlb(u8 tlb)
{
	if (tlb == 0)
		mtspr(MMUCSR0, 0x4);
	if (tlb == 1)
		mtspr(MMUCSR0, 0x2);
}

void init_tlbs(void)
{
	int i;

	for (i = 0; i < num_tlb_entries; i++) {
		write_tlb(tlb_table[i].mas0,
			  tlb_table[i].mas1,
			  tlb_table[i].mas2,
			  tlb_table[i].mas3,
			  tlb_table[i].mas7);
	}

	return ;
}

void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
		       phys_addr_t *rpn)
{
	u32 _mas1;

	mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
	asm volatile("tlbre;isync");
	_mas1 = mfspr(MAS1);

	*valid = (_mas1 & MAS1_VALID);
	*tsize = (_mas1 >> 8) & 0xf;
	*epn = mfspr(MAS2) & MAS2_EPN;
	*rpn = mfspr(MAS3) & MAS3_RPN;
#ifdef CONFIG_ENABLE_36BIT_PHYS
	*rpn |= ((u64)mfspr(MAS7)) << 32;
#endif
}

#ifndef CONFIG_NAND_SPL
static inline void use_tlb_cam(u8 idx)
{
	int i = idx / 32;
	int bit = idx % 32;

	gd->used_tlb_cams[i] |= (1 << bit);
}

static inline void free_tlb_cam(u8 idx)
{
	int i = idx / 32;
	int bit = idx % 32;

	gd->used_tlb_cams[i] &= ~(1 << bit);
}

void init_used_tlb_cams(void)
{
	int i;
	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;

	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
		gd->used_tlb_cams[i] = 0;

	/* walk all the entries */
	for (i = 0; i < num_cam; i++) {
		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
		asm volatile("tlbre;isync");
		if (mfspr(MAS1) & MAS1_VALID)
			use_tlb_cam(i);
	}
}

int find_free_tlbcam(void)
{
	int i;
	u32 idx;

	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
		idx = ffz(gd->used_tlb_cams[i]);

		if (idx != 32)
			break;
	}

	idx += i * 32;

	if (idx >= CONFIG_SYS_NUM_TLBCAMS)
		return -1;

	return idx;
}

void set_tlb(u8 tlb, u32 epn, u64 rpn,
	     u8 perms, u8 wimge,
	     u8 ts, u8 esel, u8 tsize, u8 iprot)
{
	u32 _mas0, _mas1, _mas2, _mas3, _mas7;

	if (tlb == 1)
		use_tlb_cam(esel);

	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
	_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
	_mas7 = FSL_BOOKE_MAS7(rpn);

	write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);

#ifdef CONFIG_ADDR_MAP
	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
		addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
#endif
}

void disable_tlb(u8 esel)
{
	u32 _mas0, _mas1, _mas2, _mas3, _mas7;

	free_tlb_cam(esel);

	_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
	_mas1 = 0;
	_mas2 = 0;
	_mas3 = 0;
	_mas7 = 0;

	mtspr(MAS0, _mas0);
	mtspr(MAS1, _mas1);
	mtspr(MAS2, _mas2);
	mtspr(MAS3, _mas3);
#ifdef CONFIG_ENABLE_36BIT_PHYS
	mtspr(MAS7, _mas7);
#endif
	asm volatile("isync;msync;tlbwe;isync");

#ifdef CONFIG_ADDR_MAP
	if (gd->flags & GD_FLG_RELOC)
		addrmap_set_entry(0, 0, 0, esel);
#endif
}

static void tlbsx (const volatile unsigned *addr)
{
	__asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
}

/* return -1 if we didn't find anything */
int find_tlb_idx(void *addr, u8 tlbsel)
{
	u32 _mas0, _mas1;

	/* zero out Search PID, AS */
	mtspr(MAS6, 0);

	tlbsx(addr);

	_mas0 = mfspr(MAS0);
	_mas1 = mfspr(MAS1);

	/* we found something, and its in the TLB we expect */
	if ((MAS1_VALID & _mas1) &&
		(MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
		return ((_mas0 & MAS0_ESEL_MSK) >> 16);
	}

	return -1;
}

#ifdef CONFIG_ADDR_MAP
void init_addr_map(void)
{
	int i;
	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;

	/* walk all the entries */
	for (i = 0; i < num_cam; i++) {
		unsigned long epn;
		u32 tsize, valid;
		phys_addr_t rpn;

		read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
		if (valid & MAS1_VALID)
			addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
	}

	return ;
}
#endif

unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
	int i;
	unsigned int tlb_size;
	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
	u64 size, memsize = (u64)memsize_in_meg << 20;

	size = min(memsize, CONFIG_MAX_MEM_MAPPED);

	/* Convert (4^max) kB to (2^max) bytes */
	max_cam = max_cam * 2 + 10;

	for (i = 0; size && i < 8; i++) {
		int ram_tlb_index = find_free_tlbcam();
		u32 camsize = __ilog2_u64(size) & ~1U;
		u32 align = __ilog2(ram_tlb_address) & ~1U;

		if (ram_tlb_index == -1)
			break;

		if (align == -2) align = max_cam;
		if (camsize > align)
			camsize = align;

		if (camsize > max_cam)
			camsize = max_cam;

		tlb_size = (camsize - 10) / 2;

		set_tlb(1, ram_tlb_address, ram_tlb_address,
			MAS3_SX|MAS3_SW|MAS3_SR, 0,
			0, ram_tlb_index, tlb_size, 1);

		size -= 1ULL << camsize;
		memsize -= 1ULL << camsize;
		ram_tlb_address += 1UL << camsize;
	}

	if (memsize)
		print_size(memsize, " left unmapped\n");

	/*
	 * Confirm that the requested amount of memory was mapped.
	 */
	return memsize_in_meg;
}
#endif /* !CONFIG_NAND_SPL */
Commit	Line	Data
44a23cfd	1	/*
d30f9043	2	* Copyright 2008-2009 Freescale Semiconductor, Inc.
44a23cfd KG	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/processor.h>
	28	#include <asm/mmu.h>
ecf5b98c KG	29	#ifdef CONFIG_ADDR_MAP
	30	#include <addr_map.h>
	31	#endif
	32
	33	DECLARE_GLOBAL_DATA_PTR;
44a23cfd	34
b2eec281 KG	35	void invalidate_tlb(u8 tlb)
	36	{
	37	if (tlb == 0)
	38	mtspr(MMUCSR0, 0x4);
	39	if (tlb == 1)
	40	mtspr(MMUCSR0, 0x2);
	41	}
	42
	43	void init_tlbs(void)
	44	{
	45	int i;
	46
	47	for (i = 0; i < num_tlb_entries; i++) {
	48	write_tlb(tlb_table[i].mas0,
	49	tlb_table[i].mas1,
	50	tlb_table[i].mas2,
	51	tlb_table[i].mas3,
	52	tlb_table[i].mas7);
	53	}
	54
	55	return ;
	56	}
	57
4e63df30 BB	58	void read_tlbcam_entry(int idx, u32 valid, u32 tsize, unsigned long *epn,
	59	phys_addr_t *rpn)
	60	{
	61	u32 _mas1;
	62
	63	mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
	64	asm volatile("tlbre;isync");
	65	_mas1 = mfspr(MAS1);
	66
	67	*valid = (_mas1 & MAS1_VALID);
	68	*tsize = (_mas1 >> 8) & 0xf;
	69	*epn = mfspr(MAS2) & MAS2_EPN;
	70	*rpn = mfspr(MAS3) & MAS3_RPN;
	71	#ifdef CONFIG_ENABLE_36BIT_PHYS
	72	*rpn \|= ((u64)mfspr(MAS7)) << 32;
	73	#endif
	74	}
	75
7da53351	76	#ifndef CONFIG_NAND_SPL
94e9411b KG	77	static inline void use_tlb_cam(u8 idx)
	78	{
	79	int i = idx / 32;
	80	int bit = idx % 32;
	81
	82	gd->used_tlb_cams[i] \|= (1 << bit);
	83	}
	84
	85	static inline void free_tlb_cam(u8 idx)
	86	{
	87	int i = idx / 32;
	88	int bit = idx % 32;
	89
	90	gd->used_tlb_cams[i] &= ~(1 << bit);
	91	}
	92
	93	void init_used_tlb_cams(void)
	94	{
	95	int i;
	96	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
	97
	98	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
	99	gd->used_tlb_cams[i] = 0;
	100
	101	/* walk all the entries */
	102	for (i = 0; i < num_cam; i++) {
94e9411b	103	mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
94e9411b	104	asm volatile("tlbre;isync");
4e63df30	105	if (mfspr(MAS1) & MAS1_VALID)
94e9411b KG	106	use_tlb_cam(i);
	107	}
	108	}
	109
	110	int find_free_tlbcam(void)
	111	{
	112	int i;
	113	u32 idx;
	114
	115	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
	116	idx = ffz(gd->used_tlb_cams[i]);
	117
	118	if (idx != 32)
	119	break;
	120	}
	121
	122	idx += i * 32;
	123
	124	if (idx >= CONFIG_SYS_NUM_TLBCAMS)
	125	return -1;
	126
	127	return idx;
	128	}
	129
44a23cfd KG	130	void set_tlb(u8 tlb, u32 epn, u64 rpn,
	131	u8 perms, u8 wimge,
	132	u8 ts, u8 esel, u8 tsize, u8 iprot)
	133	{
	134	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
	135
94e9411b KG	136	if (tlb == 1)
	137	use_tlb_cam(esel);
	138
44a23cfd KG	139	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
	140	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
	141	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
	142	_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
d30f9043	143	_mas7 = FSL_BOOKE_MAS7(rpn);
44a23cfd	144
d30f9043	145	write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
ecf5b98c KG	146
	147	#ifdef CONFIG_ADDR_MAP
	148	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
4e63df30	149	addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
ecf5b98c	150	#endif
44a23cfd KG	151	}
	152
	153	void disable_tlb(u8 esel)
	154	{
	155	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
	156
94e9411b KG	157	free_tlb_cam(esel);
94e9411b KG	158
44a23cfd KG	159	_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
	160	_mas1 = 0;
	161	_mas2 = 0;
	162	_mas3 = 0;
	163	_mas7 = 0;
	164
	165	mtspr(MAS0, _mas0);
	166	mtspr(MAS1, _mas1);
	167	mtspr(MAS2, _mas2);
	168	mtspr(MAS3, _mas3);
	169	#ifdef CONFIG_ENABLE_36BIT_PHYS
	170	mtspr(MAS7, _mas7);
	171	#endif
	172	asm volatile("isync;msync;tlbwe;isync");
ecf5b98c KG	173
	174	#ifdef CONFIG_ADDR_MAP
	175	if (gd->flags & GD_FLG_RELOC)
	176	addrmap_set_entry(0, 0, 0, esel);
	177	#endif
44a23cfd KG	178	}
44a23cfd KG	179
c2287af1 KG	180	static void tlbsx (const volatile unsigned *addr)
	181	{
	182	__asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
	183	}
	184
	185	/* return -1 if we didn't find anything */
	186	int find_tlb_idx(void *addr, u8 tlbsel)
	187	{
	188	u32 _mas0, _mas1;
	189
	190	/* zero out Search PID, AS */
	191	mtspr(MAS6, 0);
	192
	193	tlbsx(addr);
	194
	195	_mas0 = mfspr(MAS0);
	196	_mas1 = mfspr(MAS1);
	197
	198	/* we found something, and its in the TLB we expect */
	199	if ((MAS1_VALID & _mas1) &&
	200	(MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
	201	return ((_mas0 & MAS0_ESEL_MSK) >> 16);
	202	}
	203
	204	return -1;
	205	}
	206
ecf5b98c KG	207	#ifdef CONFIG_ADDR_MAP
	208	void init_addr_map(void)
	209	{
	210	int i;
cdbdbe65	211	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
ecf5b98c	212
e393e2e9	213	/* walk all the entries */
cdbdbe65	214	for (i = 0; i < num_cam; i++) {
e393e2e9	215	unsigned long epn;
4e63df30	216	u32 tsize, valid;
e393e2e9 KG	217	phys_addr_t rpn;
e393e2e9 KG	218
4e63df30 BB	219	read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
	220	if (valid & MAS1_VALID)
	221	addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
ecf5b98c KG	222	}
	223
	224	return ;
	225	}
	226	#endif
	227
6fb1b734 KG	228	unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
6fb1b734 KG	229	{
355f4f85	230	int i;
6fb1b734	231	unsigned int tlb_size;
f8523cb0	232	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
90d13b8a	233	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
f8523cb0	234	u64 size, memsize = (u64)memsize_in_meg << 20;
6fb1b734	235
f8523cb0 KG	236	size = min(memsize, CONFIG_MAX_MEM_MAPPED);
	237
	238	/* Convert (4^max) kB to (2^max) bytes */
	239	max_cam = max_cam * 2 + 10;
	240
355f4f85 KG	241	for (i = 0; size && i < 8; i++) {
355f4f85 KG	242	int ram_tlb_index = find_free_tlbcam();
f8523cb0 KG	243	u32 camsize = __ilog2_u64(size) & ~1U;
	244	u32 align = __ilog2(ram_tlb_address) & ~1U;
	245
355f4f85 KG	246	if (ram_tlb_index == -1)
	247	break;
	248
f8523cb0 KG	249	if (align == -2) align = max_cam;
	250	if (camsize > align)
	251	camsize = align;
	252
	253	if (camsize > max_cam)
	254	camsize = max_cam;
	255
	256	tlb_size = (camsize - 10) / 2;
6fb1b734	257
6fb1b734 KG	258	set_tlb(1, ram_tlb_address, ram_tlb_address,
	259	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	260	0, ram_tlb_index, tlb_size, 1);
	261
f8523cb0 KG	262	size -= 1ULL << camsize;
	263	memsize -= 1ULL << camsize;
	264	ram_tlb_address += 1UL << camsize;
6fb1b734 KG	265	}
6fb1b734 KG	266
f8523cb0	267	if (memsize)
d4b130dc	268	print_size(memsize, " left unmapped\n");
f8523cb0	269
6fb1b734 KG	270	/*
	271	* Confirm that the requested amount of memory was mapped.
	272	*/
	273	return memsize_in_meg;
	274	}
7da53351	275	#endif /* !CONFIG_NAND_SPL */