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debb7354 | 1 | /* |
9ff32d8c | 2 | * Copyright 2006,2009-2010 Freescale Semiconductor, Inc. |
cb5965fb | 3 | * Jeff Brown |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <watchdog.h> | |
27 | #include <command.h> | |
28 | #include <asm/cache.h> | |
e34a0e91 | 29 | #include <asm/mmu.h> |
debb7354 | 30 | #include <mpc86xx.h> |
4f93f8b1 | 31 | #include <asm/fsl_law.h> |
debb7354 | 32 | |
0e870980 PA |
33 | DECLARE_GLOBAL_DATA_PTR; |
34 | ||
4ef630df PT |
35 | /* |
36 | * Default board reset function | |
37 | */ | |
38 | static void | |
39 | __board_reset(void) | |
40 | { | |
41 | /* Do nothing */ | |
42 | } | |
f9a109b3 | 43 | void board_reset(void) __attribute__((weak, alias("__board_reset"))); |
4ef630df PT |
44 | |
45 | ||
ffff3ae5 JL |
46 | int |
47 | checkcpu(void) | |
debb7354 JL |
48 | { |
49 | sys_info_t sysinfo; | |
50 | uint pvr, svr; | |
51 | uint ver; | |
52 | uint major, minor; | |
a1c8a719 | 53 | char buf1[32], buf2[32]; |
6d0f6bcf | 54 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
9553df86 | 55 | volatile ccsr_gur_t *gur = &immap->im_gur; |
480f6179 | 56 | struct cpu_type *cpu; |
a1c8a719 | 57 | uint msscr0 = mfspr(MSSCR0); |
debb7354 JL |
58 | |
59 | svr = get_svr(); | |
1ced1216 | 60 | ver = SVR_SOC_VER(svr); |
debb7354 JL |
61 | major = SVR_MAJ(svr); |
62 | minor = SVR_MIN(svr); | |
63 | ||
21170c80 PA |
64 | if (cpu_numcores() > 1) { |
65 | #ifndef CONFIG_MP | |
66 | puts("Unicore software on multiprocessor system!!\n" | |
67 | "To enable mutlticore build define CONFIG_MP\n"); | |
68 | #endif | |
69 | } | |
a1c8a719 PT |
70 | puts("CPU: "); |
71 | ||
0e870980 PA |
72 | cpu = gd->cpu; |
73 | ||
58442dc0 | 74 | puts(cpu->name); |
480f6179 | 75 | |
debb7354 | 76 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
a1c8a719 PT |
77 | puts("Core: "); |
78 | ||
79 | pvr = get_pvr(); | |
80 | ver = PVR_E600_VER(pvr); | |
81 | major = PVR_E600_MAJ(pvr); | |
82 | minor = PVR_E600_MIN(pvr); | |
83 | ||
84 | printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); | |
85 | if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) | |
86 | puts("\n Core1Translation Enabled"); | |
87 | debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); | |
88 | ||
89 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); | |
debb7354 JL |
90 | |
91 | get_sys_info(&sysinfo); | |
92 | ||
a1c8a719 PT |
93 | puts("Clock Configuration:\n"); |
94 | printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); | |
95 | printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); | |
96 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", | |
97 | strmhz(buf1, sysinfo.freqSystemBus / 2), | |
98 | strmhz(buf2, sysinfo.freqSystemBus)); | |
5c9efb36 | 99 | |
ada591d2 | 100 | if (sysinfo.freqLocalBus > LCRR_CLKDIV) { |
a1c8a719 | 101 | printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); |
debb7354 | 102 | } else { |
a9f3acbc | 103 | printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", |
ada591d2 | 104 | sysinfo.freqLocalBus); |
debb7354 JL |
105 | } |
106 | ||
a1c8a719 PT |
107 | puts("L1: D-cache 32 KB enabled\n"); |
108 | puts(" I-cache 32 KB enabled\n"); | |
109 | ||
110 | puts("L2: "); | |
111 | if (get_l2cr() & 0x80000000) { | |
112 | #if defined(CONFIG_MPC8610) | |
113 | puts("256"); | |
114 | #elif defined(CONFIG_MPC8641) | |
115 | puts("512"); | |
116 | #endif | |
117 | puts(" KB enabled\n"); | |
118 | } else { | |
cb5965fb | 119 | puts("Disabled\n"); |
a1c8a719 | 120 | } |
5c9efb36 JL |
121 | |
122 | return 0; | |
debb7354 JL |
123 | } |
124 | ||
125 | ||
debb7354 | 126 | void |
126aa70f | 127 | do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
debb7354 | 128 | { |
4ef630df PT |
129 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
130 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
5c9efb36 | 131 | |
4ef630df PT |
132 | /* Attempt board-specific reset */ |
133 | board_reset(); | |
5c9efb36 | 134 | |
4ef630df PT |
135 | /* Next try asserting HRESET_REQ */ |
136 | out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ); | |
5c9efb36 | 137 | |
4ef630df PT |
138 | while (1) |
139 | ; | |
debb7354 JL |
140 | } |
141 | ||
142 | ||
debb7354 JL |
143 | /* |
144 | * Get timebase clock frequency | |
145 | */ | |
ffff3ae5 JL |
146 | unsigned long |
147 | get_tbclk(void) | |
debb7354 | 148 | { |
ffff3ae5 | 149 | sys_info_t sys_info; |
debb7354 JL |
150 | |
151 | get_sys_info(&sys_info); | |
5c9efb36 | 152 | return (sys_info.freqSystemBus + 3L) / 4L; |
debb7354 JL |
153 | } |
154 | ||
debb7354 JL |
155 | |
156 | #if defined(CONFIG_WATCHDOG) | |
157 | void | |
158 | watchdog_reset(void) | |
159 | { | |
3473ab73 JJ |
160 | #if defined(CONFIG_MPC8610) |
161 | /* | |
162 | * This actually feed the hard enabled watchdog. | |
163 | */ | |
6d0f6bcf | 164 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
3473ab73 JJ |
165 | volatile ccsr_wdt_t *wdt = &immap->im_wdt; |
166 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
167 | u32 tmp = gur->pordevsr; | |
168 | ||
169 | if (tmp & 0x4000) { | |
170 | wdt->swsrr = 0x556c; | |
171 | wdt->swsrr = 0xaa39; | |
172 | } | |
173 | #endif | |
debb7354 JL |
174 | } |
175 | #endif /* CONFIG_WATCHDOG */ | |
176 | ||
4f93f8b1 BB |
177 | /* |
178 | * Print out the state of various machine registers. | |
e34a0e91 | 179 | * Currently prints out LAWs, BR0/OR0, and BATs |
4f93f8b1 BB |
180 | */ |
181 | void mpc86xx_reginfo(void) | |
182 | { | |
6d0f6bcf | 183 | immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
4f93f8b1 BB |
184 | ccsr_lbc_t *lbc = &immap->im_lbc; |
185 | ||
e34a0e91 | 186 | print_bats(); |
4f93f8b1 BB |
187 | print_laws(); |
188 | ||
189 | printf ("Local Bus Controller Registers\n" | |
190 | "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0)); | |
191 | printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1)); | |
192 | printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2)); | |
193 | printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3)); | |
194 | printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4)); | |
195 | printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5)); | |
196 | printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6)); | |
197 | printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); | |
debb7354 JL |
198 | |
199 | } | |
9ff32d8c TT |
200 | |
201 | /* | |
202 | * Set the DDR BATs to reflect the actual size of DDR. | |
203 | * | |
204 | * dram_size is the actual size of DDR, in bytes | |
205 | * | |
206 | * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only | |
207 | * are using a single BAT to cover DDR. | |
208 | * | |
209 | * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN | |
210 | * is not defined) then we might have a situation where U-Boot will attempt | |
211 | * to relocated itself outside of the region mapped by DBAT0. | |
212 | * This will cause a machine check. | |
213 | * | |
214 | * Currently we are limited to power of two sized DDR since we only use a | |
215 | * single bat. If a non-power of two size is used that is less than | |
216 | * CONFIG_MAX_MEM_MAPPED u-boot will crash. | |
217 | * | |
218 | */ | |
219 | void setup_ddr_bat(phys_addr_t dram_size) | |
220 | { | |
221 | unsigned long batu, bl; | |
222 | ||
223 | bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED)); | |
224 | ||
225 | if (BATU_SIZE(bl) != dram_size) { | |
226 | u64 sz = (u64)dram_size - BATU_SIZE(bl); | |
227 | print_size(sz, " left unmapped\n"); | |
228 | } | |
229 | ||
230 | batu = bl | BATU_VS | BATU_VP; | |
231 | write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L); | |
232 | write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L); | |
233 | } |