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0de1ffc8 WD |
1 | /* |
2 | * (C) Copyright 2000-2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0de1ffc8 WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
0de1ffc8 WD |
9 | #include <mpc8xx.h> |
10 | #include <mpc8xx_irq.h> | |
11 | #include <asm/processor.h> | |
12 | #include <commproc.h> | |
13 | ||
7c7a23bd | 14 | /************************************************************************/ |
0de1ffc8 | 15 | |
0de1ffc8 WD |
16 | /* |
17 | * CPM interrupt vector functions. | |
18 | */ | |
7c7a23bd WD |
19 | struct interrupt_action { |
20 | interrupt_handler_t *handler; | |
21 | void *arg; | |
0de1ffc8 WD |
22 | }; |
23 | ||
7c7a23bd WD |
24 | static struct interrupt_action cpm_vecs[CPMVEC_NR]; |
25 | static struct interrupt_action irq_vecs[NR_IRQS]; | |
0de1ffc8 WD |
26 | |
27 | static void cpm_interrupt_init (void); | |
7c7a23bd | 28 | static void cpm_interrupt (void *regs); |
0de1ffc8 | 29 | |
7c7a23bd | 30 | /************************************************************************/ |
0de1ffc8 | 31 | |
a8c7c708 | 32 | int interrupt_init_cpu (unsigned *decrementer_count) |
0de1ffc8 | 33 | { |
6d0f6bcf | 34 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
0de1ffc8 | 35 | |
6d0f6bcf | 36 | *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; |
0de1ffc8 | 37 | |
7c7a23bd WD |
38 | /* disable all interrupts */ |
39 | immr->im_siu_conf.sc_simask = 0; | |
0de1ffc8 | 40 | |
7c7a23bd WD |
41 | /* Configure CPM interrupts */ |
42 | cpm_interrupt_init (); | |
0de1ffc8 | 43 | |
0de1ffc8 WD |
44 | return (0); |
45 | } | |
46 | ||
7c7a23bd | 47 | /************************************************************************/ |
0de1ffc8 WD |
48 | |
49 | /* | |
50 | * Handle external interrupts | |
51 | */ | |
7c7a23bd | 52 | void external_interrupt (struct pt_regs *regs) |
0de1ffc8 | 53 | { |
6d0f6bcf | 54 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
7c7a23bd WD |
55 | int irq; |
56 | ulong simask, newmask; | |
57 | ulong vec, v_bit; | |
0de1ffc8 WD |
58 | |
59 | /* | |
60 | * read the SIVEC register and shift the bits down | |
61 | * to get the irq number | |
62 | */ | |
63 | vec = immr->im_siu_conf.sc_sivec; | |
64 | irq = vec >> 26; | |
65 | v_bit = 0x80000000UL >> irq; | |
66 | ||
67 | /* | |
68 | * Read Interrupt Mask Register and Mask Interrupts | |
69 | */ | |
70 | simask = immr->im_siu_conf.sc_simask; | |
71 | newmask = simask & (~(0xFFFF0000 >> irq)); | |
72 | immr->im_siu_conf.sc_simask = newmask; | |
73 | ||
7c7a23bd | 74 | if (!(irq & 0x1)) { /* External Interrupt ? */ |
0de1ffc8 | 75 | ulong siel; |
7c7a23bd | 76 | |
0de1ffc8 WD |
77 | /* |
78 | * Read Interrupt Edge/Level Register | |
79 | */ | |
80 | siel = immr->im_siu_conf.sc_siel; | |
81 | ||
7c7a23bd | 82 | if (siel & v_bit) { /* edge triggered interrupt ? */ |
0de1ffc8 WD |
83 | /* |
84 | * Rewrite SIPEND Register to clear interrupt | |
85 | */ | |
86 | immr->im_siu_conf.sc_sipend = v_bit; | |
87 | } | |
88 | } | |
89 | ||
7c7a23bd WD |
90 | if (irq_vecs[irq].handler != NULL) { |
91 | irq_vecs[irq].handler (irq_vecs[irq].arg); | |
92 | } else { | |
0de1ffc8 | 93 | printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", |
7c7a23bd | 94 | irq, vec); |
0de1ffc8 WD |
95 | /* turn off the bogus interrupt to avoid it from now */ |
96 | simask &= ~v_bit; | |
0de1ffc8 | 97 | } |
0de1ffc8 WD |
98 | /* |
99 | * Re-Enable old Interrupt Mask | |
100 | */ | |
101 | immr->im_siu_conf.sc_simask = simask; | |
102 | } | |
103 | ||
7c7a23bd | 104 | /************************************************************************/ |
0de1ffc8 WD |
105 | |
106 | /* | |
107 | * CPM interrupt handler | |
108 | */ | |
7c7a23bd | 109 | static void cpm_interrupt (void *regs) |
0de1ffc8 | 110 | { |
6d0f6bcf | 111 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
7c7a23bd | 112 | uint vec; |
0de1ffc8 WD |
113 | |
114 | /* | |
115 | * Get the vector by setting the ACK bit | |
116 | * and then reading the register. | |
117 | */ | |
118 | immr->im_cpic.cpic_civr = 1; | |
119 | vec = immr->im_cpic.cpic_civr; | |
120 | vec >>= 11; | |
121 | ||
122 | if (cpm_vecs[vec].handler != NULL) { | |
7c7a23bd | 123 | (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); |
0de1ffc8 WD |
124 | } else { |
125 | immr->im_cpic.cpic_cimr &= ~(1 << vec); | |
126 | printf ("Masking bogus CPM interrupt vector 0x%x\n", vec); | |
127 | } | |
128 | /* | |
7c7a23bd WD |
129 | * After servicing the interrupt, |
130 | * we have to remove the status indicator. | |
0de1ffc8 WD |
131 | */ |
132 | immr->im_cpic.cpic_cisr |= (1 << vec); | |
133 | } | |
134 | ||
135 | /* | |
136 | * The CPM can generate the error interrupt when there is a race | |
137 | * condition between generating and masking interrupts. All we have | |
138 | * to do is ACK it and return. This is a no-op function so we don't | |
139 | * need any special tests in the interrupt handler. | |
140 | */ | |
7c7a23bd | 141 | static void cpm_error_interrupt (void *dummy) |
0de1ffc8 WD |
142 | { |
143 | } | |
144 | ||
7c7a23bd | 145 | /************************************************************************/ |
0de1ffc8 | 146 | /* |
7c7a23bd | 147 | * Install and free an interrupt handler |
0de1ffc8 | 148 | */ |
7c7a23bd WD |
149 | void irq_install_handler (int vec, interrupt_handler_t * handler, |
150 | void *arg) | |
0de1ffc8 | 151 | { |
6d0f6bcf | 152 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
7c7a23bd WD |
153 | |
154 | if ((vec & CPMVEC_OFFSET) != 0) { | |
155 | /* CPM interrupt */ | |
156 | vec &= 0xffff; | |
157 | if (cpm_vecs[vec].handler != NULL) { | |
158 | printf ("CPM interrupt 0x%x replacing 0x%x\n", | |
159 | (uint) handler, | |
160 | (uint) cpm_vecs[vec].handler); | |
161 | } | |
162 | cpm_vecs[vec].handler = handler; | |
163 | cpm_vecs[vec].arg = arg; | |
164 | immr->im_cpic.cpic_cimr |= (1 << vec); | |
165 | #if 0 | |
166 | printf ("Install CPM interrupt for vector %d ==> %p\n", | |
167 | vec, handler); | |
168 | #endif | |
169 | } else { | |
170 | /* SIU interrupt */ | |
171 | if (irq_vecs[vec].handler != NULL) { | |
172 | printf ("SIU interrupt %d 0x%x replacing 0x%x\n", | |
173 | vec, | |
174 | (uint) handler, | |
175 | (uint) cpm_vecs[vec].handler); | |
176 | } | |
177 | irq_vecs[vec].handler = handler; | |
178 | irq_vecs[vec].arg = arg; | |
179 | immr->im_siu_conf.sc_simask |= 1 << (31 - vec); | |
0de1ffc8 | 180 | #if 0 |
7c7a23bd WD |
181 | printf ("Install SIU interrupt for vector %d ==> %p\n", |
182 | vec, handler); | |
0de1ffc8 | 183 | #endif |
7c7a23bd | 184 | } |
0de1ffc8 WD |
185 | } |
186 | ||
7c7a23bd | 187 | void irq_free_handler (int vec) |
0de1ffc8 | 188 | { |
6d0f6bcf | 189 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
7c7a23bd WD |
190 | |
191 | if ((vec & CPMVEC_OFFSET) != 0) { | |
192 | /* CPM interrupt */ | |
193 | vec &= 0xffff; | |
194 | #if 0 | |
195 | printf ("Free CPM interrupt for vector %d ==> %p\n", | |
196 | vec, cpm_vecs[vec].handler); | |
197 | #endif | |
198 | immr->im_cpic.cpic_cimr &= ~(1 << vec); | |
199 | cpm_vecs[vec].handler = NULL; | |
200 | cpm_vecs[vec].arg = NULL; | |
201 | } else { | |
202 | /* SIU interrupt */ | |
0de1ffc8 | 203 | #if 0 |
7c7a23bd WD |
204 | printf ("Free CPM interrupt for vector %d ==> %p\n", |
205 | vec, cpm_vecs[vec].handler); | |
0de1ffc8 | 206 | #endif |
7c7a23bd WD |
207 | immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); |
208 | irq_vecs[vec].handler = NULL; | |
209 | irq_vecs[vec].arg = NULL; | |
210 | } | |
0de1ffc8 WD |
211 | } |
212 | ||
7c7a23bd | 213 | /************************************************************************/ |
0de1ffc8 | 214 | |
7c7a23bd | 215 | static void cpm_interrupt_init (void) |
0de1ffc8 | 216 | { |
6d0f6bcf | 217 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
0de1ffc8 WD |
218 | |
219 | /* | |
220 | * Initialize the CPM interrupt controller. | |
221 | */ | |
222 | ||
223 | immr->im_cpic.cpic_cicr = | |
7c7a23bd WD |
224 | (CICR_SCD_SCC4 | |
225 | CICR_SCC_SCC3 | | |
226 | CICR_SCB_SCC2 | | |
227 | CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; | |
0de1ffc8 WD |
228 | |
229 | immr->im_cpic.cpic_cimr = 0; | |
230 | ||
231 | /* | |
232 | * Install the error handler. | |
233 | */ | |
7c7a23bd | 234 | irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL); |
0de1ffc8 WD |
235 | |
236 | immr->im_cpic.cpic_cicr |= CICR_IEN; | |
7c7a23bd WD |
237 | |
238 | /* | |
239 | * Install the cpm interrupt handler | |
240 | */ | |
241 | irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL); | |
0de1ffc8 WD |
242 | } |
243 | ||
7c7a23bd | 244 | /************************************************************************/ |
0de1ffc8 | 245 | |
0de1ffc8 WD |
246 | /* |
247 | * timer_interrupt - gets called when the decrementer overflows, | |
248 | * with interrupts disabled. | |
249 | * Trivial implementation - no need to be really accurate. | |
250 | */ | |
a8c7c708 | 251 | void timer_interrupt_cpu (struct pt_regs *regs) |
0de1ffc8 | 252 | { |
6d0f6bcf | 253 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
7c7a23bd | 254 | |
0de1ffc8 WD |
255 | #if 0 |
256 | printf ("*** Timer Interrupt *** "); | |
257 | #endif | |
258 | /* Reset Timer Expired and Timers Interrupt Status */ | |
259 | immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; | |
7c7a23bd | 260 | __asm__ ("nop"); |
180d3f74 WD |
261 | /* |
262 | Clear TEXPS (and TMIST on older chips). SPLSS (on older | |
263 | chips) is cleared too. | |
264 | ||
265 | Bitwise OR is a read-modify-write operation so ALL bits | |
266 | which are cleared by writing `1' would be cleared by | |
267 | operations like | |
268 | ||
269 | immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; | |
270 | ||
271 | The same can be achieved by simple writing of the PLPRCR | |
272 | to itself. If a bit value should be preserved, read the | |
273 | register, ZERO the bit and write, not OR, the result back. | |
274 | */ | |
275 | immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr; | |
0de1ffc8 WD |
276 | } |
277 | ||
7c7a23bd | 278 | /************************************************************************/ |