[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8xx / interrupts.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc8xx.h>
#include <mpc8xx_irq.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <commproc.h>

/************************************************************************/

/*
 * CPM interrupt vector functions.
 */
struct interrupt_action {
	interrupt_handler_t *handler;
	void *arg;
};

static struct interrupt_action cpm_vecs[CPMVEC_NR];
static struct interrupt_action irq_vecs[NR_IRQS];

static void cpm_interrupt_init(void);
static void cpm_interrupt(void *regs);

/************************************************************************/

int interrupt_init_cpu(unsigned *decrementer_count)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;

	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;

	/* disable all interrupts */
	out_be32(&immr->im_siu_conf.sc_simask, 0);

	/* Configure CPM interrupts */
	cpm_interrupt_init();

	return 0;
}

/************************************************************************/

/*
 * Handle external interrupts
 */
void external_interrupt(struct pt_regs *regs)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
	int irq;
	ulong simask;
	ulong vec, v_bit;

	/*
	 * read the SIVEC register and shift the bits down
	 * to get the irq number
	 */
	vec = in_be32(&immr->im_siu_conf.sc_sivec);
	irq = vec >> 26;
	v_bit = 0x80000000UL >> irq;

	/*
	 * Read Interrupt Mask Register and Mask Interrupts
	 */
	simask = in_be32(&immr->im_siu_conf.sc_simask);
	clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);

	if (!(irq & 0x1)) {		/* External Interrupt ?     */
		ulong siel;

		/*
		 * Read Interrupt Edge/Level Register
		 */
		siel = in_be32(&immr->im_siu_conf.sc_siel);

		if (siel & v_bit) {	/* edge triggered interrupt ?   */
			/*
			 * Rewrite SIPEND Register to clear interrupt
			 */
			out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
		}
	}

	if (irq_vecs[irq].handler != NULL) {
		irq_vecs[irq].handler(irq_vecs[irq].arg);
	} else {
		printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
		       irq, vec);
		/* turn off the bogus interrupt to avoid it from now */
		simask &= ~v_bit;
	}
	/*
	 * Re-Enable old Interrupt Mask
	 */
	out_be32(&immr->im_siu_conf.sc_simask, simask);
}

/************************************************************************/

/*
 * CPM interrupt handler
 */
static void cpm_interrupt(void *regs)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
	uint vec;

	/*
	 * Get the vector by setting the ACK bit
	 * and then reading the register.
	 */
	out_be16(&immr->im_cpic.cpic_civr, 1);
	vec = in_be16(&immr->im_cpic.cpic_civr);
	vec >>= 11;

	if (cpm_vecs[vec].handler != NULL) {
		(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
	} else {
		clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
		printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
	}
	/*
	 * After servicing the interrupt,
	 * we have to remove the status indicator.
	 */
	setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
}

/*
 * The CPM can generate the error interrupt when there is a race
 * condition between generating and masking interrupts. All we have
 * to do is ACK it and return. This is a no-op function so we don't
 * need any special tests in the interrupt handler.
 */
static void cpm_error_interrupt(void *dummy)
{
}

/************************************************************************/
/*
 * Install and free an interrupt handler
 */
void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;

	if ((vec & CPMVEC_OFFSET) != 0) {
		/* CPM interrupt */
		vec &= 0xffff;
		if (cpm_vecs[vec].handler != NULL)
			printf("CPM interrupt 0x%x replacing 0x%x\n",
			       (uint)handler, (uint)cpm_vecs[vec].handler);
		cpm_vecs[vec].handler = handler;
		cpm_vecs[vec].arg = arg;
		setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
	} else {
		/* SIU interrupt */
		if (irq_vecs[vec].handler != NULL)
			printf("SIU interrupt %d 0x%x replacing 0x%x\n",
			       vec, (uint)handler, (uint)cpm_vecs[vec].handler);
		irq_vecs[vec].handler = handler;
		irq_vecs[vec].arg = arg;
		setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
	}
}

void irq_free_handler(int vec)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;

	if ((vec & CPMVEC_OFFSET) != 0) {
		/* CPM interrupt */
		vec &= 0xffff;
		clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
		cpm_vecs[vec].handler = NULL;
		cpm_vecs[vec].arg = NULL;
	} else {
		/* SIU interrupt */
		clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
		irq_vecs[vec].handler = NULL;
		irq_vecs[vec].arg = NULL;
	}
}

/************************************************************************/

static void cpm_interrupt_init(void)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
	uint cicr;

	/*
	 * Initialize the CPM interrupt controller.
	 */

	cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
	       ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;

	out_be32(&immr->im_cpic.cpic_cicr, cicr);
	out_be32(&immr->im_cpic.cpic_cimr, 0);

	/*
	 * Install the error handler.
	 */
	irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);

	setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);

	/*
	 * Install the cpm interrupt handler
	 */
	irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
}

/************************************************************************/

/*
 * timer_interrupt - gets called when the decrementer overflows,
 * with interrupts disabled.
 * Trivial implementation - no need to be really accurate.
 */
void timer_interrupt_cpu(struct pt_regs *regs)
{
	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;

	/* Reset Timer Expired and Timers Interrupt Status */
	out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
	__asm__ ("nop");
	/*
	  Clear TEXPS (and TMIST on older chips). SPLSS (on older
	  chips) is cleared too.

	  Bitwise OR is a read-modify-write operation so ALL bits
	  which are cleared by writing `1' would be cleared by
	  operations like

	  immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;

	  The same can be achieved by simple writing of the PLPRCR
	  to itself. If a bit value should be preserved, read the
	  register, ZERO the bit and write, not OR, the result back.
	*/
	setbits_be32(&immr->im_clkrst.car_plprcr, 0);
}

/************************************************************************/
Commit	Line	Data
907208c4 CL	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <mpc8xx.h>
	10	#include <mpc8xx_irq.h>
	11	#include <asm/processor.h>
ba3da734	12	#include <asm/io.h>
907208c4 CL	13	#include <commproc.h>
	14
	15	/************************************************************************/
	16
	17	/*
	18	* CPM interrupt vector functions.
	19	*/
	20	struct interrupt_action {
	21	interrupt_handler_t *handler;
	22	void *arg;
	23	};
	24
	25	static struct interrupt_action cpm_vecs[CPMVEC_NR];
	26	static struct interrupt_action irq_vecs[NR_IRQS];
	27
70fd0710 CL	28	static void cpm_interrupt_init(void);
70fd0710 CL	29	static void cpm_interrupt(void *regs);
907208c4 CL	30
	31	/************************************************************************/
	32
70fd0710	33	int interrupt_init_cpu(unsigned *decrementer_count)
907208c4	34	{
ba3da734	35	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
907208c4	36
70fd0710	37	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
907208c4 CL	38
907208c4 CL	39	/* disable all interrupts */
ba3da734	40	out_be32(&immr->im_siu_conf.sc_simask, 0);
907208c4 CL	41
907208c4 CL	42	/* Configure CPM interrupts */
70fd0710	43	cpm_interrupt_init();
907208c4	44
70fd0710	45	return 0;
907208c4 CL	46	}
	47
	48	/************************************************************************/
	49
	50	/*
	51	* Handle external interrupts
	52	*/
70fd0710	53	void external_interrupt(struct pt_regs *regs)
907208c4	54	{
ba3da734	55	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
907208c4	56	int irq;
ba3da734	57	ulong simask;
907208c4 CL	58	ulong vec, v_bit;
	59
	60	/*
	61	* read the SIVEC register and shift the bits down
	62	* to get the irq number
	63	*/
ba3da734	64	vec = in_be32(&immr->im_siu_conf.sc_sivec);
907208c4 CL	65	irq = vec >> 26;
	66	v_bit = 0x80000000UL >> irq;
	67
	68	/*
	69	* Read Interrupt Mask Register and Mask Interrupts
	70	*/
ba3da734 CL	71	simask = in_be32(&immr->im_siu_conf.sc_simask);
ba3da734 CL	72	clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
907208c4 CL	73
	74	if (!(irq & 0x1)) { /* External Interrupt ? */
	75	ulong siel;
	76
	77	/*
	78	* Read Interrupt Edge/Level Register
	79	*/
ba3da734	80	siel = in_be32(&immr->im_siu_conf.sc_siel);
907208c4 CL	81
	82	if (siel & v_bit) { /* edge triggered interrupt ? */
	83	/*
	84	* Rewrite SIPEND Register to clear interrupt
	85	*/
ba3da734	86	out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
907208c4 CL	87	}
	88	}
	89
	90	if (irq_vecs[irq].handler != NULL) {
70fd0710	91	irq_vecs[irq].handler(irq_vecs[irq].arg);
907208c4	92	} else {
70fd0710 CL	93	printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
70fd0710 CL	94	irq, vec);
907208c4 CL	95	/* turn off the bogus interrupt to avoid it from now */
	96	simask &= ~v_bit;
	97	}
	98	/*
	99	* Re-Enable old Interrupt Mask
	100	*/
ba3da734	101	out_be32(&immr->im_siu_conf.sc_simask, simask);
907208c4 CL	102	}
	103
	104	/************************************************************************/
	105
	106	/*
	107	* CPM interrupt handler
	108	*/
70fd0710	109	static void cpm_interrupt(void *regs)
907208c4	110	{
ba3da734	111	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
907208c4 CL	112	uint vec;
	113
	114	/*
	115	* Get the vector by setting the ACK bit
	116	* and then reading the register.
	117	*/
ba3da734 CL	118	out_be16(&immr->im_cpic.cpic_civr, 1);
ba3da734 CL	119	vec = in_be16(&immr->im_cpic.cpic_civr);
907208c4 CL	120	vec >>= 11;
	121
	122	if (cpm_vecs[vec].handler != NULL) {
	123	(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
	124	} else {
ba3da734	125	clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
70fd0710	126	printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
907208c4 CL	127	}
	128	/*
	129	* After servicing the interrupt,
	130	* we have to remove the status indicator.
	131	*/
ba3da734	132	setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
907208c4 CL	133	}
	134
	135	/*
	136	* The CPM can generate the error interrupt when there is a race
	137	* condition between generating and masking interrupts. All we have
	138	* to do is ACK it and return. This is a no-op function so we don't
	139	* need any special tests in the interrupt handler.
	140	*/
70fd0710	141	static void cpm_error_interrupt(void *dummy)
907208c4 CL	142	{
	143	}
	144
	145	/************************************************************************/
	146	/*
	147	* Install and free an interrupt handler
	148	*/
70fd0710	149	void irq_install_handler(int vec, interrupt_handler_t handler, void arg)
907208c4	150	{
ba3da734	151	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
907208c4 CL	152
	153	if ((vec & CPMVEC_OFFSET) != 0) {
	154	/* CPM interrupt */
	155	vec &= 0xffff;
70fd0710 CL	156	if (cpm_vecs[vec].handler != NULL)
	157	printf("CPM interrupt 0x%x replacing 0x%x\n",
	158	(uint)handler, (uint)cpm_vecs[vec].handler);
907208c4 CL	159	cpm_vecs[vec].handler = handler;
907208c4 CL	160	cpm_vecs[vec].arg = arg;
ba3da734	161	setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
907208c4 CL	162	} else {
907208c4 CL	163	/* SIU interrupt */
70fd0710 CL	164	if (irq_vecs[vec].handler != NULL)
	165	printf("SIU interrupt %d 0x%x replacing 0x%x\n",
	166	vec, (uint)handler, (uint)cpm_vecs[vec].handler);
907208c4 CL	167	irq_vecs[vec].handler = handler;
907208c4 CL	168	irq_vecs[vec].arg = arg;
ba3da734	169	setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
907208c4 CL	170	}
	171	}
	172
70fd0710	173	void irq_free_handler(int vec)
907208c4	174	{
ba3da734	175	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
907208c4 CL	176
	177	if ((vec & CPMVEC_OFFSET) != 0) {
	178	/* CPM interrupt */
	179	vec &= 0xffff;
ba3da734	180	clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
907208c4 CL	181	cpm_vecs[vec].handler = NULL;
	182	cpm_vecs[vec].arg = NULL;
	183	} else {
	184	/* SIU interrupt */
ba3da734	185	clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
907208c4 CL	186	irq_vecs[vec].handler = NULL;
	187	irq_vecs[vec].arg = NULL;
	188	}
	189	}
	190
	191	/************************************************************************/
	192
70fd0710	193	static void cpm_interrupt_init(void)
907208c4	194	{
ba3da734 CL	195	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
ba3da734 CL	196	uint cicr;
907208c4 CL	197
	198	/*
	199	* Initialize the CPM interrupt controller.
	200	*/
	201
ba3da734 CL	202	cicr = CICR_SCD_SCC4 \| CICR_SCC_SCC3 \| CICR_SCB_SCC2 \| CICR_SCA_SCC1 \|
ba3da734 CL	203	((CPM_INTERRUPT / 2) << 13) \| CICR_HP_MASK;
907208c4	204
ba3da734 CL	205	out_be32(&immr->im_cpic.cpic_cicr, cicr);
ba3da734 CL	206	out_be32(&immr->im_cpic.cpic_cimr, 0);
907208c4 CL	207
	208	/*
	209	* Install the error handler.
	210	*/
70fd0710	211	irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
907208c4	212
ba3da734	213	setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
907208c4 CL	214
	215	/*
	216	* Install the cpm interrupt handler
	217	*/
70fd0710	218	irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
907208c4 CL	219	}
	220
	221	/************************************************************************/
	222
	223	/*
	224	* timer_interrupt - gets called when the decrementer overflows,
	225	* with interrupts disabled.
	226	* Trivial implementation - no need to be really accurate.
	227	*/
70fd0710	228	void timer_interrupt_cpu(struct pt_regs *regs)
907208c4	229	{
ba3da734	230	immap_t __iomem immr = (immap_t __iomem )CONFIG_SYS_IMMR;
907208c4 CL	231
907208c4 CL	232	/* Reset Timer Expired and Timers Interrupt Status */
ba3da734	233	out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
907208c4 CL	234	__asm__ ("nop");
	235	/*
	236	Clear TEXPS (and TMIST on older chips). SPLSS (on older
	237	chips) is cleared too.
	238
	239	Bitwise OR is a read-modify-write operation so ALL bits
	240	which are cleared by writing `1' would be cleared by
	241	operations like
	242
	243	immr->im_clkrst.car_plprcr \|= PLPRCR_TEXPS;
	244
	245	The same can be achieved by simple writing of the PLPRCR
	246	to itself. If a bit value should be preserved, read the
	247	register, ZERO the bit and write, not OR, the result back.
	248	*/
ba3da734	249	setbits_be32(&immr->im_clkrst.car_plprcr, 0);
907208c4 CL	250	}
	251
	252	/************************************************************************/