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5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2001-2002 | |
3 | * Wolfgang Denk, DENX Software Engineering -- wd@denx.de | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /************************************************************************/ | |
25 | /* ** HEADER FILES */ | |
26 | /************************************************************************/ | |
27 | ||
8564acf9 WD |
28 | /* #define DEBUG */ |
29 | ||
5b1d7137 WD |
30 | #include <config.h> |
31 | #include <common.h> | |
c3f4d17e | 32 | #include <command.h> |
7aa78614 | 33 | #include <watchdog.h> |
5b1d7137 WD |
34 | #include <version.h> |
35 | #include <stdarg.h> | |
36 | #include <lcdvideo.h> | |
37 | #include <linux/types.h> | |
52cb4d4f | 38 | #include <stdio_dev.h> |
4532cb69 WD |
39 | #if defined(CONFIG_POST) |
40 | #include <post.h> | |
41 | #endif | |
682011ff | 42 | #include <lcd.h> |
5b1d7137 WD |
43 | |
44 | #ifdef CONFIG_LCD | |
45 | ||
46 | /************************************************************************/ | |
47 | /* ** CONFIG STUFF -- should be moved to board config file */ | |
48 | /************************************************************************/ | |
88804d19 WD |
49 | #ifndef CONFIG_LCD_INFO |
50 | #define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ | |
51 | #endif | |
608c9146 | 52 | |
d791b1dc | 53 | #if defined(CONFIG_V37) || defined(CONFIG_EDT32F10) |
608c9146 | 54 | #undef CONFIG_LCD_LOGO |
88804d19 | 55 | #undef CONFIG_LCD_INFO |
608c9146 WD |
56 | #endif |
57 | ||
5b1d7137 WD |
58 | /*----------------------------------------------------------------------*/ |
59 | #ifdef CONFIG_KYOCERA_KCS057QV1AJ | |
60 | /* | |
61 | * Kyocera KCS057QV1AJ-G23. Passive, color, single scan. | |
62 | */ | |
63 | #define LCD_BPP LCD_COLOR4 | |
64 | ||
8655b6f8 | 65 | vidinfo_t panel_info = { |
6d0f6bcf | 66 | 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, |
5b1d7137 WD |
67 | LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 |
68 | /* wbl, vpw, lcdac, wbf */ | |
69 | }; | |
70 | #endif /* CONFIG_KYOCERA_KCS057QV1AJ */ | |
71 | /*----------------------------------------------------------------------*/ | |
72 | ||
682011ff WD |
73 | /*----------------------------------------------------------------------*/ |
74 | #ifdef CONFIG_HITACHI_SP19X001_Z1A | |
75 | /* | |
76 | * Hitachi SP19X001-. Active, color, single scan. | |
77 | */ | |
8655b6f8 | 78 | vidinfo_t panel_info = { |
6d0f6bcf | 79 | 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, |
682011ff WD |
80 | LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 |
81 | /* wbl, vpw, lcdac, wbf */ | |
82 | }; | |
83 | #endif /* CONFIG_HITACHI_SP19X001_Z1A */ | |
84 | /*----------------------------------------------------------------------*/ | |
85 | ||
5b1d7137 | 86 | /*----------------------------------------------------------------------*/ |
fd3103bb | 87 | #ifdef CONFIG_NEC_NL6448AC33 |
5b1d7137 | 88 | /* |
fd3103bb | 89 | * NEC NL6448AC33-18. Active, color, single scan. |
5b1d7137 | 90 | */ |
8655b6f8 | 91 | vidinfo_t panel_info = { |
6d0f6bcf | 92 | 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, |
5b1d7137 WD |
93 | 3, 0, 0, 1, 1, 144, 2, 0, 33 |
94 | /* wbl, vpw, lcdac, wbf */ | |
95 | }; | |
fd3103bb | 96 | #endif /* CONFIG_NEC_NL6448AC33 */ |
5b1d7137 WD |
97 | /*----------------------------------------------------------------------*/ |
98 | ||
fd3103bb | 99 | #ifdef CONFIG_NEC_NL6448BC20 |
5b1d7137 | 100 | /* |
fd3103bb | 101 | * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. |
5b1d7137 | 102 | */ |
8655b6f8 | 103 | vidinfo_t panel_info = { |
6d0f6bcf | 104 | 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, |
5b1d7137 WD |
105 | 3, 0, 0, 1, 1, 144, 2, 0, 33 |
106 | /* wbl, vpw, lcdac, wbf */ | |
107 | }; | |
fd3103bb WD |
108 | #endif /* CONFIG_NEC_NL6448BC20 */ |
109 | /*----------------------------------------------------------------------*/ | |
110 | ||
111 | #ifdef CONFIG_NEC_NL6448BC33_54 | |
112 | /* | |
113 | * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. | |
114 | */ | |
8655b6f8 | 115 | vidinfo_t panel_info = { |
6d0f6bcf | 116 | 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, |
fd3103bb WD |
117 | 3, 0, 0, 1, 1, 144, 2, 0, 33 |
118 | /* wbl, vpw, lcdac, wbf */ | |
119 | }; | |
120 | #endif /* CONFIG_NEC_NL6448BC33_54 */ | |
5b1d7137 WD |
121 | /*----------------------------------------------------------------------*/ |
122 | ||
123 | #ifdef CONFIG_SHARP_LQ104V7DS01 | |
124 | /* | |
125 | * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. | |
126 | */ | |
8655b6f8 | 127 | vidinfo_t panel_info = { |
6d0f6bcf | 128 | 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, |
5b1d7137 WD |
129 | 3, 0, 0, 1, 1, 25, 1, 0, 33 |
130 | /* wbl, vpw, lcdac, wbf */ | |
131 | }; | |
132 | #endif /* CONFIG_SHARP_LQ104V7DS01 */ | |
133 | /*----------------------------------------------------------------------*/ | |
134 | ||
135 | #ifdef CONFIG_SHARP_16x9 | |
136 | /* | |
137 | * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am | |
138 | * not sure what it is....... | |
139 | */ | |
8655b6f8 | 140 | vidinfo_t panel_info = { |
6d0f6bcf | 141 | 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, |
5b1d7137 WD |
142 | 3, 0, 0, 1, 1, 15, 4, 0, 3 |
143 | }; | |
144 | #endif /* CONFIG_SHARP_16x9 */ | |
145 | /*----------------------------------------------------------------------*/ | |
146 | ||
147 | #ifdef CONFIG_SHARP_LQ057Q3DC02 | |
148 | /* | |
149 | * Sharp LQ057Q3DC02 display. Active, color, single scan. | |
150 | */ | |
8655b6f8 | 151 | #undef LCD_DF |
4a6fd34b WD |
152 | #define LCD_DF 12 |
153 | ||
8655b6f8 | 154 | vidinfo_t panel_info = { |
6d0f6bcf | 155 | 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, |
5b1d7137 WD |
156 | 3, 0, 0, 1, 1, 15, 4, 0, 3 |
157 | /* wbl, vpw, lcdac, wbf */ | |
158 | }; | |
88804d19 | 159 | #define CONFIG_LCD_INFO_BELOW_LOGO |
5b1d7137 WD |
160 | #endif /* CONFIG_SHARP_LQ057Q3DC02 */ |
161 | /*----------------------------------------------------------------------*/ | |
162 | ||
163 | #ifdef CONFIG_SHARP_LQ64D341 | |
164 | /* | |
165 | * Sharp LQ64D341 display, 640x480. Active, color, single scan. | |
166 | */ | |
8655b6f8 | 167 | vidinfo_t panel_info = { |
6d0f6bcf | 168 | 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, |
5b1d7137 WD |
169 | 3, 0, 0, 1, 1, 128, 16, 0, 32 |
170 | /* wbl, vpw, lcdac, wbf */ | |
171 | }; | |
172 | #endif /* CONFIG_SHARP_LQ64D341 */ | |
608c9146 | 173 | |
29127b6a | 174 | #ifdef CONFIG_SHARP_LQ065T9DR51U |
175 | /* | |
176 | * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. | |
177 | */ | |
8655b6f8 | 178 | vidinfo_t panel_info = { |
6d0f6bcf | 179 | 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, |
29127b6a | 180 | 3, 0, 0, 1, 1, 248, 4, 0, 35 |
181 | /* wbl, vpw, lcdac, wbf */ | |
182 | }; | |
88804d19 | 183 | #define CONFIG_LCD_INFO_BELOW_LOGO |
29127b6a | 184 | #endif /* CONFIG_SHARP_LQ065T9DR51U */ |
185 | ||
608c9146 WD |
186 | #ifdef CONFIG_SHARP_LQ084V1DG21 |
187 | /* | |
188 | * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. | |
189 | */ | |
8655b6f8 | 190 | vidinfo_t panel_info = { |
6d0f6bcf | 191 | 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, |
608c9146 WD |
192 | 3, 0, 0, 1, 1, 160, 3, 0, 48 |
193 | /* wbl, vpw, lcdac, wbf */ | |
194 | }; | |
195 | #endif /* CONFIG_SHARP_LQ084V1DG21 */ | |
196 | ||
5b1d7137 WD |
197 | /*----------------------------------------------------------------------*/ |
198 | ||
199 | #ifdef CONFIG_HLD1045 | |
200 | /* | |
201 | * HLD1045 display, 640x480. Active, color, single scan. | |
202 | */ | |
8655b6f8 | 203 | vidinfo_t panel_info = { |
6d0f6bcf | 204 | 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, |
5b1d7137 WD |
205 | 3, 0, 0, 1, 1, 160, 3, 0, 48 |
206 | /* wbl, vpw, lcdac, wbf */ | |
207 | }; | |
208 | #endif /* CONFIG_HLD1045 */ | |
209 | /*----------------------------------------------------------------------*/ | |
210 | ||
211 | #ifdef CONFIG_PRIMEVIEW_V16C6448AC | |
212 | /* | |
213 | * Prime View V16C6448AC | |
214 | */ | |
8655b6f8 | 215 | vidinfo_t panel_info = { |
6d0f6bcf | 216 | 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, |
5b1d7137 WD |
217 | 3, 0, 0, 1, 1, 144, 2, 0, 35 |
218 | /* wbl, vpw, lcdac, wbf */ | |
219 | }; | |
220 | #endif /* CONFIG_PRIMEVIEW_V16C6448AC */ | |
221 | ||
222 | /*----------------------------------------------------------------------*/ | |
223 | ||
224 | #ifdef CONFIG_OPTREX_BW | |
225 | /* | |
226 | * Optrex CBL50840-2 NF-FW 99 22 M5 | |
227 | * or | |
228 | * Hitachi LMG6912RPFC-00T | |
229 | * or | |
230 | * Hitachi SP14Q002 | |
231 | * | |
232 | * 320x240. Black & white. | |
233 | */ | |
234 | #define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */ | |
235 | /* 1 - 4 grey levels, 2 bpp */ | |
236 | /* 2 - 16 grey levels, 4 bpp */ | |
8655b6f8 | 237 | vidinfo_t panel_info = { |
6d0f6bcf | 238 | 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, |
5b1d7137 WD |
239 | OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 |
240 | }; | |
241 | #endif /* CONFIG_OPTREX_BW */ | |
242 | ||
243 | /*-----------------------------------------------------------------*/ | |
244 | #ifdef CONFIG_EDT32F10 | |
245 | /* | |
246 | * Emerging Display Technologies 320x240. Passive, monochrome, single scan. | |
247 | */ | |
248 | #define LCD_BPP LCD_MONOCHROME | |
4a6fd34b | 249 | #define LCD_DF 10 |
5b1d7137 | 250 | |
8655b6f8 | 251 | vidinfo_t panel_info = { |
6d0f6bcf | 252 | 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, |
4a6fd34b | 253 | LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 |
5b1d7137 WD |
254 | }; |
255 | #endif | |
256 | /*----------------------------------------------------------------------*/ | |
257 | ||
5b1d7137 | 258 | |
8655b6f8 | 259 | int lcd_line_length; |
5b1d7137 | 260 | |
5b1d7137 WD |
261 | /* |
262 | * Frame buffer memory information | |
263 | */ | |
8655b6f8 WD |
264 | void *lcd_base; /* Start of framebuffer memory */ |
265 | void *lcd_console_address; /* Start of console buffer */ | |
5b1d7137 | 266 | |
8655b6f8 WD |
267 | short console_col; |
268 | short console_row; | |
5b1d7137 WD |
269 | |
270 | /************************************************************************/ | |
271 | ||
8655b6f8 WD |
272 | void lcd_ctrl_init (void *lcdbase); |
273 | void lcd_enable (void); | |
5b1d7137 | 274 | #if LCD_BPP == LCD_COLOR8 |
8655b6f8 | 275 | void lcd_setcolreg (ushort regno, |
5b1d7137 WD |
276 | ushort red, ushort green, ushort blue); |
277 | #endif | |
278 | #if LCD_BPP == LCD_MONOCHROME | |
8655b6f8 | 279 | void lcd_initcolregs (void); |
5b1d7137 | 280 | #endif |
5b1d7137 | 281 | |
682011ff | 282 | #if defined(CONFIG_RBC823) |
8655b6f8 | 283 | void lcd_disable (void); |
682011ff WD |
284 | #endif |
285 | ||
5b1d7137 | 286 | /************************************************************************/ |
5b1d7137 WD |
287 | |
288 | /************************************************************************/ | |
8655b6f8 | 289 | /* ----------------- chipset specific functions ----------------------- */ |
5b1d7137 WD |
290 | /************************************************************************/ |
291 | ||
292 | /* | |
8655b6f8 | 293 | * Calculate fb size for VIDEOLFB_ATAG. |
5b1d7137 | 294 | */ |
8655b6f8 | 295 | ulong calc_fbsize (void) |
5b1d7137 WD |
296 | { |
297 | ulong size; | |
298 | int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; | |
299 | ||
5b1d7137 WD |
300 | size = line_length * panel_info.vl_row; |
301 | ||
8655b6f8 | 302 | return size; |
5b1d7137 WD |
303 | } |
304 | ||
8655b6f8 | 305 | void lcd_ctrl_init (void *lcdbase) |
5b1d7137 | 306 | { |
6d0f6bcf | 307 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
5b1d7137 WD |
308 | volatile lcd823_t *lcdp = &immr->im_lcd; |
309 | ||
310 | uint lccrtmp; | |
682011ff | 311 | uint lchcr_hpc_tmp; |
5b1d7137 WD |
312 | |
313 | /* Initialize the LCD control register according to the LCD | |
314 | * parameters defined. We do everything here but enable | |
315 | * the controller. | |
316 | */ | |
317 | ||
e63c8ee3 WD |
318 | #ifdef CONFIG_RPXLITE |
319 | /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ | |
6d0f6bcf | 320 | panel_info.vl_dp = CONFIG_SYS_LOW; |
e63c8ee3 WD |
321 | #endif |
322 | ||
5b1d7137 WD |
323 | lccrtmp = LCDBIT (LCCR_BNUM_BIT, |
324 | (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); | |
325 | ||
326 | lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) | | |
327 | LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) | | |
328 | LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) | | |
329 | LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) | | |
330 | LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) | | |
331 | LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) | | |
332 | LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) | | |
333 | LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) | | |
334 | LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) | | |
335 | LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft); | |
336 | ||
337 | #if 0 | |
338 | lccrtmp |= ((SIU_LEVEL5 / 2) << 12); | |
339 | lccrtmp |= LCCR_EIEN; | |
340 | #endif | |
341 | ||
342 | lcdp->lcd_lccr = lccrtmp; | |
343 | lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */ | |
344 | ||
345 | /* Initialize LCD controller bus priorities. | |
346 | */ | |
682011ff WD |
347 | #ifdef CONFIG_RBC823 |
348 | immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */ | |
349 | #else | |
5b1d7137 WD |
350 | immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ |
351 | ||
352 | /* set SHFT/CLOCK division factor 4 | |
353 | * This needs to be set based upon display type and processor | |
354 | * speed. The TFT displays run about 20 to 30 MHz. | |
355 | * I was running 64 MHz processor speed. | |
356 | * The value for this divider must be chosen so the result is | |
357 | * an integer of the processor speed (i.e., divide by 3 with | |
358 | * 64 MHz would be bad). | |
359 | */ | |
360 | immr->im_clkrst.car_sccr &= ~0x1F; | |
361 | immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ | |
362 | ||
682011ff WD |
363 | #endif /* CONFIG_RBC823 */ |
364 | ||
365 | #if defined(CONFIG_RBC823) | |
366 | /* Enable LCD on port D. | |
367 | */ | |
368 | immr->im_ioport.iop_pddat &= 0x0300; | |
369 | immr->im_ioport.iop_pdpar |= 0x1CFF; | |
370 | immr->im_ioport.iop_pddir |= 0x1CFF; | |
371 | ||
372 | /* Configure LCD_ON, VEE_ON, CCFL_ON on port B. | |
373 | */ | |
374 | immr->im_cpm.cp_pbdat &= ~0x00005001; | |
375 | immr->im_cpm.cp_pbpar &= ~0x00005001; | |
376 | immr->im_cpm.cp_pbdir |= 0x00005001; | |
377 | #elif !defined(CONFIG_EDT32F10) | |
5b1d7137 WD |
378 | /* Enable LCD on port D. |
379 | */ | |
380 | immr->im_ioport.iop_pdpar |= 0x1FFF; | |
381 | immr->im_ioport.iop_pddir |= 0x1FFF; | |
382 | ||
383 | /* Enable LCD_A/B/C on port B. | |
384 | */ | |
385 | immr->im_cpm.cp_pbpar |= 0x00005001; | |
386 | immr->im_cpm.cp_pbdir |= 0x00005001; | |
387 | #else | |
388 | /* Enable LCD on port D. | |
389 | */ | |
390 | immr->im_ioport.iop_pdpar |= 0x1DFF; | |
391 | immr->im_ioport.iop_pdpar &= ~0x0200; | |
392 | immr->im_ioport.iop_pddir |= 0x1FFF; | |
393 | immr->im_ioport.iop_pddat |= 0x0200; | |
394 | #endif | |
395 | ||
396 | /* Load the physical address of the linear frame buffer | |
397 | * into the LCD controller. | |
398 | * BIG NOTE: This has to be modified to load A and B depending | |
399 | * upon the split mode of the LCD. | |
400 | */ | |
401 | lcdp->lcd_lcfaa = (ulong)lcd_base; | |
402 | lcdp->lcd_lcfba = (ulong)lcd_base; | |
403 | ||
404 | /* MORE HACKS...This must be updated according to 823 manual | |
405 | * for different panels. | |
682011ff WD |
406 | * Udi Finkelstein - done - see below: |
407 | * Note: You better not try unsupported combinations such as | |
408 | * 4-bit wide passive dual scan LCD at 4/8 Bit color. | |
5b1d7137 | 409 | */ |
682011ff | 410 | lchcr_hpc_tmp = |
8bde7f77 | 411 | (panel_info.vl_col * |
682011ff WD |
412 | (panel_info.vl_tft ? 8 : |
413 | (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */ | |
414 | /* use << to mult by: single scan = 1, dual scan = 2 */ | |
415 | panel_info.vl_splt) * | |
416 | (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */ | |
417 | ||
5b1d7137 WD |
418 | lcdp->lcd_lchcr = LCHCR_BO | |
419 | LCDBIT (LCHCR_AT_BIT, 4) | | |
682011ff | 420 | LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) | |
5b1d7137 | 421 | panel_info.vl_wbl; |
5b1d7137 WD |
422 | |
423 | lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) | | |
424 | LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) | | |
425 | LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) | | |
426 | panel_info.vl_wbf; | |
427 | ||
428 | } | |
429 | ||
430 | /*----------------------------------------------------------------------*/ | |
431 | ||
432 | #ifdef NOT_USED_SO_FAR | |
433 | static void | |
434 | lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) | |
435 | { | |
6d0f6bcf | 436 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
5b1d7137 WD |
437 | volatile cpm8xx_t *cp = &(immr->im_cpm); |
438 | unsigned short colreg, *cmap_ptr; | |
439 | ||
440 | cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; | |
441 | ||
442 | colreg = *cmap_ptr; | |
6d0f6bcf | 443 | #ifdef CONFIG_SYS_INVERT_COLORS |
5b1d7137 WD |
444 | colreg ^= 0x0FFF; |
445 | #endif | |
446 | ||
447 | *red = (colreg >> 8) & 0x0F; | |
448 | *green = (colreg >> 4) & 0x0F; | |
449 | *blue = colreg & 0x0F; | |
450 | } | |
451 | #endif /* NOT_USED_SO_FAR */ | |
452 | ||
453 | /*----------------------------------------------------------------------*/ | |
454 | ||
455 | #if LCD_BPP == LCD_COLOR8 | |
8655b6f8 | 456 | void |
5b1d7137 WD |
457 | lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) |
458 | { | |
6d0f6bcf | 459 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
5b1d7137 WD |
460 | volatile cpm8xx_t *cp = &(immr->im_cpm); |
461 | unsigned short colreg, *cmap_ptr; | |
462 | ||
463 | cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; | |
464 | ||
465 | colreg = ((red & 0x0F) << 8) | | |
466 | ((green & 0x0F) << 4) | | |
467 | (blue & 0x0F) ; | |
6d0f6bcf | 468 | #ifdef CONFIG_SYS_INVERT_COLORS |
5b1d7137 WD |
469 | colreg ^= 0x0FFF; |
470 | #endif | |
471 | *cmap_ptr = colreg; | |
472 | ||
473 | debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", | |
474 | regno, &(cp->lcd_cmap[regno * 2]), | |
475 | red, green, blue, | |
8bde7f77 | 476 | cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]); |
5b1d7137 WD |
477 | } |
478 | #endif /* LCD_COLOR8 */ | |
479 | ||
480 | /*----------------------------------------------------------------------*/ | |
481 | ||
482 | #if LCD_BPP == LCD_MONOCHROME | |
483 | static | |
484 | void lcd_initcolregs (void) | |
485 | { | |
6d0f6bcf | 486 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
5b1d7137 WD |
487 | volatile cpm8xx_t *cp = &(immr->im_cpm); |
488 | ushort regno; | |
489 | ||
490 | for (regno = 0; regno < 16; regno++) { | |
491 | cp->lcd_cmap[regno * 2] = 0; | |
492 | cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f; | |
493 | } | |
494 | } | |
495 | #endif | |
496 | ||
497 | /*----------------------------------------------------------------------*/ | |
498 | ||
8655b6f8 | 499 | void lcd_enable (void) |
5b1d7137 | 500 | { |
6d0f6bcf | 501 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
5b1d7137 WD |
502 | volatile lcd823_t *lcdp = &immr->im_lcd; |
503 | ||
504 | /* Enable the LCD panel */ | |
682011ff | 505 | #ifndef CONFIG_RBC823 |
5b1d7137 | 506 | immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ |
682011ff | 507 | #endif |
5b1d7137 | 508 | lcdp->lcd_lccr |= LCCR_PON; |
608c9146 WD |
509 | |
510 | #ifdef CONFIG_V37 | |
511 | /* Turn on display backlight */ | |
512 | immr->im_cpm.cp_pbpar |= 0x00008000; | |
513 | immr->im_cpm.cp_pbdir |= 0x00008000; | |
682011ff WD |
514 | #elif defined(CONFIG_RBC823) |
515 | /* Turn on display backlight */ | |
516 | immr->im_cpm.cp_pbdat |= 0x00004000; | |
608c9146 WD |
517 | #endif |
518 | ||
5b1d7137 WD |
519 | #if defined(CONFIG_LWMON) |
520 | { uchar c = pic_read (0x60); | |
6d0f6bcf | 521 | #if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON) |
7d7ce412 | 522 | /* Enable LCD later in sysmon test, only if temperature is OK */ |
4532cb69 | 523 | #else |
8bde7f77 | 524 | c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ |
4532cb69 | 525 | #endif |
5b1d7137 WD |
526 | pic_write (0x60, c); |
527 | } | |
4a6fd34b WD |
528 | #endif /* CONFIG_LWMON */ |
529 | ||
530 | #if defined(CONFIG_R360MPI) | |
5b1d7137 | 531 | { |
4a6fd34b | 532 | extern void r360_i2c_lcd_write (uchar data0, uchar data1); |
cb4dbb7b WD |
533 | unsigned long bgi, ctr; |
534 | char *p; | |
535 | ||
536 | if ((p = getenv("lcdbgi")) != NULL) { | |
537 | bgi = simple_strtoul (p, 0, 10) & 0xFFF; | |
538 | } else { | |
539 | bgi = 0xFFF; | |
540 | } | |
541 | ||
542 | if ((p = getenv("lcdctr")) != NULL) { | |
543 | ctr = simple_strtoul (p, 0, 10) & 0xFFF; | |
544 | } else { | |
545 | ctr=0x7FF; | |
546 | } | |
5b1d7137 | 547 | |
4a6fd34b WD |
548 | r360_i2c_lcd_write(0x10, 0x01); |
549 | r360_i2c_lcd_write(0x20, 0x01); | |
cb4dbb7b WD |
550 | r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF); |
551 | r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); | |
5b1d7137 | 552 | } |
4a6fd34b | 553 | #endif /* CONFIG_R360MPI */ |
682011ff WD |
554 | #ifdef CONFIG_RBC823 |
555 | udelay(200000); /* wait 200ms */ | |
556 | /* Turn VEE_ON first */ | |
557 | immr->im_cpm.cp_pbdat |= 0x00000001; | |
558 | udelay(200000); /* wait 200ms */ | |
559 | /* Now turn on LCD_ON */ | |
560 | immr->im_cpm.cp_pbdat |= 0x00001000; | |
561 | #endif | |
8564acf9 WD |
562 | #ifdef CONFIG_RRVISION |
563 | debug ("PC4->Output(1): enable LVDS\n"); | |
564 | debug ("PC5->Output(0): disable PAL clock\n"); | |
565 | immr->im_ioport.iop_pddir |= 0x1000; | |
566 | immr->im_ioport.iop_pcpar &= ~(0x0C00); | |
567 | immr->im_ioport.iop_pcdir |= 0x0C00 ; | |
568 | immr->im_ioport.iop_pcdat |= 0x0800 ; | |
569 | immr->im_ioport.iop_pcdat &= ~(0x0400); | |
570 | debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", | |
571 | immr->im_ioport.iop_pdpar, | |
572 | immr->im_ioport.iop_pddir, | |
573 | immr->im_ioport.iop_pddat); | |
574 | debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", | |
575 | immr->im_ioport.iop_pcpar, | |
576 | immr->im_ioport.iop_pcdir, | |
577 | immr->im_ioport.iop_pcdat); | |
578 | #endif | |
5b1d7137 WD |
579 | } |
580 | ||
581 | /*----------------------------------------------------------------------*/ | |
582 | ||
682011ff WD |
583 | #if defined (CONFIG_RBC823) |
584 | void lcd_disable (void) | |
5b1d7137 | 585 | { |
6d0f6bcf | 586 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
5b1d7137 WD |
587 | volatile lcd823_t *lcdp = &immr->im_lcd; |
588 | ||
589 | #if defined(CONFIG_LWMON) | |
590 | { uchar c = pic_read (0x60); | |
8bde7f77 | 591 | c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */ |
5b1d7137 WD |
592 | pic_write (0x60, c); |
593 | } | |
594 | #elif defined(CONFIG_R360MPI) | |
595 | { | |
4a6fd34b | 596 | extern void r360_i2c_lcd_write (uchar data0, uchar data1); |
5b1d7137 | 597 | |
4a6fd34b WD |
598 | r360_i2c_lcd_write(0x10, 0x00); |
599 | r360_i2c_lcd_write(0x20, 0x00); | |
600 | r360_i2c_lcd_write(0x30, 0x00); | |
601 | r360_i2c_lcd_write(0x40, 0x00); | |
5b1d7137 WD |
602 | } |
603 | #endif /* CONFIG_LWMON */ | |
604 | /* Disable the LCD panel */ | |
605 | lcdp->lcd_lccr &= ~LCCR_PON; | |
682011ff WD |
606 | #ifdef CONFIG_RBC823 |
607 | /* Turn off display backlight, VEE and LCD_ON */ | |
608 | immr->im_cpm.cp_pbdat &= ~0x00005001; | |
609 | #else | |
5b1d7137 | 610 | immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */ |
682011ff | 611 | #endif /* CONFIG_RBC823 */ |
5b1d7137 | 612 | } |
682011ff | 613 | #endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */ |
5b1d7137 WD |
614 | |
615 | ||
5b1d7137 WD |
616 | /************************************************************************/ |
617 | ||
618 | #endif /* CONFIG_LCD */ |