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ed247f48 WD |
1 | /* |
2 | * File: scc.c | |
3 | * Description: | |
53677ef1 | 4 | * Basic ET HW initialization and packet RX/TX routines |
ed247f48 WD |
5 | * |
6 | * NOTE <<<IMPORTANT: PLEASE READ>>>: | |
7 | * Do not cache Rx/Tx buffers! | |
8 | */ | |
9 | ||
10 | /* | |
11 | * MPC823 <-> MC68160 Connections: | |
12 | * | |
13 | * Setup MPC823 to work with MC68160 Enhanced Ethernet | |
14 | * Serial Tranceiver as follows: | |
15 | * | |
16 | * MPC823 Signal MC68160 Comments | |
17 | * ------ ------ ------- -------- | |
18 | * PA-12 ETHTX --------> TX Eth. Port Transmit Data | |
19 | * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable | |
20 | * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock | |
21 | * PA-13 ETHRX <-------- RX Eth. Port Receive Data | |
22 | * PC-8 E_RENA <-------- RENA Eth. Receive Enable | |
23 | * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock | |
24 | * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication | |
25 | * | |
26 | * FADS Board Signal MC68160 Comments | |
27 | * ----------------- ------- -------- | |
28 | * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable | |
29 | * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable | |
30 | * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex | |
31 | * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <common.h> | |
36 | #include <malloc.h> | |
37 | #include <commproc.h> | |
38 | #include <net.h> | |
39 | #include <command.h> | |
40 | ||
4431283c | 41 | #if defined(CONFIG_CMD_NET) && defined(SCC_ENET) |
ed247f48 WD |
42 | |
43 | /* Ethernet Transmit and Receive Buffers */ | |
44 | #define DBUF_LENGTH 1520 | |
45 | ||
46 | #define TX_BUF_CNT 2 | |
47 | ||
2729af9d | 48 | #define TOUT_LOOP 10000 /* 10 ms to have a packet sent */ |
ed247f48 WD |
49 | |
50 | static char txbuf[DBUF_LENGTH]; | |
51 | ||
52 | static uint rxIdx; /* index of the current RX buffer */ | |
53 | static uint txIdx; /* index of the current TX buffer */ | |
54 | ||
55 | /* | |
56 | * SCC Ethernet Tx and Rx buffer descriptors allocated at the | |
57 | * immr->udata_bd address on Dual-Port RAM | |
58 | * Provide for Double Buffering | |
59 | */ | |
60 | ||
61 | typedef volatile struct CommonBufferDescriptor { | |
62 | cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ | |
63 | cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ | |
64 | } RTXBD; | |
65 | ||
66 | static RTXBD *rtx; | |
67 | ||
1b10d071 | 68 | static int scc_send(struct eth_device *dev, void *packet, int length); |
ed247f48 WD |
69 | static int scc_recv(struct eth_device* dev); |
70 | static int scc_init (struct eth_device* dev, bd_t * bd); | |
71 | static void scc_halt(struct eth_device* dev); | |
72 | ||
73 | int scc_initialize(bd_t *bis) | |
74 | { | |
75 | struct eth_device* dev; | |
76 | ||
77 | dev = (struct eth_device*) malloc(sizeof *dev); | |
7f6c2cbc | 78 | memset(dev, 0, sizeof *dev); |
ed247f48 | 79 | |
192bc694 | 80 | strcpy(dev->name, "SCC"); |
ed247f48 WD |
81 | dev->iobase = 0; |
82 | dev->priv = 0; | |
83 | dev->init = scc_init; | |
84 | dev->halt = scc_halt; | |
85 | dev->send = scc_send; | |
86 | dev->recv = scc_recv; | |
87 | ||
88 | eth_register(dev); | |
89 | ||
90 | return 1; | |
91 | } | |
92 | ||
1b10d071 | 93 | static int scc_send(struct eth_device *dev, void *packet, int length) |
ed247f48 WD |
94 | { |
95 | int i, j=0; | |
96 | #if 0 | |
97 | volatile char *in, *out; | |
98 | #endif | |
99 | ||
100 | /* section 16.9.23.3 | |
101 | * Wait for ready | |
102 | */ | |
103 | #if 0 | |
104 | while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY); | |
105 | out = (char *)(rtx->txbd[txIdx].cbd_bufaddr); | |
106 | in = packet; | |
107 | for(i = 0; i < length; i++) { | |
108 | *out++ = *in++; | |
109 | } | |
110 | rtx->txbd[txIdx].cbd_datlen = length; | |
111 | rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST); | |
112 | while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++; | |
113 | ||
114 | #ifdef ET_DEBUG | |
115 | printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); | |
116 | #endif | |
117 | i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; | |
118 | ||
119 | /* wrap around buffer index when necessary */ | |
120 | if (txIdx >= TX_BUF_CNT) txIdx = 0; | |
121 | #endif | |
122 | ||
123 | while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { | |
124 | udelay (1); /* will also trigger Wd if needed */ | |
125 | j++; | |
126 | } | |
127 | if (j>=TOUT_LOOP) printf("TX not ready\n"); | |
128 | rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; | |
129 | rtx->txbd[txIdx].cbd_datlen = length; | |
130 | rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP); | |
131 | while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { | |
132 | udelay (1); /* will also trigger Wd if needed */ | |
133 | j++; | |
134 | } | |
135 | if (j>=TOUT_LOOP) printf("TX timeout\n"); | |
136 | #ifdef ET_DEBUG | |
137 | printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); | |
138 | #endif | |
139 | i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; | |
140 | return i; | |
141 | } | |
142 | ||
3bbc899f | 143 | static int scc_recv (struct eth_device *dev) |
ed247f48 WD |
144 | { |
145 | int length; | |
146 | ||
3bbc899f WD |
147 | for (;;) { |
148 | /* section 16.9.23.2 */ | |
149 | if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { | |
150 | length = -1; | |
151 | break; /* nothing received - leave for() loop */ | |
152 | } | |
ed247f48 | 153 | |
3bbc899f | 154 | length = rtx->rxbd[rxIdx].cbd_datlen; |
ed247f48 | 155 | |
3bbc899f | 156 | if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { |
ed247f48 | 157 | #ifdef ET_DEBUG |
3bbc899f | 158 | printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); |
ed247f48 | 159 | #endif |
3bbc899f WD |
160 | } else { |
161 | /* Pass the packet up to the protocol layers. */ | |
1fd92db8 JH |
162 | net_process_received_packet(net_rx_packets[rxIdx], |
163 | length - 4); | |
3bbc899f WD |
164 | } |
165 | ||
166 | ||
167 | /* Give the buffer back to the SCC. */ | |
168 | rtx->rxbd[rxIdx].cbd_datlen = 0; | |
169 | ||
170 | /* wrap around buffer index when necessary */ | |
171 | if ((rxIdx + 1) >= PKTBUFSRX) { | |
172 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc = | |
173 | (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); | |
174 | rxIdx = 0; | |
175 | } else { | |
176 | rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; | |
177 | rxIdx++; | |
178 | } | |
ed247f48 | 179 | } |
3bbc899f | 180 | return length; |
ed247f48 WD |
181 | } |
182 | ||
183 | /************************************************************** | |
184 | * | |
185 | * SCC Ethernet Initialization Routine | |
186 | * | |
187 | *************************************************************/ | |
188 | ||
3bbc899f | 189 | static int scc_init (struct eth_device *dev, bd_t * bis) |
ed247f48 WD |
190 | { |
191 | ||
3bbc899f WD |
192 | int i; |
193 | scc_enet_t *pram_ptr; | |
ed247f48 | 194 | |
6d0f6bcf | 195 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
ed247f48 | 196 | |
3bbc899f | 197 | pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]); |
ed247f48 | 198 | |
3bbc899f WD |
199 | rxIdx = 0; |
200 | txIdx = 0; | |
ed247f48 | 201 | |
5fdc215f | 202 | if (!rtx) { |
6d0f6bcf | 203 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
5fdc215f WD |
204 | rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + |
205 | dpram_alloc_align (sizeof (RTXBD), 8)); | |
ed247f48 | 206 | #else |
5fdc215f WD |
207 | rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); |
208 | #endif | |
209 | } | |
ed247f48 WD |
210 | |
211 | #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) | |
3bbc899f WD |
212 | /* Configure port A pins for Txd and Rxd. |
213 | */ | |
214 | immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); | |
215 | immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); | |
216 | immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; | |
ed247f48 | 217 | #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) |
3bbc899f WD |
218 | /* Configure port B pins for Txd and Rxd. |
219 | */ | |
220 | immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); | |
221 | immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); | |
222 | immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; | |
ed247f48 WD |
223 | #else |
224 | #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined | |
225 | #endif | |
226 | ||
227 | #if defined(PC_ENET_LBK) | |
3bbc899f WD |
228 | /* Configure port C pins to disable External Loopback |
229 | */ | |
230 | immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; | |
231 | immr->im_ioport.iop_pcdir |= PC_ENET_LBK; | |
232 | immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; | |
233 | immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ | |
234 | #endif /* PC_ENET_LBK */ | |
235 | ||
236 | /* Configure port C pins to enable CLSN and RENA. | |
237 | */ | |
238 | immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); | |
239 | immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); | |
240 | immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); | |
241 | ||
242 | /* Configure port A for TCLK and RCLK. | |
243 | */ | |
244 | immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); | |
245 | immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); | |
246 | ||
247 | /* | |
248 | * Configure Serial Interface clock routing -- see section 16.7.5.3 | |
249 | * First, clear all SCC bits to zero, then set the ones we want. | |
250 | */ | |
251 | ||
252 | immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; | |
253 | immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; | |
254 | ||
255 | ||
256 | /* | |
257 | * Initialize SDCR -- see section 16.9.23.7 | |
258 | * SDMA configuration register | |
259 | */ | |
260 | immr->im_siu_conf.sc_sdcr = 0x01; | |
261 | ||
262 | ||
263 | /* | |
264 | * Setup SCC Ethernet Parameter RAM | |
265 | */ | |
266 | ||
267 | pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ | |
268 | pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ | |
269 | ||
270 | pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ | |
271 | ||
272 | pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ | |
273 | pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ | |
274 | ||
275 | /* | |
276 | * Setup Receiver Buffer Descriptors (13.14.24.18) | |
277 | * Settings: | |
278 | * Empty, Wrap | |
279 | */ | |
280 | ||
281 | for (i = 0; i < PKTBUFSRX; i++) { | |
282 | rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; | |
283 | rtx->rxbd[i].cbd_datlen = 0; /* Reset */ | |
1fd92db8 | 284 | rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; |
3bbc899f WD |
285 | } |
286 | ||
287 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; | |
288 | ||
289 | /* | |
290 | * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) | |
291 | * Settings: | |
292 | * Add PADs to Short FRAMES, Wrap, Last, Tx CRC | |
293 | */ | |
294 | ||
295 | for (i = 0; i < TX_BUF_CNT; i++) { | |
296 | rtx->txbd[i].cbd_sc = | |
297 | (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); | |
298 | rtx->txbd[i].cbd_datlen = 0; /* Reset */ | |
299 | rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); | |
300 | } | |
301 | ||
302 | rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; | |
303 | ||
304 | /* | |
305 | * Enter Command: Initialize Rx Params for SCC | |
306 | */ | |
307 | ||
308 | do { /* Spin until ready to issue command */ | |
309 | __asm__ ("eieio"); | |
310 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); | |
311 | /* Issue command */ | |
312 | immr->im_cpm.cp_cpcr = | |
313 | ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); | |
314 | do { /* Spin until command processed */ | |
315 | __asm__ ("eieio"); | |
316 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); | |
317 | ||
318 | /* | |
319 | * Ethernet Specific Parameter RAM | |
320 | * see table 13-16, pg. 660, | |
321 | * pg. 681 (example with suggested settings) | |
322 | */ | |
323 | ||
324 | pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ | |
325 | pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ | |
326 | pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ | |
327 | pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ | |
328 | pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ | |
329 | pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ | |
330 | ||
331 | pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ | |
332 | pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ | |
333 | pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ | |
334 | ||
335 | pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ | |
336 | pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ | |
337 | ||
338 | pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ | |
339 | pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ | |
340 | pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ | |
341 | pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ | |
ed247f48 | 342 | |
8b2c9a71 | 343 | #define ea eth_get_ethaddr() |
3bbc899f WD |
344 | pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; |
345 | pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; | |
346 | pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; | |
ed247f48 WD |
347 | #undef ea |
348 | ||
3bbc899f WD |
349 | pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ |
350 | pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ | |
351 | pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ | |
352 | pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ | |
353 | pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ | |
354 | pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ | |
355 | pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ | |
356 | pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ | |
357 | ||
358 | /* | |
359 | * Enter Command: Initialize Tx Params for SCC | |
360 | */ | |
361 | ||
362 | do { /* Spin until ready to issue command */ | |
363 | __asm__ ("eieio"); | |
364 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); | |
365 | /* Issue command */ | |
366 | immr->im_cpm.cp_cpcr = | |
367 | ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); | |
368 | do { /* Spin until command processed */ | |
369 | __asm__ ("eieio"); | |
370 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); | |
371 | ||
372 | /* | |
373 | * Mask all Events in SCCM - we use polling mode | |
374 | */ | |
375 | immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0; | |
376 | ||
377 | /* | |
378 | * Clear Events in SCCE -- Clear bits by writing 1's | |
379 | */ | |
380 | ||
381 | immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); | |
382 | ||
383 | ||
384 | /* | |
385 | * Initialize GSMR High 32-Bits | |
386 | * Settings: Normal Mode | |
387 | */ | |
388 | ||
389 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0; | |
390 | ||
391 | /* | |
392 | * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive | |
393 | * Settings: | |
394 | * TCI = Invert | |
395 | * TPL = 48 bits | |
396 | * TPP = Repeating 10's | |
397 | * MODE = Ethernet | |
398 | */ | |
399 | ||
400 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI | | |
401 | SCC_GSMRL_TPL_48 | | |
402 | SCC_GSMRL_TPP_10 | | |
403 | SCC_GSMRL_MODE_ENET); | |
404 | ||
405 | /* | |
406 | * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 | |
407 | */ | |
408 | ||
409 | immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555; | |
410 | ||
411 | /* | |
412 | * Initialize the PSMR | |
413 | * Settings: | |
414 | * CRC = 32-Bit CCITT | |
415 | * NIB = Begin searching for SFD 22 bits after RENA | |
416 | * FDE = Full Duplex Enable | |
417 | * LPB = Loopback Enable (Needed when FDE is set) | |
418 | * BRO = Reject broadcast packets | |
419 | * PROMISCOUS = Catch all packets regardless of dest. MAC adress | |
420 | */ | |
421 | immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC | | |
422 | SCC_PSMR_NIB22 | | |
ed247f48 | 423 | #if defined(CONFIG_SCC_ENET_FULL_DUPLEX) |
3bbc899f | 424 | SCC_PSMR_FDE | SCC_PSMR_LPB | |
ed247f48 WD |
425 | #endif |
426 | #if defined(CONFIG_SCC_ENET_NO_BROADCAST) | |
3bbc899f | 427 | SCC_PSMR_BRO | |
ed247f48 WD |
428 | #endif |
429 | #if defined(CONFIG_SCC_ENET_PROMISCOUS) | |
3bbc899f | 430 | SCC_PSMR_PRO | |
ed247f48 | 431 | #endif |
3bbc899f | 432 | 0; |
ed247f48 | 433 | |
3bbc899f WD |
434 | /* |
435 | * Configure Ethernet TENA Signal | |
436 | */ | |
ed247f48 WD |
437 | |
438 | #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) | |
3bbc899f WD |
439 | immr->im_ioport.iop_pcpar |= PC_ENET_TENA; |
440 | immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; | |
ed247f48 | 441 | #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) |
3bbc899f WD |
442 | immr->im_cpm.cp_pbpar |= PB_ENET_TENA; |
443 | immr->im_cpm.cp_pbdir |= PB_ENET_TENA; | |
ed247f48 WD |
444 | #else |
445 | #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined | |
ed247f48 WD |
446 | #endif |
447 | ||
3bbc899f WD |
448 | /* |
449 | * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive | |
450 | */ | |
ed247f48 | 451 | |
3bbc899f WD |
452 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= |
453 | (SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
ed247f48 | 454 | |
3bbc899f | 455 | return 1; |
ed247f48 WD |
456 | } |
457 | ||
458 | ||
3bbc899f | 459 | static void scc_halt (struct eth_device *dev) |
ed247f48 | 460 | { |
6d0f6bcf | 461 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
3bbc899f WD |
462 | |
463 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= | |
464 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
281e00a3 WD |
465 | |
466 | immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); | |
ed247f48 WD |
467 | } |
468 | ||
469 | #if 0 | |
3bbc899f | 470 | void restart (void) |
ed247f48 | 471 | { |
6d0f6bcf | 472 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
3bbc899f WD |
473 | |
474 | immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= | |
475 | (SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
ed247f48 WD |
476 | } |
477 | #endif | |
068b60a0 | 478 | #endif |