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Commit | Line | Data |
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4a9cbbe8 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
4a9cbbe8 WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <commproc.h> | |
10 | #include <command.h> | |
281e00a3 | 11 | #include <serial.h> |
d0fb80c3 | 12 | #include <watchdog.h> |
6c768ca7 | 13 | #include <linux/compiler.h> |
4a9cbbe8 | 14 | |
d87080b7 WD |
15 | DECLARE_GLOBAL_DATA_PTR; |
16 | ||
4a9cbbe8 WD |
17 | #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ |
18 | ||
19 | #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ | |
20 | #define SMC_INDEX 0 | |
4a9cbbe8 WD |
21 | #define PROFF_SMC PROFF_SMC1 |
22 | #define CPM_CR_CH_SMC CPM_CR_CH_SMC1 | |
23 | ||
24 | #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ | |
25 | #define SMC_INDEX 1 | |
4a9cbbe8 WD |
26 | #define PROFF_SMC PROFF_SMC2 |
27 | #define CPM_CR_CH_SMC CPM_CR_CH_SMC2 | |
28 | ||
281e00a3 WD |
29 | #endif /* CONFIG_8xx_CONS_SMCx */ |
30 | ||
31 | #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ | |
4a9cbbe8 WD |
32 | #define SCC_INDEX 0 |
33 | #define PROFF_SCC PROFF_SCC1 | |
34 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC1 | |
35 | ||
36 | #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */ | |
4a9cbbe8 WD |
37 | #define SCC_INDEX 1 |
38 | #define PROFF_SCC PROFF_SCC2 | |
39 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC2 | |
40 | ||
41 | #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */ | |
4a9cbbe8 WD |
42 | #define SCC_INDEX 2 |
43 | #define PROFF_SCC PROFF_SCC3 | |
44 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC3 | |
45 | ||
46 | #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */ | |
4a9cbbe8 WD |
47 | #define SCC_INDEX 3 |
48 | #define PROFF_SCC PROFF_SCC4 | |
49 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC4 | |
50 | ||
281e00a3 | 51 | #endif /* CONFIG_8xx_CONS_SCCx */ |
4a9cbbe8 | 52 | |
2b3f12c2 HS |
53 | #if !defined(CONFIG_SYS_SMC_RXBUFLEN) |
54 | #define CONFIG_SYS_SMC_RXBUFLEN 1 | |
55 | #define CONFIG_SYS_MAXIDLE 0 | |
56 | #else | |
57 | #if !defined(CONFIG_SYS_MAXIDLE) | |
58 | #error "you must define CONFIG_SYS_MAXIDLE" | |
59 | #endif | |
60 | #endif | |
61 | ||
62 | typedef volatile struct serialbuffer { | |
63 | cbd_t rxbd; /* Rx BD */ | |
64 | cbd_t txbd; /* Tx BD */ | |
65 | uint rxindex; /* index for next character to read */ | |
66 | volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ | |
67 | volatile uchar txbuf; /* tx buffers */ | |
68 | } serialbuffer_t; | |
69 | ||
2535d602 WD |
70 | static void serial_setdivisor(volatile cpm8xx_t *cp) |
71 | { | |
75d1ea7f | 72 | int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; |
2535d602 WD |
73 | |
74 | if(divisor/16>0x1000) { | |
8ed44d91 | 75 | /* bad divisor, assume 50MHz clock and 9600 baud */ |
75d1ea7f | 76 | divisor=(50*1000*1000 + 8*9600)/16/9600; |
2535d602 WD |
77 | } |
78 | ||
6d0f6bcf JCPV |
79 | #ifdef CONFIG_SYS_BRGCLK_PRESCALE |
80 | divisor /= CONFIG_SYS_BRGCLK_PRESCALE; | |
3bbc899f WD |
81 | #endif |
82 | ||
2535d602 WD |
83 | if(divisor<=0x1000) { |
84 | cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; | |
85 | } else { | |
86 | cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16; | |
87 | } | |
88 | } | |
89 | ||
4a9cbbe8 WD |
90 | #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2)) |
91 | ||
92 | /* | |
93 | * Minimal serial functions needed to use one of the SMC ports | |
94 | * as serial console interface. | |
95 | */ | |
96 | ||
281e00a3 WD |
97 | static void smc_setbrg (void) |
98 | { | |
6d0f6bcf | 99 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
281e00a3 WD |
100 | volatile cpm8xx_t *cp = &(im->im_cpm); |
101 | ||
102 | /* Set up the baud rate generator. | |
103 | * See 8xx_io/commproc.c for details. | |
104 | * | |
105 | * Wire BRG1 to SMCx | |
106 | */ | |
107 | ||
108 | cp->cp_simode = 0x00000000; | |
109 | ||
110 | serial_setdivisor(cp); | |
111 | } | |
112 | ||
113 | static int smc_init (void) | |
4a9cbbe8 | 114 | { |
6d0f6bcf | 115 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
116 | volatile smc_t *sp; |
117 | volatile smc_uart_t *up; | |
4a9cbbe8 WD |
118 | volatile cpm8xx_t *cp = &(im->im_cpm); |
119 | #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850)) | |
120 | volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); | |
121 | #endif | |
122 | uint dpaddr; | |
2b3f12c2 | 123 | volatile serialbuffer_t *rtx; |
4a9cbbe8 WD |
124 | |
125 | /* initialize pointers to SMC */ | |
126 | ||
127 | sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); | |
128 | up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 129 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
130 | up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase]; |
131 | #else | |
132 | /* Disable relocation */ | |
133 | up->smc_rpbase = 0; | |
134 | #endif | |
4a9cbbe8 | 135 | |
255d28e1 | 136 | /* Disable transmitter/receiver. */ |
4a9cbbe8 WD |
137 | sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); |
138 | ||
255d28e1 | 139 | /* Enable SDMA. */ |
4a9cbbe8 WD |
140 | im->im_siu_conf.sc_sdcr = 1; |
141 | ||
142 | /* clear error conditions */ | |
6d0f6bcf JCPV |
143 | #ifdef CONFIG_SYS_SDSR |
144 | im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; | |
4a9cbbe8 WD |
145 | #else |
146 | im->im_sdma.sdma_sdsr = 0x83; | |
147 | #endif | |
148 | ||
149 | /* clear SDMA interrupt mask */ | |
6d0f6bcf JCPV |
150 | #ifdef CONFIG_SYS_SDMR |
151 | im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; | |
4a9cbbe8 WD |
152 | #else |
153 | im->im_sdma.sdma_sdmr = 0x00; | |
154 | #endif | |
155 | ||
156 | #if defined(CONFIG_8xx_CONS_SMC1) | |
255d28e1 | 157 | /* Use Port B for SMC1 instead of other functions. */ |
4a9cbbe8 WD |
158 | cp->cp_pbpar |= 0x000000c0; |
159 | cp->cp_pbdir &= ~0x000000c0; | |
160 | cp->cp_pbodr &= ~0x000000c0; | |
161 | #else /* CONFIG_8xx_CONS_SMC2 */ | |
162 | # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850) | |
255d28e1 | 163 | /* Use Port A for SMC2 instead of other functions. */ |
4a9cbbe8 WD |
164 | ip->iop_papar |= 0x00c0; |
165 | ip->iop_padir &= ~0x00c0; | |
166 | ip->iop_paodr &= ~0x00c0; | |
167 | # else /* must be a 860 then */ | |
168 | /* Use Port B for SMC2 instead of other functions. | |
255d28e1 | 169 | */ |
4a9cbbe8 WD |
170 | cp->cp_pbpar |= 0x00000c00; |
171 | cp->cp_pbdir &= ~0x00000c00; | |
172 | cp->cp_pbodr &= ~0x00000c00; | |
173 | # endif | |
174 | #endif | |
175 | ||
b028f715 | 176 | #if defined(CONFIG_FADS) || defined(CONFIG_ADS) |
4a9cbbe8 WD |
177 | /* Enable RS232 */ |
178 | #if defined(CONFIG_8xx_CONS_SMC1) | |
179 | *((uint *) BCSR1) &= ~BCSR1_RS232EN_1; | |
180 | #else | |
181 | *((uint *) BCSR1) &= ~BCSR1_RS232EN_2; | |
182 | #endif | |
183 | #endif /* CONFIG_FADS */ | |
184 | ||
185 | #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) | |
186 | /* Enable Monitor Port Transceiver */ | |
187 | *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; | |
188 | #endif /* CONFIG_RPXLITE */ | |
189 | ||
190 | /* Set the physical address of the host memory buffers in | |
191 | * the buffer descriptors. | |
192 | */ | |
193 | ||
6d0f6bcf | 194 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
2b3f12c2 HS |
195 | /* allocate |
196 | * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index | |
197 | */ | |
198 | dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8); | |
4a9cbbe8 WD |
199 | #else |
200 | dpaddr = CPM_SERIAL_BASE ; | |
201 | #endif | |
202 | ||
2b3f12c2 | 203 | rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr]; |
4a9cbbe8 WD |
204 | /* Allocate space for two buffer descriptors in the DP ram. |
205 | * For now, this address seems OK, but it may have to | |
206 | * change with newer versions of the firmware. | |
207 | * damm: allocating space after the two buffers for rx/tx data | |
208 | */ | |
209 | ||
2b3f12c2 HS |
210 | rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; |
211 | rtx->rxbd.cbd_sc = 0; | |
212 | ||
213 | rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; | |
214 | rtx->txbd.cbd_sc = 0; | |
4a9cbbe8 | 215 | |
255d28e1 | 216 | /* Set up the uart parameters in the parameter ram. */ |
4a9cbbe8 WD |
217 | up->smc_rbase = dpaddr; |
218 | up->smc_tbase = dpaddr+sizeof(cbd_t); | |
219 | up->smc_rfcr = SMC_EB; | |
220 | up->smc_tfcr = SMC_EB; | |
6d0f6bcf | 221 | #if defined (CONFIG_SYS_SMC_UCODE_PATCH) |
b423d055 HS |
222 | up->smc_rbptr = up->smc_rbase; |
223 | up->smc_tbptr = up->smc_tbase; | |
224 | up->smc_rstate = 0; | |
225 | up->smc_tstate = 0; | |
226 | #endif | |
4a9cbbe8 WD |
227 | |
228 | #if defined(CONFIG_MBX) | |
229 | board_serial_init(); | |
230 | #endif /* CONFIG_MBX */ | |
231 | ||
232 | /* Set UART mode, 8 bit, no parity, one stop. | |
233 | * Enable receive and transmit. | |
234 | */ | |
235 | sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; | |
236 | ||
237 | /* Mask all interrupts and remove anything pending. | |
238 | */ | |
239 | sp->smc_smcm = 0; | |
240 | sp->smc_smce = 0xff; | |
241 | ||
6d0f6bcf | 242 | #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4 |
8139567b | 243 | /* clock source is PLD */ |
2a8dfe08 | 244 | |
8139567b | 245 | /* set freq to 19200 Baud */ |
6d0f6bcf | 246 | *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3; |
8139567b MK |
247 | /* configure clk4 as input */ |
248 | im->im_ioport.iop_pdpar |= 0x800; | |
249 | im->im_ioport.iop_pddir &= ~0x800; | |
f11033e7 | 250 | |
2a8dfe08 | 251 | cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000); |
b02d0177 MK |
252 | #else |
253 | /* Set up the baud rate generator */ | |
281e00a3 | 254 | smc_setbrg (); |
b02d0177 | 255 | #endif |
4a9cbbe8 | 256 | |
255d28e1 | 257 | /* Make the first buffer the only buffer. */ |
2b3f12c2 HS |
258 | rtx->txbd.cbd_sc |= BD_SC_WRAP; |
259 | rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; | |
4a9cbbe8 | 260 | |
2b3f12c2 HS |
261 | /* single/multi character receive. */ |
262 | up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; | |
263 | up->smc_maxidl = CONFIG_SYS_MAXIDLE; | |
264 | rtx->rxindex = 0; | |
4a9cbbe8 | 265 | |
255d28e1 | 266 | /* Initialize Tx/Rx parameters. */ |
4a9cbbe8 WD |
267 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ |
268 | ; | |
269 | ||
270 | cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
271 | ||
272 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
273 | ; | |
274 | ||
255d28e1 | 275 | /* Enable transmitter/receiver. */ |
4a9cbbe8 WD |
276 | sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; |
277 | ||
278 | return (0); | |
279 | } | |
280 | ||
281e00a3 WD |
281 | static void |
282 | smc_putc(const char c) | |
4a9cbbe8 | 283 | { |
4a9cbbe8 | 284 | volatile smc_uart_t *up; |
6d0f6bcf | 285 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 | 286 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
2b3f12c2 | 287 | volatile serialbuffer_t *rtx; |
4a9cbbe8 | 288 | |
4532cb69 | 289 | #ifdef CONFIG_MODEM_SUPPORT |
4532cb69 WD |
290 | if (gd->be_quiet) |
291 | return; | |
292 | #endif | |
293 | ||
4a9cbbe8 | 294 | if (c == '\n') |
281e00a3 | 295 | smc_putc ('\r'); |
4a9cbbe8 WD |
296 | |
297 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 298 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
299 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
300 | #endif | |
4a9cbbe8 | 301 | |
2b3f12c2 | 302 | rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; |
4a9cbbe8 | 303 | |
255d28e1 | 304 | /* Wait for last character to go. */ |
2b3f12c2 HS |
305 | rtx->txbuf = c; |
306 | rtx->txbd.cbd_datlen = 1; | |
307 | rtx->txbd.cbd_sc |= BD_SC_READY; | |
4a9cbbe8 | 308 | __asm__("eieio"); |
d0fb80c3 | 309 | |
2b3f12c2 | 310 | while (rtx->txbd.cbd_sc & BD_SC_READY) { |
d0fb80c3 | 311 | WATCHDOG_RESET (); |
4a9cbbe8 | 312 | __asm__("eieio"); |
d0fb80c3 | 313 | } |
4a9cbbe8 WD |
314 | } |
315 | ||
281e00a3 WD |
316 | static void |
317 | smc_puts (const char *s) | |
318 | { | |
319 | while (*s) { | |
320 | smc_putc (*s++); | |
321 | } | |
322 | } | |
323 | ||
324 | static int | |
325 | smc_getc(void) | |
4a9cbbe8 | 326 | { |
4a9cbbe8 | 327 | volatile smc_uart_t *up; |
6d0f6bcf | 328 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 | 329 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
2b3f12c2 HS |
330 | volatile serialbuffer_t *rtx; |
331 | unsigned char c; | |
4a9cbbe8 WD |
332 | |
333 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 334 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
335 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
336 | #endif | |
2b3f12c2 | 337 | rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; |
4a9cbbe8 | 338 | |
255d28e1 | 339 | /* Wait for character to show up. */ |
2b3f12c2 | 340 | while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) |
d0fb80c3 WD |
341 | WATCHDOG_RESET (); |
342 | ||
2b3f12c2 HS |
343 | /* the characters are read one by one, |
344 | * use the rxindex to know the next char to deliver | |
345 | */ | |
346 | c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex); | |
347 | rtx->rxindex++; | |
4a9cbbe8 | 348 | |
2b3f12c2 HS |
349 | /* check if all char are readout, then make prepare for next receive */ |
350 | if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { | |
351 | rtx->rxindex = 0; | |
352 | rtx->rxbd.cbd_sc |= BD_SC_EMPTY; | |
353 | } | |
4a9cbbe8 WD |
354 | return(c); |
355 | } | |
356 | ||
281e00a3 WD |
357 | static int |
358 | smc_tstc(void) | |
4a9cbbe8 | 359 | { |
4a9cbbe8 | 360 | volatile smc_uart_t *up; |
6d0f6bcf | 361 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 | 362 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
2b3f12c2 | 363 | volatile serialbuffer_t *rtx; |
4a9cbbe8 WD |
364 | |
365 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 366 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
367 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
368 | #endif | |
4a9cbbe8 | 369 | |
2b3f12c2 | 370 | rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; |
4a9cbbe8 | 371 | |
2b3f12c2 | 372 | return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); |
4a9cbbe8 WD |
373 | } |
374 | ||
281e00a3 WD |
375 | struct serial_device serial_smc_device = |
376 | { | |
90bad891 MV |
377 | .name = "serial_smc", |
378 | .start = smc_init, | |
379 | .stop = NULL, | |
380 | .setbrg = smc_setbrg, | |
381 | .getc = smc_getc, | |
382 | .tstc = smc_tstc, | |
383 | .putc = smc_putc, | |
384 | .puts = smc_puts, | |
281e00a3 WD |
385 | }; |
386 | ||
387 | #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */ | |
388 | ||
389 | #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ | |
390 | defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) | |
391 | ||
392 | static void | |
393 | scc_setbrg (void) | |
394 | { | |
6d0f6bcf | 395 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
281e00a3 | 396 | volatile cpm8xx_t *cp = &(im->im_cpm); |
4a9cbbe8 | 397 | |
281e00a3 WD |
398 | /* Set up the baud rate generator. |
399 | * See 8xx_io/commproc.c for details. | |
400 | * | |
401 | * Wire BRG1 to SCCx | |
402 | */ | |
403 | ||
404 | cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); | |
405 | ||
406 | serial_setdivisor(cp); | |
407 | } | |
408 | ||
409 | static int scc_init (void) | |
4a9cbbe8 | 410 | { |
6d0f6bcf | 411 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
412 | volatile scc_t *sp; |
413 | volatile scc_uart_t *up; | |
414 | volatile cbd_t *tbdf, *rbdf; | |
415 | volatile cpm8xx_t *cp = &(im->im_cpm); | |
416 | uint dpaddr; | |
417 | #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850) | |
418 | volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); | |
419 | #endif | |
420 | ||
421 | /* initialize pointers to SCC */ | |
422 | ||
423 | sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]); | |
424 | up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC]; | |
425 | ||
426 | #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2) | |
427 | { /* Disable Ethernet, enable Serial */ | |
428 | uchar c; | |
429 | ||
430 | c = pic_read (0x61); | |
431 | c &= ~0x40; /* enable COM3 */ | |
432 | c |= 0x80; /* disable Ethernet */ | |
433 | pic_write (0x61, c); | |
434 | ||
435 | /* enable RTS2 */ | |
436 | cp->cp_pbpar |= 0x2000; | |
437 | cp->cp_pbdat |= 0x2000; | |
438 | cp->cp_pbdir |= 0x2000; | |
439 | } | |
440 | #endif /* CONFIG_LWMON */ | |
441 | ||
255d28e1 | 442 | /* Disable transmitter/receiver. */ |
4a9cbbe8 WD |
443 | sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
444 | ||
445 | #if (SCC_INDEX == 2) && defined(CONFIG_MPC850) | |
446 | /* | |
447 | * The MPC850 has SCC3 on Port B | |
448 | */ | |
449 | cp->cp_pbpar |= 0x06; | |
450 | cp->cp_pbdir &= ~0x06; | |
451 | cp->cp_pbodr &= ~0x06; | |
452 | ||
453 | #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860) | |
454 | /* | |
455 | * Standard configuration for SCC's is on Part A | |
456 | */ | |
457 | ip->iop_papar |= ((3 << (2 * SCC_INDEX))); | |
458 | ip->iop_padir &= ~((3 << (2 * SCC_INDEX))); | |
459 | ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); | |
460 | #else | |
461 | /* | |
462 | * The IP860 has SCC3 and SCC4 on Port D | |
463 | */ | |
464 | ip->iop_pdpar |= ((3 << (2 * SCC_INDEX))); | |
465 | #endif | |
466 | ||
255d28e1 | 467 | /* Allocate space for two buffer descriptors in the DP ram. */ |
4a9cbbe8 | 468 | |
6d0f6bcf | 469 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
4a9cbbe8 WD |
470 | dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; |
471 | #else | |
281e00a3 | 472 | dpaddr = CPM_SERIAL2_BASE ; |
4a9cbbe8 WD |
473 | #endif |
474 | ||
255d28e1 | 475 | /* Enable SDMA. */ |
4a9cbbe8 WD |
476 | im->im_siu_conf.sc_sdcr = 0x0001; |
477 | ||
478 | /* Set the physical address of the host memory buffers in | |
479 | * the buffer descriptors. | |
480 | */ | |
481 | ||
482 | rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; | |
483 | rbdf->cbd_bufaddr = (uint) (rbdf+2); | |
484 | rbdf->cbd_sc = 0; | |
485 | tbdf = rbdf + 1; | |
486 | tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; | |
487 | tbdf->cbd_sc = 0; | |
488 | ||
255d28e1 | 489 | /* Set up the baud rate generator. */ |
281e00a3 | 490 | scc_setbrg (); |
4a9cbbe8 | 491 | |
255d28e1 | 492 | /* Set up the uart parameters in the parameter ram. */ |
4a9cbbe8 WD |
493 | up->scc_genscc.scc_rbase = dpaddr; |
494 | up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); | |
495 | ||
255d28e1 | 496 | /* Initialize Tx/Rx parameters. */ |
4a9cbbe8 WD |
497 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ |
498 | ; | |
499 | cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
500 | ||
501 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
502 | ; | |
503 | ||
504 | up->scc_genscc.scc_rfcr = SCC_EB | 0x05; | |
505 | up->scc_genscc.scc_tfcr = SCC_EB | 0x05; | |
506 | ||
507 | up->scc_genscc.scc_mrblr = 1; /* Single character receive */ | |
508 | up->scc_maxidl = 0; /* disable max idle */ | |
509 | up->scc_brkcr = 1; /* send one break character on stop TX */ | |
510 | up->scc_parec = 0; | |
511 | up->scc_frmec = 0; | |
512 | up->scc_nosec = 0; | |
513 | up->scc_brkec = 0; | |
514 | up->scc_uaddr1 = 0; | |
515 | up->scc_uaddr2 = 0; | |
516 | up->scc_toseq = 0; | |
517 | up->scc_char1 = 0x8000; | |
518 | up->scc_char2 = 0x8000; | |
519 | up->scc_char3 = 0x8000; | |
520 | up->scc_char4 = 0x8000; | |
521 | up->scc_char5 = 0x8000; | |
522 | up->scc_char6 = 0x8000; | |
523 | up->scc_char7 = 0x8000; | |
524 | up->scc_char8 = 0x8000; | |
525 | up->scc_rccm = 0xc0ff; | |
526 | ||
255d28e1 | 527 | /* Set low latency / small fifo. */ |
4a9cbbe8 WD |
528 | sp->scc_gsmrh = SCC_GSMRH_RFW; |
529 | ||
530 | /* Set SCC(x) clock mode to 16x | |
531 | * See 8xx_io/commproc.c for details. | |
532 | * | |
533 | * Wire BRG1 to SCCn | |
534 | */ | |
535 | ||
255d28e1 | 536 | /* Set UART mode, clock divider 16 on Tx and Rx */ |
281e00a3 | 537 | sp->scc_gsmrl &= ~0xF; |
4a9cbbe8 WD |
538 | sp->scc_gsmrl |= |
539 | (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
540 | ||
281e00a3 | 541 | sp->scc_psmr = 0; |
4a9cbbe8 WD |
542 | sp->scc_psmr |= SCU_PSMR_CL; |
543 | ||
255d28e1 | 544 | /* Mask all interrupts and remove anything pending. */ |
4a9cbbe8 WD |
545 | sp->scc_sccm = 0; |
546 | sp->scc_scce = 0xffff; | |
547 | sp->scc_dsr = 0x7e7e; | |
548 | sp->scc_psmr = 0x3000; | |
549 | ||
255d28e1 | 550 | /* Make the first buffer the only buffer. */ |
4a9cbbe8 WD |
551 | tbdf->cbd_sc |= BD_SC_WRAP; |
552 | rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; | |
553 | ||
255d28e1 | 554 | /* Enable transmitter/receiver. */ |
4a9cbbe8 WD |
555 | sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
556 | ||
557 | return (0); | |
558 | } | |
559 | ||
281e00a3 WD |
560 | static void |
561 | scc_putc(const char c) | |
4a9cbbe8 WD |
562 | { |
563 | volatile cbd_t *tbdf; | |
564 | volatile char *buf; | |
565 | volatile scc_uart_t *up; | |
6d0f6bcf | 566 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
567 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
568 | ||
281e00a3 | 569 | #ifdef CONFIG_MODEM_SUPPORT |
281e00a3 WD |
570 | if (gd->be_quiet) |
571 | return; | |
572 | #endif | |
573 | ||
4a9cbbe8 | 574 | if (c == '\n') |
281e00a3 | 575 | scc_putc ('\r'); |
4a9cbbe8 WD |
576 | |
577 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
578 | ||
579 | tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; | |
580 | ||
255d28e1 | 581 | /* Wait for last character to go. */ |
4a9cbbe8 WD |
582 | |
583 | buf = (char *)tbdf->cbd_bufaddr; | |
4a9cbbe8 WD |
584 | |
585 | *buf = c; | |
586 | tbdf->cbd_datlen = 1; | |
587 | tbdf->cbd_sc |= BD_SC_READY; | |
588 | __asm__("eieio"); | |
d0fb80c3 WD |
589 | |
590 | while (tbdf->cbd_sc & BD_SC_READY) { | |
4a9cbbe8 | 591 | __asm__("eieio"); |
d0fb80c3 WD |
592 | WATCHDOG_RESET (); |
593 | } | |
4a9cbbe8 WD |
594 | } |
595 | ||
281e00a3 WD |
596 | static void |
597 | scc_puts (const char *s) | |
598 | { | |
599 | while (*s) { | |
600 | scc_putc (*s++); | |
601 | } | |
602 | } | |
603 | ||
604 | static int | |
605 | scc_getc(void) | |
4a9cbbe8 WD |
606 | { |
607 | volatile cbd_t *rbdf; | |
608 | volatile unsigned char *buf; | |
609 | volatile scc_uart_t *up; | |
6d0f6bcf | 610 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
611 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
612 | unsigned char c; | |
613 | ||
614 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
615 | ||
616 | rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; | |
617 | ||
255d28e1 | 618 | /* Wait for character to show up. */ |
4a9cbbe8 | 619 | buf = (unsigned char *)rbdf->cbd_bufaddr; |
d0fb80c3 | 620 | |
4a9cbbe8 | 621 | while (rbdf->cbd_sc & BD_SC_EMPTY) |
d0fb80c3 WD |
622 | WATCHDOG_RESET (); |
623 | ||
4a9cbbe8 WD |
624 | c = *buf; |
625 | rbdf->cbd_sc |= BD_SC_EMPTY; | |
626 | ||
627 | return(c); | |
628 | } | |
629 | ||
281e00a3 WD |
630 | static int |
631 | scc_tstc(void) | |
4a9cbbe8 WD |
632 | { |
633 | volatile cbd_t *rbdf; | |
634 | volatile scc_uart_t *up; | |
6d0f6bcf | 635 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
636 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
637 | ||
638 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
639 | ||
640 | rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; | |
641 | ||
642 | return(!(rbdf->cbd_sc & BD_SC_EMPTY)); | |
643 | } | |
644 | ||
281e00a3 WD |
645 | struct serial_device serial_scc_device = |
646 | { | |
90bad891 MV |
647 | .name = "serial_scc", |
648 | .start = scc_init, | |
649 | .stop = NULL, | |
650 | .setbrg = scc_setbrg, | |
651 | .getc = scc_getc, | |
652 | .tstc = scc_tstc, | |
653 | .putc = scc_putc, | |
654 | .puts = scc_puts, | |
281e00a3 WD |
655 | }; |
656 | ||
657 | #endif /* CONFIG_8xx_CONS_SCCx */ | |
4a9cbbe8 | 658 | |
6c768ca7 MF |
659 | __weak struct serial_device *default_serial_console(void) |
660 | { | |
661 | #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) | |
662 | return &serial_smc_device; | |
663 | #else | |
664 | return &serial_scc_device; | |
665 | #endif | |
666 | } | |
667 | ||
f0eb1f61 MV |
668 | void mpc8xx_serial_initialize(void) |
669 | { | |
670 | #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) | |
671 | serial_register(&serial_smc_device); | |
672 | #endif | |
673 | #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ | |
674 | defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) | |
675 | serial_register(&serial_scc_device); | |
676 | #endif | |
677 | } | |
678 | ||
281e00a3 WD |
679 | #ifdef CONFIG_MODEM_SUPPORT |
680 | void disable_putc(void) | |
4a9cbbe8 | 681 | { |
281e00a3 | 682 | gd->be_quiet = 1; |
4a9cbbe8 WD |
683 | } |
684 | ||
281e00a3 WD |
685 | void enable_putc(void) |
686 | { | |
281e00a3 WD |
687 | gd->be_quiet = 0; |
688 | } | |
689 | #endif | |
4a9cbbe8 | 690 | |
4431283c | 691 | #if defined(CONFIG_CMD_KGDB) |
4a9cbbe8 WD |
692 | |
693 | void | |
694 | kgdb_serial_init(void) | |
695 | { | |
281e00a3 WD |
696 | int i = -1; |
697 | ||
1c9a5606 | 698 | if (strcmp(default_serial_console()->name, "serial_smc") == 0) |
281e00a3 | 699 | { |
4a9cbbe8 | 700 | #if defined(CONFIG_8xx_CONS_SMC1) |
281e00a3 | 701 | i = 1; |
4a9cbbe8 | 702 | #elif defined(CONFIG_8xx_CONS_SMC2) |
281e00a3 WD |
703 | i = 2; |
704 | #endif | |
705 | } | |
1c9a5606 | 706 | else if (strcmp(default_serial_console()->name, "serial_scc") == 0) |
281e00a3 WD |
707 | { |
708 | #if defined(CONFIG_8xx_CONS_SCC1) | |
709 | i = 1; | |
4a9cbbe8 | 710 | #elif defined(CONFIG_8xx_CONS_SCC2) |
281e00a3 | 711 | i = 2; |
4a9cbbe8 | 712 | #elif defined(CONFIG_8xx_CONS_SCC3) |
281e00a3 | 713 | i = 3; |
4a9cbbe8 | 714 | #elif defined(CONFIG_8xx_CONS_SCC4) |
281e00a3 | 715 | i = 4; |
4a9cbbe8 | 716 | #endif |
281e00a3 WD |
717 | } |
718 | ||
719 | if (i >= 0) | |
720 | { | |
1c9a5606 | 721 | serial_printf("[on %s%d] ", default_serial_console()->name, i); |
281e00a3 | 722 | } |
4a9cbbe8 WD |
723 | } |
724 | ||
725 | void | |
726 | putDebugChar (int c) | |
727 | { | |
728 | serial_putc (c); | |
729 | } | |
730 | ||
731 | void | |
732 | putDebugStr (const char *str) | |
733 | { | |
734 | serial_puts (str); | |
735 | } | |
736 | ||
737 | int | |
738 | getDebugChar (void) | |
739 | { | |
740 | return serial_getc(); | |
741 | } | |
742 | ||
743 | void | |
744 | kgdb_interruptible (int yes) | |
745 | { | |
746 | return; | |
747 | } | |
068b60a0 | 748 | #endif |
4a9cbbe8 WD |
749 | |
750 | #endif /* CONFIG_8xx_CONS_NONE */ |