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Commit | Line | Data |
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4a9cbbe8 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
4a9cbbe8 WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <commproc.h> | |
10 | #include <command.h> | |
281e00a3 | 11 | #include <serial.h> |
d0fb80c3 | 12 | #include <watchdog.h> |
6c768ca7 | 13 | #include <linux/compiler.h> |
4a9cbbe8 | 14 | |
d87080b7 WD |
15 | DECLARE_GLOBAL_DATA_PTR; |
16 | ||
4a9cbbe8 WD |
17 | #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ |
18 | ||
19 | #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ | |
20 | #define SMC_INDEX 0 | |
4a9cbbe8 WD |
21 | #define PROFF_SMC PROFF_SMC1 |
22 | #define CPM_CR_CH_SMC CPM_CR_CH_SMC1 | |
23 | ||
24 | #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ | |
25 | #define SMC_INDEX 1 | |
4a9cbbe8 WD |
26 | #define PROFF_SMC PROFF_SMC2 |
27 | #define CPM_CR_CH_SMC CPM_CR_CH_SMC2 | |
28 | ||
281e00a3 WD |
29 | #endif /* CONFIG_8xx_CONS_SMCx */ |
30 | ||
31 | #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ | |
4a9cbbe8 WD |
32 | #define SCC_INDEX 0 |
33 | #define PROFF_SCC PROFF_SCC1 | |
34 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC1 | |
35 | ||
36 | #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */ | |
4a9cbbe8 WD |
37 | #define SCC_INDEX 1 |
38 | #define PROFF_SCC PROFF_SCC2 | |
39 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC2 | |
40 | ||
41 | #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */ | |
4a9cbbe8 WD |
42 | #define SCC_INDEX 2 |
43 | #define PROFF_SCC PROFF_SCC3 | |
44 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC3 | |
45 | ||
46 | #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */ | |
4a9cbbe8 WD |
47 | #define SCC_INDEX 3 |
48 | #define PROFF_SCC PROFF_SCC4 | |
49 | #define CPM_CR_CH_SCC CPM_CR_CH_SCC4 | |
50 | ||
281e00a3 | 51 | #endif /* CONFIG_8xx_CONS_SCCx */ |
4a9cbbe8 | 52 | |
2b3f12c2 HS |
53 | #if !defined(CONFIG_SYS_SMC_RXBUFLEN) |
54 | #define CONFIG_SYS_SMC_RXBUFLEN 1 | |
55 | #define CONFIG_SYS_MAXIDLE 0 | |
56 | #else | |
57 | #if !defined(CONFIG_SYS_MAXIDLE) | |
58 | #error "you must define CONFIG_SYS_MAXIDLE" | |
59 | #endif | |
60 | #endif | |
61 | ||
62 | typedef volatile struct serialbuffer { | |
63 | cbd_t rxbd; /* Rx BD */ | |
64 | cbd_t txbd; /* Tx BD */ | |
65 | uint rxindex; /* index for next character to read */ | |
66 | volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ | |
67 | volatile uchar txbuf; /* tx buffers */ | |
68 | } serialbuffer_t; | |
69 | ||
2535d602 WD |
70 | static void serial_setdivisor(volatile cpm8xx_t *cp) |
71 | { | |
75d1ea7f | 72 | int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; |
2535d602 WD |
73 | |
74 | if(divisor/16>0x1000) { | |
8ed44d91 | 75 | /* bad divisor, assume 50MHz clock and 9600 baud */ |
75d1ea7f | 76 | divisor=(50*1000*1000 + 8*9600)/16/9600; |
2535d602 WD |
77 | } |
78 | ||
6d0f6bcf JCPV |
79 | #ifdef CONFIG_SYS_BRGCLK_PRESCALE |
80 | divisor /= CONFIG_SYS_BRGCLK_PRESCALE; | |
3bbc899f WD |
81 | #endif |
82 | ||
2535d602 WD |
83 | if(divisor<=0x1000) { |
84 | cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; | |
85 | } else { | |
86 | cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16; | |
87 | } | |
88 | } | |
89 | ||
4a9cbbe8 WD |
90 | #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2)) |
91 | ||
92 | /* | |
93 | * Minimal serial functions needed to use one of the SMC ports | |
94 | * as serial console interface. | |
95 | */ | |
96 | ||
281e00a3 WD |
97 | static void smc_setbrg (void) |
98 | { | |
6d0f6bcf | 99 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
281e00a3 WD |
100 | volatile cpm8xx_t *cp = &(im->im_cpm); |
101 | ||
102 | /* Set up the baud rate generator. | |
103 | * See 8xx_io/commproc.c for details. | |
104 | * | |
105 | * Wire BRG1 to SMCx | |
106 | */ | |
107 | ||
108 | cp->cp_simode = 0x00000000; | |
109 | ||
110 | serial_setdivisor(cp); | |
111 | } | |
112 | ||
113 | static int smc_init (void) | |
4a9cbbe8 | 114 | { |
6d0f6bcf | 115 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
116 | volatile smc_t *sp; |
117 | volatile smc_uart_t *up; | |
4a9cbbe8 WD |
118 | volatile cpm8xx_t *cp = &(im->im_cpm); |
119 | #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850)) | |
120 | volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); | |
121 | #endif | |
122 | uint dpaddr; | |
2b3f12c2 | 123 | volatile serialbuffer_t *rtx; |
4a9cbbe8 WD |
124 | |
125 | /* initialize pointers to SMC */ | |
126 | ||
127 | sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); | |
128 | up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 129 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
130 | up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase]; |
131 | #else | |
132 | /* Disable relocation */ | |
133 | up->smc_rpbase = 0; | |
134 | #endif | |
4a9cbbe8 | 135 | |
255d28e1 | 136 | /* Disable transmitter/receiver. */ |
4a9cbbe8 WD |
137 | sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); |
138 | ||
255d28e1 | 139 | /* Enable SDMA. */ |
4a9cbbe8 WD |
140 | im->im_siu_conf.sc_sdcr = 1; |
141 | ||
142 | /* clear error conditions */ | |
6d0f6bcf JCPV |
143 | #ifdef CONFIG_SYS_SDSR |
144 | im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; | |
4a9cbbe8 WD |
145 | #else |
146 | im->im_sdma.sdma_sdsr = 0x83; | |
147 | #endif | |
148 | ||
149 | /* clear SDMA interrupt mask */ | |
6d0f6bcf JCPV |
150 | #ifdef CONFIG_SYS_SDMR |
151 | im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; | |
4a9cbbe8 WD |
152 | #else |
153 | im->im_sdma.sdma_sdmr = 0x00; | |
154 | #endif | |
155 | ||
156 | #if defined(CONFIG_8xx_CONS_SMC1) | |
255d28e1 | 157 | /* Use Port B for SMC1 instead of other functions. */ |
4a9cbbe8 WD |
158 | cp->cp_pbpar |= 0x000000c0; |
159 | cp->cp_pbdir &= ~0x000000c0; | |
160 | cp->cp_pbodr &= ~0x000000c0; | |
161 | #else /* CONFIG_8xx_CONS_SMC2 */ | |
162 | # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850) | |
255d28e1 | 163 | /* Use Port A for SMC2 instead of other functions. */ |
4a9cbbe8 WD |
164 | ip->iop_papar |= 0x00c0; |
165 | ip->iop_padir &= ~0x00c0; | |
166 | ip->iop_paodr &= ~0x00c0; | |
167 | # else /* must be a 860 then */ | |
168 | /* Use Port B for SMC2 instead of other functions. | |
255d28e1 | 169 | */ |
4a9cbbe8 WD |
170 | cp->cp_pbpar |= 0x00000c00; |
171 | cp->cp_pbdir &= ~0x00000c00; | |
172 | cp->cp_pbodr &= ~0x00000c00; | |
173 | # endif | |
174 | #endif | |
175 | ||
4a9cbbe8 WD |
176 | /* Set the physical address of the host memory buffers in |
177 | * the buffer descriptors. | |
178 | */ | |
179 | ||
6d0f6bcf | 180 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
2b3f12c2 HS |
181 | /* allocate |
182 | * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index | |
183 | */ | |
184 | dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8); | |
4a9cbbe8 WD |
185 | #else |
186 | dpaddr = CPM_SERIAL_BASE ; | |
187 | #endif | |
188 | ||
2b3f12c2 | 189 | rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr]; |
4a9cbbe8 WD |
190 | /* Allocate space for two buffer descriptors in the DP ram. |
191 | * For now, this address seems OK, but it may have to | |
192 | * change with newer versions of the firmware. | |
193 | * damm: allocating space after the two buffers for rx/tx data | |
194 | */ | |
195 | ||
2b3f12c2 HS |
196 | rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; |
197 | rtx->rxbd.cbd_sc = 0; | |
198 | ||
199 | rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; | |
200 | rtx->txbd.cbd_sc = 0; | |
4a9cbbe8 | 201 | |
255d28e1 | 202 | /* Set up the uart parameters in the parameter ram. */ |
4a9cbbe8 WD |
203 | up->smc_rbase = dpaddr; |
204 | up->smc_tbase = dpaddr+sizeof(cbd_t); | |
205 | up->smc_rfcr = SMC_EB; | |
206 | up->smc_tfcr = SMC_EB; | |
6d0f6bcf | 207 | #if defined (CONFIG_SYS_SMC_UCODE_PATCH) |
b423d055 HS |
208 | up->smc_rbptr = up->smc_rbase; |
209 | up->smc_tbptr = up->smc_tbase; | |
210 | up->smc_rstate = 0; | |
211 | up->smc_tstate = 0; | |
212 | #endif | |
4a9cbbe8 | 213 | |
4a9cbbe8 WD |
214 | /* Set UART mode, 8 bit, no parity, one stop. |
215 | * Enable receive and transmit. | |
216 | */ | |
217 | sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; | |
218 | ||
219 | /* Mask all interrupts and remove anything pending. | |
220 | */ | |
221 | sp->smc_smcm = 0; | |
222 | sp->smc_smce = 0xff; | |
223 | ||
6d0f6bcf | 224 | #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4 |
8139567b | 225 | /* clock source is PLD */ |
2a8dfe08 | 226 | |
8139567b | 227 | /* set freq to 19200 Baud */ |
6d0f6bcf | 228 | *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3; |
8139567b MK |
229 | /* configure clk4 as input */ |
230 | im->im_ioport.iop_pdpar |= 0x800; | |
231 | im->im_ioport.iop_pddir &= ~0x800; | |
f11033e7 | 232 | |
2a8dfe08 | 233 | cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000); |
b02d0177 MK |
234 | #else |
235 | /* Set up the baud rate generator */ | |
281e00a3 | 236 | smc_setbrg (); |
b02d0177 | 237 | #endif |
4a9cbbe8 | 238 | |
255d28e1 | 239 | /* Make the first buffer the only buffer. */ |
2b3f12c2 HS |
240 | rtx->txbd.cbd_sc |= BD_SC_WRAP; |
241 | rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; | |
4a9cbbe8 | 242 | |
2b3f12c2 HS |
243 | /* single/multi character receive. */ |
244 | up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; | |
245 | up->smc_maxidl = CONFIG_SYS_MAXIDLE; | |
246 | rtx->rxindex = 0; | |
4a9cbbe8 | 247 | |
255d28e1 | 248 | /* Initialize Tx/Rx parameters. */ |
4a9cbbe8 WD |
249 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ |
250 | ; | |
251 | ||
252 | cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
253 | ||
254 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
255 | ; | |
256 | ||
255d28e1 | 257 | /* Enable transmitter/receiver. */ |
4a9cbbe8 WD |
258 | sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; |
259 | ||
260 | return (0); | |
261 | } | |
262 | ||
281e00a3 WD |
263 | static void |
264 | smc_putc(const char c) | |
4a9cbbe8 | 265 | { |
4a9cbbe8 | 266 | volatile smc_uart_t *up; |
6d0f6bcf | 267 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 | 268 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
2b3f12c2 | 269 | volatile serialbuffer_t *rtx; |
4a9cbbe8 | 270 | |
4532cb69 | 271 | #ifdef CONFIG_MODEM_SUPPORT |
4532cb69 WD |
272 | if (gd->be_quiet) |
273 | return; | |
274 | #endif | |
275 | ||
4a9cbbe8 | 276 | if (c == '\n') |
281e00a3 | 277 | smc_putc ('\r'); |
4a9cbbe8 WD |
278 | |
279 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 280 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
281 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
282 | #endif | |
4a9cbbe8 | 283 | |
2b3f12c2 | 284 | rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; |
4a9cbbe8 | 285 | |
255d28e1 | 286 | /* Wait for last character to go. */ |
2b3f12c2 HS |
287 | rtx->txbuf = c; |
288 | rtx->txbd.cbd_datlen = 1; | |
289 | rtx->txbd.cbd_sc |= BD_SC_READY; | |
4a9cbbe8 | 290 | __asm__("eieio"); |
d0fb80c3 | 291 | |
2b3f12c2 | 292 | while (rtx->txbd.cbd_sc & BD_SC_READY) { |
d0fb80c3 | 293 | WATCHDOG_RESET (); |
4a9cbbe8 | 294 | __asm__("eieio"); |
d0fb80c3 | 295 | } |
4a9cbbe8 WD |
296 | } |
297 | ||
281e00a3 WD |
298 | static void |
299 | smc_puts (const char *s) | |
300 | { | |
301 | while (*s) { | |
302 | smc_putc (*s++); | |
303 | } | |
304 | } | |
305 | ||
306 | static int | |
307 | smc_getc(void) | |
4a9cbbe8 | 308 | { |
4a9cbbe8 | 309 | volatile smc_uart_t *up; |
6d0f6bcf | 310 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 | 311 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
2b3f12c2 HS |
312 | volatile serialbuffer_t *rtx; |
313 | unsigned char c; | |
4a9cbbe8 WD |
314 | |
315 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 316 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
317 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
318 | #endif | |
2b3f12c2 | 319 | rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; |
4a9cbbe8 | 320 | |
255d28e1 | 321 | /* Wait for character to show up. */ |
2b3f12c2 | 322 | while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) |
d0fb80c3 WD |
323 | WATCHDOG_RESET (); |
324 | ||
2b3f12c2 HS |
325 | /* the characters are read one by one, |
326 | * use the rxindex to know the next char to deliver | |
327 | */ | |
328 | c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex); | |
329 | rtx->rxindex++; | |
4a9cbbe8 | 330 | |
2b3f12c2 HS |
331 | /* check if all char are readout, then make prepare for next receive */ |
332 | if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { | |
333 | rtx->rxindex = 0; | |
334 | rtx->rxbd.cbd_sc |= BD_SC_EMPTY; | |
335 | } | |
4a9cbbe8 WD |
336 | return(c); |
337 | } | |
338 | ||
281e00a3 WD |
339 | static int |
340 | smc_tstc(void) | |
4a9cbbe8 | 341 | { |
4a9cbbe8 | 342 | volatile smc_uart_t *up; |
6d0f6bcf | 343 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 | 344 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
2b3f12c2 | 345 | volatile serialbuffer_t *rtx; |
4a9cbbe8 WD |
346 | |
347 | up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; | |
6d0f6bcf | 348 | #ifdef CONFIG_SYS_SMC_UCODE_PATCH |
b423d055 HS |
349 | up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; |
350 | #endif | |
4a9cbbe8 | 351 | |
2b3f12c2 | 352 | rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; |
4a9cbbe8 | 353 | |
2b3f12c2 | 354 | return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); |
4a9cbbe8 WD |
355 | } |
356 | ||
281e00a3 WD |
357 | struct serial_device serial_smc_device = |
358 | { | |
90bad891 MV |
359 | .name = "serial_smc", |
360 | .start = smc_init, | |
361 | .stop = NULL, | |
362 | .setbrg = smc_setbrg, | |
363 | .getc = smc_getc, | |
364 | .tstc = smc_tstc, | |
365 | .putc = smc_putc, | |
366 | .puts = smc_puts, | |
281e00a3 WD |
367 | }; |
368 | ||
369 | #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */ | |
370 | ||
371 | #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ | |
372 | defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) | |
373 | ||
374 | static void | |
375 | scc_setbrg (void) | |
376 | { | |
6d0f6bcf | 377 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
281e00a3 | 378 | volatile cpm8xx_t *cp = &(im->im_cpm); |
4a9cbbe8 | 379 | |
281e00a3 WD |
380 | /* Set up the baud rate generator. |
381 | * See 8xx_io/commproc.c for details. | |
382 | * | |
383 | * Wire BRG1 to SCCx | |
384 | */ | |
385 | ||
386 | cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); | |
387 | ||
388 | serial_setdivisor(cp); | |
389 | } | |
390 | ||
391 | static int scc_init (void) | |
4a9cbbe8 | 392 | { |
6d0f6bcf | 393 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
394 | volatile scc_t *sp; |
395 | volatile scc_uart_t *up; | |
396 | volatile cbd_t *tbdf, *rbdf; | |
397 | volatile cpm8xx_t *cp = &(im->im_cpm); | |
398 | uint dpaddr; | |
399 | #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850) | |
400 | volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); | |
401 | #endif | |
402 | ||
403 | /* initialize pointers to SCC */ | |
404 | ||
405 | sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]); | |
406 | up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC]; | |
407 | ||
408 | #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2) | |
409 | { /* Disable Ethernet, enable Serial */ | |
410 | uchar c; | |
411 | ||
412 | c = pic_read (0x61); | |
413 | c &= ~0x40; /* enable COM3 */ | |
414 | c |= 0x80; /* disable Ethernet */ | |
415 | pic_write (0x61, c); | |
416 | ||
417 | /* enable RTS2 */ | |
418 | cp->cp_pbpar |= 0x2000; | |
419 | cp->cp_pbdat |= 0x2000; | |
420 | cp->cp_pbdir |= 0x2000; | |
421 | } | |
422 | #endif /* CONFIG_LWMON */ | |
423 | ||
255d28e1 | 424 | /* Disable transmitter/receiver. */ |
4a9cbbe8 WD |
425 | sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
426 | ||
427 | #if (SCC_INDEX == 2) && defined(CONFIG_MPC850) | |
428 | /* | |
429 | * The MPC850 has SCC3 on Port B | |
430 | */ | |
431 | cp->cp_pbpar |= 0x06; | |
432 | cp->cp_pbdir &= ~0x06; | |
433 | cp->cp_pbodr &= ~0x06; | |
434 | ||
435 | #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860) | |
436 | /* | |
437 | * Standard configuration for SCC's is on Part A | |
438 | */ | |
439 | ip->iop_papar |= ((3 << (2 * SCC_INDEX))); | |
440 | ip->iop_padir &= ~((3 << (2 * SCC_INDEX))); | |
441 | ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); | |
442 | #else | |
443 | /* | |
444 | * The IP860 has SCC3 and SCC4 on Port D | |
445 | */ | |
446 | ip->iop_pdpar |= ((3 << (2 * SCC_INDEX))); | |
447 | #endif | |
448 | ||
255d28e1 | 449 | /* Allocate space for two buffer descriptors in the DP ram. */ |
4a9cbbe8 | 450 | |
6d0f6bcf | 451 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
4a9cbbe8 WD |
452 | dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; |
453 | #else | |
281e00a3 | 454 | dpaddr = CPM_SERIAL2_BASE ; |
4a9cbbe8 WD |
455 | #endif |
456 | ||
255d28e1 | 457 | /* Enable SDMA. */ |
4a9cbbe8 WD |
458 | im->im_siu_conf.sc_sdcr = 0x0001; |
459 | ||
460 | /* Set the physical address of the host memory buffers in | |
461 | * the buffer descriptors. | |
462 | */ | |
463 | ||
464 | rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; | |
465 | rbdf->cbd_bufaddr = (uint) (rbdf+2); | |
466 | rbdf->cbd_sc = 0; | |
467 | tbdf = rbdf + 1; | |
468 | tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; | |
469 | tbdf->cbd_sc = 0; | |
470 | ||
255d28e1 | 471 | /* Set up the baud rate generator. */ |
281e00a3 | 472 | scc_setbrg (); |
4a9cbbe8 | 473 | |
255d28e1 | 474 | /* Set up the uart parameters in the parameter ram. */ |
4a9cbbe8 WD |
475 | up->scc_genscc.scc_rbase = dpaddr; |
476 | up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); | |
477 | ||
255d28e1 | 478 | /* Initialize Tx/Rx parameters. */ |
4a9cbbe8 WD |
479 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ |
480 | ; | |
481 | cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
482 | ||
483 | while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ | |
484 | ; | |
485 | ||
486 | up->scc_genscc.scc_rfcr = SCC_EB | 0x05; | |
487 | up->scc_genscc.scc_tfcr = SCC_EB | 0x05; | |
488 | ||
489 | up->scc_genscc.scc_mrblr = 1; /* Single character receive */ | |
490 | up->scc_maxidl = 0; /* disable max idle */ | |
491 | up->scc_brkcr = 1; /* send one break character on stop TX */ | |
492 | up->scc_parec = 0; | |
493 | up->scc_frmec = 0; | |
494 | up->scc_nosec = 0; | |
495 | up->scc_brkec = 0; | |
496 | up->scc_uaddr1 = 0; | |
497 | up->scc_uaddr2 = 0; | |
498 | up->scc_toseq = 0; | |
499 | up->scc_char1 = 0x8000; | |
500 | up->scc_char2 = 0x8000; | |
501 | up->scc_char3 = 0x8000; | |
502 | up->scc_char4 = 0x8000; | |
503 | up->scc_char5 = 0x8000; | |
504 | up->scc_char6 = 0x8000; | |
505 | up->scc_char7 = 0x8000; | |
506 | up->scc_char8 = 0x8000; | |
507 | up->scc_rccm = 0xc0ff; | |
508 | ||
255d28e1 | 509 | /* Set low latency / small fifo. */ |
4a9cbbe8 WD |
510 | sp->scc_gsmrh = SCC_GSMRH_RFW; |
511 | ||
512 | /* Set SCC(x) clock mode to 16x | |
513 | * See 8xx_io/commproc.c for details. | |
514 | * | |
515 | * Wire BRG1 to SCCn | |
516 | */ | |
517 | ||
255d28e1 | 518 | /* Set UART mode, clock divider 16 on Tx and Rx */ |
281e00a3 | 519 | sp->scc_gsmrl &= ~0xF; |
4a9cbbe8 WD |
520 | sp->scc_gsmrl |= |
521 | (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
522 | ||
281e00a3 | 523 | sp->scc_psmr = 0; |
4a9cbbe8 WD |
524 | sp->scc_psmr |= SCU_PSMR_CL; |
525 | ||
255d28e1 | 526 | /* Mask all interrupts and remove anything pending. */ |
4a9cbbe8 WD |
527 | sp->scc_sccm = 0; |
528 | sp->scc_scce = 0xffff; | |
529 | sp->scc_dsr = 0x7e7e; | |
530 | sp->scc_psmr = 0x3000; | |
531 | ||
255d28e1 | 532 | /* Make the first buffer the only buffer. */ |
4a9cbbe8 WD |
533 | tbdf->cbd_sc |= BD_SC_WRAP; |
534 | rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; | |
535 | ||
255d28e1 | 536 | /* Enable transmitter/receiver. */ |
4a9cbbe8 WD |
537 | sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
538 | ||
539 | return (0); | |
540 | } | |
541 | ||
281e00a3 WD |
542 | static void |
543 | scc_putc(const char c) | |
4a9cbbe8 WD |
544 | { |
545 | volatile cbd_t *tbdf; | |
546 | volatile char *buf; | |
547 | volatile scc_uart_t *up; | |
6d0f6bcf | 548 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
549 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
550 | ||
281e00a3 | 551 | #ifdef CONFIG_MODEM_SUPPORT |
281e00a3 WD |
552 | if (gd->be_quiet) |
553 | return; | |
554 | #endif | |
555 | ||
4a9cbbe8 | 556 | if (c == '\n') |
281e00a3 | 557 | scc_putc ('\r'); |
4a9cbbe8 WD |
558 | |
559 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
560 | ||
561 | tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; | |
562 | ||
255d28e1 | 563 | /* Wait for last character to go. */ |
4a9cbbe8 WD |
564 | |
565 | buf = (char *)tbdf->cbd_bufaddr; | |
4a9cbbe8 WD |
566 | |
567 | *buf = c; | |
568 | tbdf->cbd_datlen = 1; | |
569 | tbdf->cbd_sc |= BD_SC_READY; | |
570 | __asm__("eieio"); | |
d0fb80c3 WD |
571 | |
572 | while (tbdf->cbd_sc & BD_SC_READY) { | |
4a9cbbe8 | 573 | __asm__("eieio"); |
d0fb80c3 WD |
574 | WATCHDOG_RESET (); |
575 | } | |
4a9cbbe8 WD |
576 | } |
577 | ||
281e00a3 WD |
578 | static void |
579 | scc_puts (const char *s) | |
580 | { | |
581 | while (*s) { | |
582 | scc_putc (*s++); | |
583 | } | |
584 | } | |
585 | ||
586 | static int | |
587 | scc_getc(void) | |
4a9cbbe8 WD |
588 | { |
589 | volatile cbd_t *rbdf; | |
590 | volatile unsigned char *buf; | |
591 | volatile scc_uart_t *up; | |
6d0f6bcf | 592 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
593 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
594 | unsigned char c; | |
595 | ||
596 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
597 | ||
598 | rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; | |
599 | ||
255d28e1 | 600 | /* Wait for character to show up. */ |
4a9cbbe8 | 601 | buf = (unsigned char *)rbdf->cbd_bufaddr; |
d0fb80c3 | 602 | |
4a9cbbe8 | 603 | while (rbdf->cbd_sc & BD_SC_EMPTY) |
d0fb80c3 WD |
604 | WATCHDOG_RESET (); |
605 | ||
4a9cbbe8 WD |
606 | c = *buf; |
607 | rbdf->cbd_sc |= BD_SC_EMPTY; | |
608 | ||
609 | return(c); | |
610 | } | |
611 | ||
281e00a3 WD |
612 | static int |
613 | scc_tstc(void) | |
4a9cbbe8 WD |
614 | { |
615 | volatile cbd_t *rbdf; | |
616 | volatile scc_uart_t *up; | |
6d0f6bcf | 617 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
4a9cbbe8 WD |
618 | volatile cpm8xx_t *cpmp = &(im->im_cpm); |
619 | ||
620 | up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; | |
621 | ||
622 | rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; | |
623 | ||
624 | return(!(rbdf->cbd_sc & BD_SC_EMPTY)); | |
625 | } | |
626 | ||
281e00a3 WD |
627 | struct serial_device serial_scc_device = |
628 | { | |
90bad891 MV |
629 | .name = "serial_scc", |
630 | .start = scc_init, | |
631 | .stop = NULL, | |
632 | .setbrg = scc_setbrg, | |
633 | .getc = scc_getc, | |
634 | .tstc = scc_tstc, | |
635 | .putc = scc_putc, | |
636 | .puts = scc_puts, | |
281e00a3 WD |
637 | }; |
638 | ||
639 | #endif /* CONFIG_8xx_CONS_SCCx */ | |
4a9cbbe8 | 640 | |
6c768ca7 MF |
641 | __weak struct serial_device *default_serial_console(void) |
642 | { | |
643 | #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) | |
644 | return &serial_smc_device; | |
645 | #else | |
646 | return &serial_scc_device; | |
647 | #endif | |
648 | } | |
649 | ||
f0eb1f61 MV |
650 | void mpc8xx_serial_initialize(void) |
651 | { | |
652 | #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) | |
653 | serial_register(&serial_smc_device); | |
654 | #endif | |
655 | #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ | |
656 | defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) | |
657 | serial_register(&serial_scc_device); | |
658 | #endif | |
659 | } | |
660 | ||
281e00a3 WD |
661 | #ifdef CONFIG_MODEM_SUPPORT |
662 | void disable_putc(void) | |
4a9cbbe8 | 663 | { |
281e00a3 | 664 | gd->be_quiet = 1; |
4a9cbbe8 WD |
665 | } |
666 | ||
281e00a3 WD |
667 | void enable_putc(void) |
668 | { | |
281e00a3 WD |
669 | gd->be_quiet = 0; |
670 | } | |
671 | #endif | |
4a9cbbe8 | 672 | |
4431283c | 673 | #if defined(CONFIG_CMD_KGDB) |
4a9cbbe8 WD |
674 | |
675 | void | |
676 | kgdb_serial_init(void) | |
677 | { | |
281e00a3 WD |
678 | int i = -1; |
679 | ||
1c9a5606 | 680 | if (strcmp(default_serial_console()->name, "serial_smc") == 0) |
281e00a3 | 681 | { |
4a9cbbe8 | 682 | #if defined(CONFIG_8xx_CONS_SMC1) |
281e00a3 | 683 | i = 1; |
4a9cbbe8 | 684 | #elif defined(CONFIG_8xx_CONS_SMC2) |
281e00a3 WD |
685 | i = 2; |
686 | #endif | |
687 | } | |
1c9a5606 | 688 | else if (strcmp(default_serial_console()->name, "serial_scc") == 0) |
281e00a3 WD |
689 | { |
690 | #if defined(CONFIG_8xx_CONS_SCC1) | |
691 | i = 1; | |
4a9cbbe8 | 692 | #elif defined(CONFIG_8xx_CONS_SCC2) |
281e00a3 | 693 | i = 2; |
4a9cbbe8 | 694 | #elif defined(CONFIG_8xx_CONS_SCC3) |
281e00a3 | 695 | i = 3; |
4a9cbbe8 | 696 | #elif defined(CONFIG_8xx_CONS_SCC4) |
281e00a3 | 697 | i = 4; |
4a9cbbe8 | 698 | #endif |
281e00a3 WD |
699 | } |
700 | ||
701 | if (i >= 0) | |
702 | { | |
1c9a5606 | 703 | serial_printf("[on %s%d] ", default_serial_console()->name, i); |
281e00a3 | 704 | } |
4a9cbbe8 WD |
705 | } |
706 | ||
707 | void | |
708 | putDebugChar (int c) | |
709 | { | |
710 | serial_putc (c); | |
711 | } | |
712 | ||
713 | void | |
714 | putDebugStr (const char *str) | |
715 | { | |
716 | serial_puts (str); | |
717 | } | |
718 | ||
719 | int | |
720 | getDebugChar (void) | |
721 | { | |
722 | return serial_getc(); | |
723 | } | |
724 | ||
725 | void | |
726 | kgdb_interruptible (int yes) | |
727 | { | |
728 | return; | |
729 | } | |
068b60a0 | 730 | #endif |
4a9cbbe8 WD |
731 | |
732 | #endif /* CONFIG_8xx_CONS_NONE */ |