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[thirdparty/u-boot.git] / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c
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58e5e9af 1/*
fcea3068 2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
58e5e9af 3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
58e5e9af
KG		 5 */
6
7/*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13#include <common.h>
14#include <asm/fsl_ddr_sdram.h>
15
16#include "ddr.h"
17
e76cd5d4 18#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
e1fd16b6 19
2ed2e912 20static u32 fsl_ddr_get_version(void)
e1fd16b6
YS		 21{
22 ccsr_ddr_t *ddr;
23 u32 ver_major_minor_errata;
24
25 ddr = (void *)_DDR_ADDR;
26 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
27 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
28
29 return ver_major_minor_errata;
30}
31
32unsigned int picos_to_mclk(unsigned int picos);
33
58e5e9af
KG		 34/*
35 * Determine Rtt value.
36 *
37 * This should likely be either board or controller specific.
38 *
c360ceac 39 * Rtt(nominal) - DDR2:
58e5e9af
KG		 40 * 0 = Rtt disabled
41 * 1 = 75 ohm
42 * 2 = 150 ohm
43 * 3 = 50 ohm
c360ceac
DL		 44 * Rtt(nominal) - DDR3:
45 * 0 = Rtt disabled
46 * 1 = 60 ohm
47 * 2 = 120 ohm
48 * 3 = 40 ohm
49 * 4 = 20 ohm
50 * 5 = 30 ohm
58e5e9af
KG		 51 *
52 * FIXME: Apparently 8641 needs a value of 2
53 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
54 *
55 * FIXME: There was some effort down this line earlier:
56 *
57 * unsigned int i;
58 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
59 * if (popts->dimmslot[i].num_valid_cs
60 * && (popts->cs_local_opts[2*i].odt_rd_cfg
61 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
62 * rtt = 2;
63 * break;
64 * }
65 * }
66 */
67static inline int fsl_ddr_get_rtt(void)
68{
69 int rtt;
70
71#if defined(CONFIG_FSL_DDR1)
72 rtt = 0;
73#elif defined(CONFIG_FSL_DDR2)
74 rtt = 3;
75#else
c360ceac 76 rtt = 0;
58e5e9af
KG		 77#endif
78
79 return rtt;
80}
81
c360ceac
DL		 82/*
83 * compute the CAS write latency according to DDR3 spec
84 * CWL = 5 if tCK >= 2.5ns
85 * 6 if 2.5ns > tCK >= 1.875ns
86 * 7 if 1.875ns > tCK >= 1.5ns
87 * 8 if 1.5ns > tCK >= 1.25ns
2bba85f4
YS		 88 * 9 if 1.25ns > tCK >= 1.07ns
89 * 10 if 1.07ns > tCK >= 0.935ns
90 * 11 if 0.935ns > tCK >= 0.833ns
91 * 12 if 0.833ns > tCK >= 0.75ns
c360ceac
DL		 92 */
93static inline unsigned int compute_cas_write_latency(void)
94{
95 unsigned int cwl;
96 const unsigned int mclk_ps = get_memory_clk_period_ps();
97
98 if (mclk_ps >= 2500)
99 cwl = 5;
100 else if (mclk_ps >= 1875)
101 cwl = 6;
102 else if (mclk_ps >= 1500)
103 cwl = 7;
104 else if (mclk_ps >= 1250)
105 cwl = 8;
2bba85f4
YS		 106 else if (mclk_ps >= 1070)
107 cwl = 9;
108 else if (mclk_ps >= 935)
109 cwl = 10;
110 else if (mclk_ps >= 833)
111 cwl = 11;
112 else if (mclk_ps >= 750)
113 cwl = 12;
114 else {
115 cwl = 12;
116 printf("Warning: CWL is out of range\n");
117 }
c360ceac
DL		 118 return cwl;
119}
120
58e5e9af 121/* Chip Select Configuration (CSn_CONFIG) */
5800e7ab 122static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
58e5e9af
KG		 123 const memctl_options_t *popts,
124 const dimm_params_t *dimm_params)
125{
126 unsigned int cs_n_en = 0; /* Chip Select enable */
127 unsigned int intlv_en = 0; /* Memory controller interleave enable */
128 unsigned int intlv_ctl = 0; /* Interleaving control */
129 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
130 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
131 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
132 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
133 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
134 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
5800e7ab 135 int go_config = 0;
58e5e9af
KG		 136
137 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
5800e7ab
YS		 138 switch (i) {
139 case 0:
140 if (dimm_params[dimm_number].n_ranks > 0) {
141 go_config = 1;
58e5e9af 142 /* These fields only available in CS0_CONFIG */
a4c66509
YS		 143 if (!popts->memctl_interleaving)
144 break;
145 switch (popts->memctl_interleaving_mode) {
146 case FSL_DDR_CACHE_LINE_INTERLEAVING:
147 case FSL_DDR_PAGE_INTERLEAVING:
148 case FSL_DDR_BANK_INTERLEAVING:
149 case FSL_DDR_SUPERBANK_INTERLEAVING:
150 intlv_en = popts->memctl_interleaving;
151 intlv_ctl = popts->memctl_interleaving_mode;
152 break;
153 default:
154 break;
155 }
58e5e9af 156 }
5800e7ab
YS		 157 break;
158 case 1:
159 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
160 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
161 go_config = 1;
162 break;
163 case 2:
164 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
cae7c1b5 165 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
5800e7ab
YS		 166 go_config = 1;
167 break;
168 case 3:
169 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
170 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
171 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
172 go_config = 1;
173 break;
174 default:
175 break;
176 }
177 if (go_config) {
178 unsigned int n_banks_per_sdram_device;
179 cs_n_en = 1;
58e5e9af
KG		 180 ap_n_en = popts->cs_local_opts[i].auto_precharge;
181 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
182 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
183 n_banks_per_sdram_device
5800e7ab 184 = dimm_params[dimm_number].n_banks_per_sdram_device;
58e5e9af 185 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
5800e7ab
YS		 186 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
187 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
58e5e9af 188 }
58e5e9af
KG		 189 ddr->cs[i].config = (0
190 | ((cs_n_en & 0x1) << 31)
191 | ((intlv_en & 0x3) << 29)
dbbbb3ab 192 | ((intlv_ctl & 0xf) << 24)
58e5e9af
KG		 193 | ((ap_n_en & 0x1) << 23)
194
195 /* XXX: some implementation only have 1 bit starting at left */
196 | ((odt_rd_cfg & 0x7) << 20)
197
198 /* XXX: Some implementation only have 1 bit starting at left */
199 | ((odt_wr_cfg & 0x7) << 16)
200
201 | ((ba_bits_cs_n & 0x3) << 14)
202 | ((row_bits_cs_n & 0x7) << 8)
203 | ((col_bits_cs_n & 0x7) << 0)
204 );
1f293b41 205 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
58e5e9af
KG		 206}
207
208/* Chip Select Configuration 2 (CSn_CONFIG_2) */
209/* FIXME: 8572 */
210static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
211{
212 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
213
214 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
1f293b41 215 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
58e5e9af
KG		 216}
217
218/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
219
c360ceac 220#if !defined(CONFIG_FSL_DDR1)
123922b1
YS		 221static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
222{
223#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
224 if (dimm_params[0].n_ranks == 4)
225 return 1;
226#endif
227
228#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
229 if ((dimm_params[0].n_ranks == 2) &&
230 (dimm_params[1].n_ranks == 2))
231 return 1;
232
233#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
234 if (dimm_params[0].n_ranks == 4)
235 return 1;
236#endif
237#endif
238 return 0;
239}
240
58e5e9af
KG		 241/*
242 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
243 *
244 * Avoid writing for DDR I. The new PQ38 DDR controller
245 * dreams up non-zero default values to be backwards compatible.
246 */
e1fd16b6 247static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
123922b1
YS		 248 const memctl_options_t *popts,
249 const dimm_params_t *dimm_params)
58e5e9af
KG		 250{
251 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
252 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
253 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
254 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
255 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
256
257 /* Active powerdown exit timing (tXARD and tXARDS). */
258 unsigned char act_pd_exit_mclk;
259 /* Precharge powerdown exit timing (tXP). */
260 unsigned char pre_pd_exit_mclk;
5fb8a8a7 261 /* ODT powerdown exit timing (tAXPD). */
58e5e9af
KG		 262 unsigned char taxpd_mclk;
263 /* Mode register set cycle time (tMRD). */
264 unsigned char tmrd_mclk;
265
e1fd16b6 266#ifdef CONFIG_FSL_DDR3
c360ceac
DL		 267 /*
268 * (tXARD and tXARDS). Empirical?
269 * The DDR3 spec has not tXARD,
270 * we use the tXP instead of it.
271 * tXP=max(3nCK, 7.5ns) for DDR3.
c360ceac 272 * spec has not the tAXPD, we use
5fb8a8a7 273 * tAXPD=1, need design to confirm.
c360ceac 274 */
0a71c92c 275 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
5df4b0ad 276 unsigned int data_rate = get_ddr_freq(0);
c360ceac 277 tmrd_mclk = 4;
99bac479 278 /* set the turnaround time */
123922b1
YS		 279
280 /*
281 * for single quad-rank DIMM and two dual-rank DIMMs
282 * to avoid ODT overlap
283 */
284 if (avoid_odt_overlap(dimm_params)) {
285 twwt_mclk = 2;
286 trrt_mclk = 1;
287 }
288 /* for faster clock, need more time for data setup */
289 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
290
856e4b0d
YS		 291 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
292 twrt_mclk = 1;
e1fd16b6
YS		 293
294 if (popts->dynamic_power == 0) { /* powerdown is not used */
295 act_pd_exit_mclk = 1;
296 pre_pd_exit_mclk = 1;
297 taxpd_mclk = 1;
298 } else {
299 /* act_pd_exit_mclk = tXARD, see above */
300 act_pd_exit_mclk = picos_to_mclk(tXP);
301 /* Mode register MR0[A12] is '1' - fast exit */
302 pre_pd_exit_mclk = act_pd_exit_mclk;
303 taxpd_mclk = 1;
304 }
c360ceac
DL		 305#else /* CONFIG_FSL_DDR2 */
306 /*
307 * (tXARD and tXARDS). Empirical?
308 * tXARD = 2 for DDR2
309 * tXP=2
310 * tAXPD=8
311 */
312 act_pd_exit_mclk = 2;
313 pre_pd_exit_mclk = 2;
314 taxpd_mclk = 8;
58e5e9af 315 tmrd_mclk = 2;
c360ceac 316#endif
58e5e9af 317
23f9670f
YS		 318 if (popts->trwt_override)
319 trwt_mclk = popts->trwt;
320
58e5e9af
KG		 321 ddr->timing_cfg_0 = (0
322 | ((trwt_mclk & 0x3) << 30) /* RWT */
323 | ((twrt_mclk & 0x3) << 28) /* WRT */
324 | ((trrt_mclk & 0x3) << 26) /* RRT */
325 | ((twwt_mclk & 0x3) << 24) /* WWT */
326 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
22ff3d01 327 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
58e5e9af
KG		 328 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
329 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
330 );
331 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
332}
333#endif /* defined(CONFIG_FSL_DDR2) */
334
335/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
336static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
45064adc 337 const memctl_options_t *popts,
c360ceac
DL		 338 const common_timing_params_t *common_dimm,
339 unsigned int cas_latency)
58e5e9af 340{
45064adc
YS		 341 /* Extended precharge to activate interval (tRP) */
342 unsigned int ext_pretoact = 0;
58e5e9af
KG		 343 /* Extended Activate to precharge interval (tRAS) */
344 unsigned int ext_acttopre = 0;
45064adc
YS		 345 /* Extended activate to read/write interval (tRCD) */
346 unsigned int ext_acttorw = 0;
347 /* Extended refresh recovery time (tRFC) */
348 unsigned int ext_refrec;
349 /* Extended MCAS latency from READ cmd */
350 unsigned int ext_caslat = 0;
351 /* Extended last data to precharge interval (tWR) */
352 unsigned int ext_wrrec = 0;
353 /* Control Adjust */
354 unsigned int cntl_adj = 0;
355
356 ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
357 ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
358 ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
359 ext_caslat = (2 * cas_latency - 1) >> 4;
58e5e9af 360 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
45064adc
YS		 361 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
362 ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
363 (popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
c360ceac 364
58e5e9af 365 ddr->timing_cfg_3 = (0
45064adc
YS		 366 | ((ext_pretoact & 0x1) << 28)
367 | ((ext_acttopre & 0x2) << 24)
368 | ((ext_acttorw & 0x1) << 22)
369 | ((ext_refrec & 0x1F) << 16)
370 | ((ext_caslat & 0x3) << 12)
371 | ((ext_wrrec & 0x1) << 8)
58e5e9af
KG		 372 | ((cntl_adj & 0x7) << 0)
373 );
1f293b41 374 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
58e5e9af
KG		 375}
376
377/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
378static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
c360ceac 379 const memctl_options_t *popts,
58e5e9af
KG		 380 const common_timing_params_t *common_dimm,
381 unsigned int cas_latency)
382{
383 /* Precharge-to-activate interval (tRP) */
384 unsigned char pretoact_mclk;
385 /* Activate to precharge interval (tRAS) */
386 unsigned char acttopre_mclk;
387 /* Activate to read/write interval (tRCD) */
388 unsigned char acttorw_mclk;
389 /* CASLAT */
390 unsigned char caslat_ctrl;
391 /* Refresh recovery time (tRFC) ; trfc_low */
392 unsigned char refrec_ctrl;
393 /* Last data to precharge minimum interval (tWR) */
394 unsigned char wrrec_mclk;
395 /* Activate-to-activate interval (tRRD) */
396 unsigned char acttoact_mclk;
397 /* Last write data pair to read command issue interval (tWTR) */
398 unsigned char wrtord_mclk;
f5b6fb7c
YS		 399 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
400 static const u8 wrrec_table[] = {
401 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
58e5e9af
KG		 402
403 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
404 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
405 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
406
407 /*
408 * Translate CAS Latency to a DDR controller field value:
409 *
410 * CAS Lat DDR I DDR II Ctrl
411 * Clocks SPD Bit SPD Bit Value
412 * ------- ------- ------- -----
413 * 1.0 0 0001
414 * 1.5 1 0010
415 * 2.0 2 2 0011
416 * 2.5 3 0100
417 * 3.0 4 3 0101
418 * 3.5 5 0110
419 * 4.0 4 0111
420 * 4.5 1000
421 * 5.0 5 1001
422 */
423#if defined(CONFIG_FSL_DDR1)
424 caslat_ctrl = (cas_latency + 1) & 0x07;
425#elif defined(CONFIG_FSL_DDR2)
426 caslat_ctrl = 2 * cas_latency - 1;
427#else
c360ceac
DL		 428 /*
429 * if the CAS latency more than 8 cycle,
430 * we need set extend bit for it at
431 * TIMING_CFG_3[EXT_CASLAT]
432 */
c360ceac 433 caslat_ctrl = 2 * cas_latency - 1;
58e5e9af
KG		 434#endif
435
436 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
437 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
f5b6fb7c 438
45064adc
YS		 439 if (wrrec_mclk > 16)
440 printf("Error: WRREC doesn't support more than 16 clocks\n");
441 else
442 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
c360ceac
DL		 443 if (popts->OTF_burst_chop_en)
444 wrrec_mclk += 2;
445
58e5e9af 446 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
c360ceac
DL		 447 /*
448 * JEDEC has min requirement for tRRD
449 */
450#if defined(CONFIG_FSL_DDR3)
451 if (acttoact_mclk < 4)
452 acttoact_mclk = 4;
453#endif
58e5e9af 454 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
c360ceac
DL		 455 /*
456 * JEDEC has some min requirements for tWTR
457 */
458#if defined(CONFIG_FSL_DDR2)
459 if (wrtord_mclk < 2)
460 wrtord_mclk = 2;
461#elif defined(CONFIG_FSL_DDR3)
462 if (wrtord_mclk < 4)
463 wrtord_mclk = 4;
464#endif
465 if (popts->OTF_burst_chop_en)
466 wrtord_mclk += 2;
58e5e9af
KG		 467
468 ddr->timing_cfg_1 = (0
80ee3ce6 469 | ((pretoact_mclk & 0x0F) << 28)
58e5e9af 470 | ((acttopre_mclk & 0x0F) << 24)
80ee3ce6 471 | ((acttorw_mclk & 0xF) << 20)
58e5e9af
KG		 472 | ((caslat_ctrl & 0xF) << 16)
473 | ((refrec_ctrl & 0xF) << 12)
80ee3ce6 474 | ((wrrec_mclk & 0x0F) << 8)
57495e4e
YS		 475 | ((acttoact_mclk & 0x0F) << 4)
476 | ((wrtord_mclk & 0x0F) << 0)
58e5e9af 477 );
1f293b41 478 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
58e5e9af
KG		 479}
480
481/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
482static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
483 const memctl_options_t *popts,
484 const common_timing_params_t *common_dimm,
485 unsigned int cas_latency,
486 unsigned int additive_latency)
487{
488 /* Additive latency */
489 unsigned char add_lat_mclk;
490 /* CAS-to-preamble override */
491 unsigned short cpo;
492 /* Write latency */
493 unsigned char wr_lat;
494 /* Read to precharge (tRTP) */
495 unsigned char rd_to_pre;
496 /* Write command to write data strobe timing adjustment */
497 unsigned char wr_data_delay;
498 /* Minimum CKE pulse width (tCKE) */
499 unsigned char cke_pls;
500 /* Window for four activates (tFAW) */
501 unsigned short four_act;
502
503 /* FIXME add check that this must be less than acttorw_mclk */
504 add_lat_mclk = additive_latency;
505 cpo = popts->cpo_override;
506
507#if defined(CONFIG_FSL_DDR1)
508 /*
509 * This is a lie. It should really be 1, but if it is
510 * set to 1, bits overlap into the old controller's
511 * otherwise unused ACSM field. If we leave it 0, then
512 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
513 */
514 wr_lat = 0;
515#elif defined(CONFIG_FSL_DDR2)
6a819783 516 wr_lat = cas_latency - 1;
58e5e9af 517#else
c360ceac 518 wr_lat = compute_cas_write_latency();
58e5e9af
KG		 519#endif
520
521 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
c360ceac
DL		 522 /*
523 * JEDEC has some min requirements for tRTP
524 */
6a819783 525#if defined(CONFIG_FSL_DDR2)
c360ceac
DL		 526 if (rd_to_pre < 2)
527 rd_to_pre = 2;
528#elif defined(CONFIG_FSL_DDR3)
529 if (rd_to_pre < 4)
530 rd_to_pre = 4;
6a819783 531#endif
c360ceac
DL		 532 if (additive_latency)
533 rd_to_pre += additive_latency;
534 if (popts->OTF_burst_chop_en)
535 rd_to_pre += 2; /* according to UM */
536
58e5e9af
KG		 537 wr_data_delay = popts->write_data_delay;
538 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
539 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
540
541 ddr->timing_cfg_2 = (0
22ff3d01 542 | ((add_lat_mclk & 0xf) << 28)
58e5e9af 543 | ((cpo & 0x1f) << 23)
22ff3d01 544 | ((wr_lat & 0xf) << 19)
c360ceac
DL		 545 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
546 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
58e5e9af 547 | ((cke_pls & 0x7) << 6)
22ff3d01 548 | ((four_act & 0x3f) << 0)
58e5e9af 549 );
1f293b41 550 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
58e5e9af
KG		 551}
552
9490ff48
YS		 553/* DDR SDRAM Register Control Word */
554static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
e1fd16b6 555 const memctl_options_t *popts,
9490ff48
YS		 556 const common_timing_params_t *common_dimm)
557{
558 if (common_dimm->all_DIMMs_registered
559 && !common_dimm->all_DIMMs_unbuffered) {
e1fd16b6
YS		 560 if (popts->rcw_override) {
561 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
562 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
563 } else {
564 ddr->ddr_sdram_rcw_1 =
565 common_dimm->rcw[0] << 28 | \
566 common_dimm->rcw[1] << 24 | \
567 common_dimm->rcw[2] << 20 | \
568 common_dimm->rcw[3] << 16 | \
569 common_dimm->rcw[4] << 12 | \
570 common_dimm->rcw[5] << 8 | \
571 common_dimm->rcw[6] << 4 | \
572 common_dimm->rcw[7];
573 ddr->ddr_sdram_rcw_2 =
574 common_dimm->rcw[8] << 28 | \
575 common_dimm->rcw[9] << 24 | \
576 common_dimm->rcw[10] << 20 | \
577 common_dimm->rcw[11] << 16 | \
578 common_dimm->rcw[12] << 12 | \
579 common_dimm->rcw[13] << 8 | \
580 common_dimm->rcw[14] << 4 | \
581 common_dimm->rcw[15];
582 }
9490ff48
YS		 583 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
584 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
585 }
586}
587
58e5e9af
KG		 588/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
589static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
590 const memctl_options_t *popts,
591 const common_timing_params_t *common_dimm)
592{
593 unsigned int mem_en; /* DDR SDRAM interface logic enable */
594 unsigned int sren; /* Self refresh enable (during sleep) */
595 unsigned int ecc_en; /* ECC enable. */
596 unsigned int rd_en; /* Registered DIMM enable */
597 unsigned int sdram_type; /* Type of SDRAM */
598 unsigned int dyn_pwr; /* Dynamic power management mode */
599 unsigned int dbw; /* DRAM dta bus width */
22ff3d01 600 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
58e5e9af
KG		 601 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
602 unsigned int threeT_en; /* Enable 3T timing */
603 unsigned int twoT_en; /* Enable 2T timing */
604 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
605 unsigned int x32_en = 0; /* x32 enable */
606 unsigned int pchb8 = 0; /* precharge bit 8 enable */
607 unsigned int hse; /* Global half strength override */
608 unsigned int mem_halt = 0; /* memory controller halt */
609 unsigned int bi = 0; /* Bypass initialization */
610
611 mem_en = 1;
612 sren = popts->self_refresh_in_sleep;
613 if (common_dimm->all_DIMMs_ECC_capable) {
614 /* Allow setting of ECC only if all DIMMs are ECC. */
615 ecc_en = popts->ECC_mode;
616 } else {
617 ecc_en = 0;
618 }
619
e1fd16b6
YS		 620 if (common_dimm->all_DIMMs_registered
621 && !common_dimm->all_DIMMs_unbuffered) {
622 rd_en = 1;
623 twoT_en = 0;
624 } else {
625 rd_en = 0;
626 twoT_en = popts->twoT_en;
627 }
58e5e9af
KG		 628
629 sdram_type = CONFIG_FSL_SDRAM_TYPE;
630
631 dyn_pwr = popts->dynamic_power;
632 dbw = popts->data_bus_width;
c360ceac
DL		 633 /* 8-beat burst enable DDR-III case
634 * we must clear it when use the on-the-fly mode,
635 * must set it when use the 32-bits bus mode.
636 */
637 if (sdram_type == SDRAM_TYPE_DDR3) {
638 if (popts->burst_length == DDR_BL8)
639 eight_be = 1;
640 if (popts->burst_length == DDR_OTF)
641 eight_be = 0;
642 if (dbw == 0x1)
643 eight_be = 1;
644 }
645
58e5e9af 646 threeT_en = popts->threeT_en;
58e5e9af
KG		 647 ba_intlv_ctl = popts->ba_intlv_ctl;
648 hse = popts->half_strength_driver_enable;
649
650 ddr->ddr_sdram_cfg = (0
651 | ((mem_en & 0x1) << 31)
652 | ((sren & 0x1) << 30)
653 | ((ecc_en & 0x1) << 29)
654 | ((rd_en & 0x1) << 28)
655 | ((sdram_type & 0x7) << 24)
656 | ((dyn_pwr & 0x1) << 21)
657 | ((dbw & 0x3) << 19)
658 | ((eight_be & 0x1) << 18)
659 | ((ncap & 0x1) << 17)
660 | ((threeT_en & 0x1) << 16)
661 | ((twoT_en & 0x1) << 15)
662 | ((ba_intlv_ctl & 0x7F) << 8)
663 | ((x32_en & 0x1) << 5)
664 | ((pchb8 & 0x1) << 4)
665 | ((hse & 0x1) << 3)
666 | ((mem_halt & 0x1) << 1)
667 | ((bi & 0x1) << 0)
668 );
1f293b41 669 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
58e5e9af
KG		 670}
671
672/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
673static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
e1fd16b6
YS		 674 const memctl_options_t *popts,
675 const unsigned int unq_mrs_en)
58e5e9af
KG		 676{
677 unsigned int frc_sr = 0; /* Force self refresh */
678 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
679 unsigned int dll_rst_dis; /* DLL reset disable */
680 unsigned int dqs_cfg; /* DQS configuration */
cae7c1b5 681 unsigned int odt_cfg = 0; /* ODT configuration */
58e5e9af 682 unsigned int num_pr; /* Number of posted refreshes */
57495e4e 683 unsigned int slow = 0; /* DDR will be run less than 1250 */
58e5e9af
KG		 684 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
685 unsigned int ap_en; /* Address Parity Enable */
686 unsigned int d_init; /* DRAM data initialization */
687 unsigned int rcw_en = 0; /* Register Control Word Enable */
688 unsigned int md_en = 0; /* Mirrored DIMM Enable */
5800e7ab 689 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
cae7c1b5 690 int i;
58e5e9af
KG		 691
692 dll_rst_dis = 1; /* Make this configurable */
693 dqs_cfg = popts->DQS_config;
cae7c1b5
YS		 694 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
695 if (popts->cs_local_opts[i].odt_rd_cfg
696 || popts->cs_local_opts[i].odt_wr_cfg) {
697 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
698 break;
699 }
58e5e9af
KG		 700 }
701
702 num_pr = 1; /* Make this configurable */
703
704 /*
705 * 8572 manual says
706 * {TIMING_CFG_1[PRETOACT]
707 * + [DDR_SDRAM_CFG_2[NUM_PR]
708 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
709 * << DDR_SDRAM_INTERVAL[REFINT]
710 */
c360ceac
DL		 711#if defined(CONFIG_FSL_DDR3)
712 obc_cfg = popts->OTF_burst_chop_en;
713#else
714 obc_cfg = 0;
715#endif
58e5e9af 716
57495e4e
YS		 717#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
718 slow = get_ddr_freq(0) < 1249000000;
719#endif
720
e1fd16b6
YS		 721 if (popts->registered_dimm_en) {
722 rcw_en = 1;
723 ap_en = popts->ap_en;
724 } else {
e1fd16b6
YS		 725 ap_en = 0;
726 }
58e5e9af
KG		 727
728#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
729 /* Use the DDR controller to auto initialize memory. */
e1fd16b6 730 d_init = popts->ECC_init_using_memctl;
58e5e9af
KG		 731 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
732 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
733#else
734 /* Memory will be initialized via DMA, or not at all. */
735 d_init = 0;
736#endif
737
c360ceac
DL		 738#if defined(CONFIG_FSL_DDR3)
739 md_en = popts->mirrored_dimm;
740#endif
5800e7ab 741 qd_en = popts->quad_rank_present ? 1 : 0;
58e5e9af
KG		 742 ddr->ddr_sdram_cfg_2 = (0
743 | ((frc_sr & 0x1) << 31)
744 | ((sr_ie & 0x1) << 30)
745 | ((dll_rst_dis & 0x1) << 29)
746 | ((dqs_cfg & 0x3) << 26)
747 | ((odt_cfg & 0x3) << 21)
748 | ((num_pr & 0xf) << 12)
57495e4e 749 | ((slow & 1) << 11)
5800e7ab 750 | (qd_en << 9)
e1fd16b6 751 | (unq_mrs_en << 8)
58e5e9af
KG		 752 | ((obc_cfg & 0x1) << 6)
753 | ((ap_en & 0x1) << 5)
754 | ((d_init & 0x1) << 4)
755 | ((rcw_en & 0x1) << 2)
756 | ((md_en & 0x1) << 0)
757 );
1f293b41 758 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
58e5e9af
KG		 759}
760
761/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1aa3d08a 762static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
e1fd16b6
YS		 763 const memctl_options_t *popts,
764 const unsigned int unq_mrs_en)
58e5e9af
KG		 765{
766 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
767 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
768
c360ceac 769#if defined(CONFIG_FSL_DDR3)
92966835 770 int i;
1aa3d08a 771 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
c360ceac
DL		 772 unsigned int srt = 0; /* self-refresh temerature, normal range */
773 unsigned int asr = 0; /* auto self-refresh disable */
774 unsigned int cwl = compute_cas_write_latency() - 5;
775 unsigned int pasr = 0; /* partial array self refresh disable */
776
1aa3d08a
DL		 777 if (popts->rtt_override)
778 rtt_wr = popts->rtt_wr_override_value;
e1fd16b6
YS		 779 else
780 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
c360ceac
DL		 781 esdmode2 = (0
782 | ((rtt_wr & 0x3) << 9)
783 | ((srt & 0x1) << 7)
784 | ((asr & 0x1) << 6)
785 | ((cwl & 0x7) << 3)
786 | ((pasr & 0x7) << 0));
787#endif
58e5e9af
KG		 788 ddr->ddr_sdram_mode_2 = (0
789 | ((esdmode2 & 0xFFFF) << 16)
790 | ((esdmode3 & 0xFFFF) << 0)
791 );
1f293b41 792 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
e1fd16b6
YS		 793
794#ifdef CONFIG_FSL_DDR3
795 if (unq_mrs_en) { /* unique mode registers are supported */
dea7f887 796 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
e1fd16b6
YS		 797 if (popts->rtt_override)
798 rtt_wr = popts->rtt_wr_override_value;
799 else
800 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
801
802 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
803 esdmode2 |= (rtt_wr & 0x3) << 9;
804 switch (i) {
805 case 1:
806 ddr->ddr_sdram_mode_4 = (0
807 | ((esdmode2 & 0xFFFF) << 16)
808 | ((esdmode3 & 0xFFFF) << 0)
809 );
810 break;
811 case 2:
812 ddr->ddr_sdram_mode_6 = (0
813 | ((esdmode2 & 0xFFFF) << 16)
814 | ((esdmode3 & 0xFFFF) << 0)
815 );
816 break;
817 case 3:
818 ddr->ddr_sdram_mode_8 = (0
819 | ((esdmode2 & 0xFFFF) << 16)
820 | ((esdmode3 & 0xFFFF) << 0)
821 );
822 break;
823 }
824 }
825 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
826 ddr->ddr_sdram_mode_4);
827 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
828 ddr->ddr_sdram_mode_6);
829 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
830 ddr->ddr_sdram_mode_8);
831 }
832#endif
58e5e9af
KG		 833}
834
835/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
836static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
837 const memctl_options_t *popts,
838 const common_timing_params_t *common_dimm)
839{
840 unsigned int refint; /* Refresh interval */
841 unsigned int bstopre; /* Precharge interval */
842
843 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
844
845 bstopre = popts->bstopre;
846
847 /* refint field used 0x3FFF in earlier controllers */
848 ddr->ddr_sdram_interval = (0
849 | ((refint & 0xFFFF) << 16)
850 | ((bstopre & 0x3FFF) << 0)
851 );
1f293b41 852 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
58e5e9af
KG		 853}
854
c360ceac
DL		 855#if defined(CONFIG_FSL_DDR3)
856/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
857static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
858 const memctl_options_t *popts,
859 const common_timing_params_t *common_dimm,
860 unsigned int cas_latency,
e1fd16b6
YS		 861 unsigned int additive_latency,
862 const unsigned int unq_mrs_en)
c360ceac
DL		 863{
864 unsigned short esdmode; /* Extended SDRAM mode */
865 unsigned short sdmode; /* SDRAM mode */
866
867 /* Mode Register - MR1 */
868 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
869 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
870 unsigned int rtt;
871 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
872 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
e1fd16b6 873 unsigned int dic = 0; /* Output driver impedance, 40ohm */
c360ceac
DL		 874 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
875 1=Disable (Test/Debug) */
876
877 /* Mode Register - MR0 */
878 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
fcea3068 879 unsigned int wr = 0; /* Write Recovery */
c360ceac
DL		 880 unsigned int dll_rst; /* DLL Reset */
881 unsigned int mode; /* Normal=0 or Test=1 */
882 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
883 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
884 unsigned int bt;
885 unsigned int bl; /* BL: Burst Length */
886
887 unsigned int wr_mclk;
f5b6fb7c
YS		 888 /*
889 * DDR_SDRAM_MODE doesn't support 9,11,13,15
890 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
891 * for this table
892 */
893 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
c360ceac
DL		 894
895 const unsigned int mclk_ps = get_memory_clk_period_ps();
e1fd16b6 896 int i;
c360ceac 897
c360ceac
DL		 898 if (popts->rtt_override)
899 rtt = popts->rtt_override_value;
e1fd16b6
YS		 900 else
901 rtt = popts->cs_local_opts[0].odt_rtt_norm;
c360ceac
DL		 902
903 if (additive_latency == (cas_latency - 1))
904 al = 1;
905 if (additive_latency == (cas_latency - 2))
906 al = 2;
907
e1fd16b6
YS		 908 if (popts->quad_rank_present)
909 dic = 1; /* output driver impedance 240/7 ohm */
910
c360ceac
DL		 911 /*
912 * The esdmode value will also be used for writing
913 * MR1 during write leveling for DDR3, although the
914 * bits specifically related to the write leveling
915 * scheme will be handled automatically by the DDR
916 * controller. so we set the wrlvl_en = 0 here.
917 */
918 esdmode = (0
919 | ((qoff & 0x1) << 12)
920 | ((tdqs_en & 0x1) << 11)
6d8565a1 921 | ((rtt & 0x4) << 7) /* rtt field is split */
c360ceac 922 | ((wrlvl_en & 0x1) << 7)
6d8565a1
KG		 923 | ((rtt & 0x2) << 5) /* rtt field is split */
924 | ((dic & 0x2) << 4) /* DIC field is split */
c360ceac 925 | ((al & 0x3) << 3)
6d8565a1 926 | ((rtt & 0x1) << 2) /* rtt field is split */
c360ceac
DL		 927 | ((dic & 0x1) << 1) /* DIC field is split */
928 | ((dll_en & 0x1) << 0)
929 );
930
931 /*
932 * DLL control for precharge PD
933 * 0=slow exit DLL off (tXPDLL)
934 * 1=fast exit DLL on (tXP)
935 */
936 dll_on = 1;
f5b6fb7c 937
c360ceac 938 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
fcea3068
YS		 939 if (wr_mclk <= 16) {
940 wr = wr_table[wr_mclk - 5];
941 } else {
942 printf("Error: unsupported write recovery for mode register "
943 "wr_mclk = %d\n", wr_mclk);
944 }
f5b6fb7c 945
c360ceac
DL		 946 dll_rst = 0; /* dll no reset */
947 mode = 0; /* normal mode */
948
949 /* look up table to get the cas latency bits */
fcea3068
YS		 950 if (cas_latency >= 5 && cas_latency <= 16) {
951 unsigned char cas_latency_table[] = {
c360ceac
DL		 952 0x2, /* 5 clocks */
953 0x4, /* 6 clocks */
954 0x6, /* 7 clocks */
955 0x8, /* 8 clocks */
956 0xa, /* 9 clocks */
957 0xc, /* 10 clocks */
fcea3068
YS		 958 0xe, /* 11 clocks */
959 0x1, /* 12 clocks */
960 0x3, /* 13 clocks */
961 0x5, /* 14 clocks */
962 0x7, /* 15 clocks */
963 0x9, /* 16 clocks */
c360ceac
DL		 964 };
965 caslat = cas_latency_table[cas_latency - 5];
fcea3068
YS		 966 } else {
967 printf("Error: unsupported cas latency for mode register\n");
c360ceac 968 }
fcea3068 969
c360ceac
DL		 970 bt = 0; /* Nibble sequential */
971
972 switch (popts->burst_length) {
973 case DDR_BL8:
974 bl = 0;
975 break;
976 case DDR_OTF:
977 bl = 1;
978 break;
979 case DDR_BC4:
980 bl = 2;
981 break;
982 default:
983 printf("Error: invalid burst length of %u specified. "
984 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
985 popts->burst_length);
986 bl = 1;
987 break;
988 }
989
990 sdmode = (0
991 | ((dll_on & 0x1) << 12)
992 | ((wr & 0x7) << 9)
993 | ((dll_rst & 0x1) << 8)
994 | ((mode & 0x1) << 7)
995 | (((caslat >> 1) & 0x7) << 4)
996 | ((bt & 0x1) << 3)
fcea3068 997 | ((caslat & 1) << 2)
c360ceac
DL		 998 | ((bl & 0x3) << 0)
999 );
1000
1001 ddr->ddr_sdram_mode = (0
1002 | ((esdmode & 0xFFFF) << 16)
1003 | ((sdmode & 0xFFFF) << 0)
1004 );
1005
1006 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
e1fd16b6
YS		 1007
1008 if (unq_mrs_en) { /* unique mode registers are supported */
dea7f887 1009 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
e1fd16b6
YS		 1010 if (popts->rtt_override)
1011 rtt = popts->rtt_override_value;
1012 else
1013 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1014
1015 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1016 esdmode |= (0
1017 | ((rtt & 0x4) << 7) /* rtt field is split */
1018 | ((rtt & 0x2) << 5) /* rtt field is split */
1019 | ((rtt & 0x1) << 2) /* rtt field is split */
1020 );
1021 switch (i) {
1022 case 1:
1023 ddr->ddr_sdram_mode_3 = (0
1024 | ((esdmode & 0xFFFF) << 16)
1025 | ((sdmode & 0xFFFF) << 0)
1026 );
1027 break;
1028 case 2:
1029 ddr->ddr_sdram_mode_5 = (0
1030 | ((esdmode & 0xFFFF) << 16)
1031 | ((sdmode & 0xFFFF) << 0)
1032 );
1033 break;
1034 case 3:
1035 ddr->ddr_sdram_mode_7 = (0
1036 | ((esdmode & 0xFFFF) << 16)
1037 | ((sdmode & 0xFFFF) << 0)
1038 );
1039 break;
1040 }
1041 }
1042 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1043 ddr->ddr_sdram_mode_3);
1044 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1045 ddr->ddr_sdram_mode_5);
1046 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1047 ddr->ddr_sdram_mode_5);
1048 }
c360ceac
DL		 1049}
1050
1051#else /* !CONFIG_FSL_DDR3 */
1052
58e5e9af
KG		 1053/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1054static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1055 const memctl_options_t *popts,
1056 const common_timing_params_t *common_dimm,
1057 unsigned int cas_latency,
e1fd16b6
YS		 1058 unsigned int additive_latency,
1059 const unsigned int unq_mrs_en)
58e5e9af
KG		 1060{
1061 unsigned short esdmode; /* Extended SDRAM mode */
1062 unsigned short sdmode; /* SDRAM mode */
1063
1064 /*
1065 * FIXME: This ought to be pre-calculated in a
1066 * technology-specific routine,
1067 * e.g. compute_DDR2_mode_register(), and then the
1068 * sdmode and esdmode passed in as part of common_dimm.
1069 */
1070
1071 /* Extended Mode Register */
1072 unsigned int mrs = 0; /* Mode Register Set */
1073 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1074 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1075 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1076 unsigned int ocd = 0; /* 0x0=OCD not supported,
1077 0x7=OCD default state */
1078 unsigned int rtt;
1079 unsigned int al; /* Posted CAS# additive latency (AL) */
1080 unsigned int ods = 0; /* Output Drive Strength:
1081 0 = Full strength (18ohm)
1082 1 = Reduced strength (4ohm) */
1083 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1084 1=Disable (Test/Debug) */
1085
1086 /* Mode Register (MR) */
1087 unsigned int mr; /* Mode Register Definition */
1088 unsigned int pd; /* Power-Down Mode */
1089 unsigned int wr; /* Write Recovery */
1090 unsigned int dll_res; /* DLL Reset */
1091 unsigned int mode; /* Normal=0 or Test=1 */
302e52e0 1092 unsigned int caslat = 0;/* CAS# latency */
58e5e9af
KG		 1093 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1094 unsigned int bt;
1095 unsigned int bl; /* BL: Burst Length */
1096
1097#if defined(CONFIG_FSL_DDR2)
1098 const unsigned int mclk_ps = get_memory_clk_period_ps();
1099#endif
cae7c1b5 1100 dqs_en = !popts->DQS_config;
58e5e9af
KG		 1101 rtt = fsl_ddr_get_rtt();
1102
1103 al = additive_latency;
1104
1105 esdmode = (0
1106 | ((mrs & 0x3) << 14)
1107 | ((outputs & 0x1) << 12)
1108 | ((rdqs_en & 0x1) << 11)
1109 | ((dqs_en & 0x1) << 10)
1110 | ((ocd & 0x7) << 7)
1111 | ((rtt & 0x2) << 5) /* rtt field is split */
1112 | ((al & 0x7) << 3)
1113 | ((rtt & 0x1) << 2) /* rtt field is split */
1114 | ((ods & 0x1) << 1)
1115 | ((dll_en & 0x1) << 0)
1116 );
1117
1118 mr = 0; /* FIXME: CHECKME */
1119
1120 /*
1121 * 0 = Fast Exit (Normal)
1122 * 1 = Slow Exit (Low Power)
1123 */
1124 pd = 0;
1125
1126#if defined(CONFIG_FSL_DDR1)
1127 wr = 0; /* Historical */
1128#elif defined(CONFIG_FSL_DDR2)
1129 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
58e5e9af
KG		 1130#endif
1131 dll_res = 0;
1132 mode = 0;
1133
1134#if defined(CONFIG_FSL_DDR1)
1135 if (1 <= cas_latency && cas_latency <= 4) {
1136 unsigned char mode_caslat_table[4] = {
1137 0x5, /* 1.5 clocks */
1138 0x2, /* 2.0 clocks */
1139 0x6, /* 2.5 clocks */
1140 0x3 /* 3.0 clocks */
1141 };
302e52e0
KG		 1142 caslat = mode_caslat_table[cas_latency - 1];
1143 } else {
1144 printf("Warning: unknown cas_latency %d\n", cas_latency);
58e5e9af
KG		 1145 }
1146#elif defined(CONFIG_FSL_DDR2)
1147 caslat = cas_latency;
58e5e9af
KG		 1148#endif
1149 bt = 0;
1150
1151 switch (popts->burst_length) {
c360ceac 1152 case DDR_BL4:
58e5e9af
KG		 1153 bl = 2;
1154 break;
c360ceac 1155 case DDR_BL8:
58e5e9af
KG		 1156 bl = 3;
1157 break;
1158 default:
1159 printf("Error: invalid burst length of %u specified. "
1160 " Defaulting to 4 beats.\n",
1161 popts->burst_length);
1162 bl = 2;
1163 break;
1164 }
1165
1166 sdmode = (0
1167 | ((mr & 0x3) << 14)
1168 | ((pd & 0x1) << 12)
1169 | ((wr & 0x7) << 9)
1170 | ((dll_res & 0x1) << 8)
1171 | ((mode & 0x1) << 7)
1172 | ((caslat & 0x7) << 4)
1173 | ((bt & 0x1) << 3)
1174 | ((bl & 0x7) << 0)
1175 );
1176
1177 ddr->ddr_sdram_mode = (0
1178 | ((esdmode & 0xFFFF) << 16)
1179 | ((sdmode & 0xFFFF) << 0)
1180 );
1f293b41 1181 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
58e5e9af 1182}
c360ceac 1183#endif
58e5e9af
KG		 1184
1185/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1186static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1187{
1188 unsigned int init_value; /* Initialization value */
1189
5b933943
AG		 1190#ifdef CONFIG_MEM_INIT_VALUE
1191 init_value = CONFIG_MEM_INIT_VALUE;
1192#else
58e5e9af 1193 init_value = 0xDEADBEEF;
5b933943 1194#endif
58e5e9af
KG		 1195 ddr->ddr_data_init = init_value;
1196}
1197
1198/*
1199 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1200 * The old controller on the 8540/60 doesn't have this register.
1201 * Hope it's OK to set it (to 0) anyway.
1202 */
1203static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1204 const memctl_options_t *popts)
1205{
1206 unsigned int clk_adjust; /* Clock adjust */
1207
1208 clk_adjust = popts->clk_adjust;
1209 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
9490ff48 1210 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
58e5e9af
KG		 1211}
1212
1213/* DDR Initialization Address (DDR_INIT_ADDR) */
1214static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1215{
1216 unsigned int init_addr = 0; /* Initialization address */
1217
1218 ddr->ddr_init_addr = init_addr;
1219}
1220
1221/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1222static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1223{
1224 unsigned int uia = 0; /* Use initialization address */
1225 unsigned int init_ext_addr = 0; /* Initialization address */
1226
1227 ddr->ddr_init_ext_addr = (0
1228 | ((uia & 0x1) << 31)
1229 | (init_ext_addr & 0xF)
1230 );
1231}
1232
1233/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
ec145e87
DL		 1234static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1235 const memctl_options_t *popts)
58e5e9af
KG		 1236{
1237 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1238 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1239 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1240 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1241 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1242
c360ceac 1243#if defined(CONFIG_FSL_DDR3)
ec145e87
DL		 1244 if (popts->burst_length == DDR_BL8) {
1245 /* We set BL/2 for fixed BL8 */
1246 rrt = 0; /* BL/2 clocks */
1247 wwt = 0; /* BL/2 clocks */
1248 } else {
1249 /* We need to set BL/2 + 2 to BC4 and OTF */
1250 rrt = 2; /* BL/2 + 2 clocks */
1251 wwt = 2; /* BL/2 + 2 clocks */
1252 }
c360ceac
DL		 1253 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1254#endif
58e5e9af
KG		 1255 ddr->timing_cfg_4 = (0
1256 | ((rwt & 0xf) << 28)
1257 | ((wrt & 0xf) << 24)
1258 | ((rrt & 0xf) << 20)
1259 | ((wwt & 0xf) << 16)
1260 | (dll_lock & 0x3)
1261 );
1f293b41 1262 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
58e5e9af
KG		 1263}
1264
1265/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
e1fd16b6 1266static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
58e5e9af
KG		 1267{
1268 unsigned int rodt_on = 0; /* Read to ODT on */
1269 unsigned int rodt_off = 0; /* Read to ODT off */
1270 unsigned int wodt_on = 0; /* Write to ODT on */
1271 unsigned int wodt_off = 0; /* Write to ODT off */
1272
c360ceac 1273#if defined(CONFIG_FSL_DDR3)
e1fd16b6
YS		 1274 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1275 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
c360ceac 1276 rodt_off = 4; /* 4 clocks */
5fb8a8a7 1277 wodt_on = 1; /* 1 clocks */
c360ceac
DL		 1278 wodt_off = 4; /* 4 clocks */
1279#endif
1280
58e5e9af 1281 ddr->timing_cfg_5 = (0
22ff3d01
DL		 1282 | ((rodt_on & 0x1f) << 24)
1283 | ((rodt_off & 0x7) << 20)
1284 | ((wodt_on & 0x1f) << 12)
1285 | ((wodt_off & 0x7) << 8)
58e5e9af 1286 );
1f293b41 1287 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
58e5e9af
KG		 1288}
1289
1290/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
c360ceac 1291static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
58e5e9af 1292{
58e5e9af
KG		 1293 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1294 /* Normal Operation Full Calibration Time (tZQoper) */
1295 unsigned int zqoper = 0;
1296 /* Normal Operation Short Calibration Time (tZQCS) */
1297 unsigned int zqcs = 0;
1298
c360ceac
DL		 1299 if (zq_en) {
1300 zqinit = 9; /* 512 clocks */
1301 zqoper = 8; /* 256 clocks */
1302 zqcs = 6; /* 64 clocks */
1303 }
1304
58e5e9af
KG		 1305 ddr->ddr_zq_cntl = (0
1306 | ((zq_en & 0x1) << 31)
1307 | ((zqinit & 0xF) << 24)
1308 | ((zqoper & 0xF) << 16)
1309 | ((zqcs & 0xF) << 8)
1310 );
e1fd16b6 1311 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
58e5e9af
KG		 1312}
1313
1314/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
bdc9f7b5
DL		 1315static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1316 const memctl_options_t *popts)
58e5e9af 1317{
58e5e9af
KG		 1318 /*
1319 * First DQS pulse rising edge after margining mode
1320 * is programmed (tWL_MRD)
1321 */
1322 unsigned int wrlvl_mrd = 0;
1323 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1324 unsigned int wrlvl_odten = 0;
1325 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1326 unsigned int wrlvl_dqsen = 0;
1327 /* WRLVL_SMPL: Write leveling sample time */
1328 unsigned int wrlvl_smpl = 0;
1329 /* WRLVL_WLR: Write leveling repeition time */
1330 unsigned int wrlvl_wlr = 0;
1331 /* WRLVL_START: Write leveling start time */
1332 unsigned int wrlvl_start = 0;
1333
c360ceac
DL		 1334 /* suggest enable write leveling for DDR3 due to fly-by topology */
1335 if (wrlvl_en) {
1336 /* tWL_MRD min = 40 nCK, we set it 64 */
1337 wrlvl_mrd = 0x6;
1338 /* tWL_ODTEN 128 */
1339 wrlvl_odten = 0x7;
1340 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1341 wrlvl_dqsen = 0x5;
1342 /*
bdc9f7b5
DL		 1343 * Write leveling sample time at least need 6 clocks
1344 * higher than tWLO to allow enough time for progagation
1345 * delay and sampling the prime data bits.
c360ceac
DL		 1346 */
1347 wrlvl_smpl = 0xf;
1348 /*
1349 * Write leveling repetition time
1350 * at least tWLO + 6 clocks clocks
5fb8a8a7 1351 * we set it 64
c360ceac 1352 */
5fb8a8a7 1353 wrlvl_wlr = 0x6;
c360ceac
DL		 1354 /*
1355 * Write leveling start time
1356 * The value use for the DQS_ADJUST for the first sample
e1fd16b6
YS		 1357 * when write leveling is enabled. It probably needs to be
1358 * overriden per platform.
c360ceac
DL		 1359 */
1360 wrlvl_start = 0x8;
bdc9f7b5
DL		 1361 /*
1362 * Override the write leveling sample and start time
1363 * according to specific board
1364 */
1365 if (popts->wrlvl_override) {
1366 wrlvl_smpl = popts->wrlvl_sample;
1367 wrlvl_start = popts->wrlvl_start;
1368 }
c360ceac
DL		 1369 }
1370
58e5e9af
KG		 1371 ddr->ddr_wrlvl_cntl = (0
1372 | ((wrlvl_en & 0x1) << 31)
1373 | ((wrlvl_mrd & 0x7) << 24)
1374 | ((wrlvl_odten & 0x7) << 20)
1375 | ((wrlvl_dqsen & 0x7) << 16)
1376 | ((wrlvl_smpl & 0xf) << 12)
1377 | ((wrlvl_wlr & 0x7) << 8)
22ff3d01 1378 | ((wrlvl_start & 0x1F) << 0)
58e5e9af 1379 );
e1fd16b6 1380 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
57495e4e
YS		 1381 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1382 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1383 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1384 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1385
58e5e9af
KG		 1386}
1387
1388/* DDR Self Refresh Counter (DDR_SR_CNTR) */
22cca7e1 1389static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
58e5e9af 1390{
22cca7e1 1391 /* Self Refresh Idle Threshold */
58e5e9af
KG		 1392 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1393}
1394
7fd101c9
YS		 1395static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1396{
1397 if (popts->addr_hash) {
1398 ddr->ddr_eor = 0x40000000; /* address hash enable */
c2a63f48 1399 puts("Address hashing enabled.\n");
7fd101c9
YS		 1400 }
1401}
1402
e1fd16b6
YS		 1403static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1404{
1405 ddr->ddr_cdr1 = popts->ddr_cdr1;
1406 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1407}
1408
57495e4e
YS		 1409static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1410{
1411 ddr->ddr_cdr2 = popts->ddr_cdr2;
1412 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1413}
1414
58e5e9af
KG		 1415unsigned int
1416check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1417{
1418 unsigned int res = 0;
1419
1420 /*
1421 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1422 * not set at the same time.
1423 */
1424 if (ddr->ddr_sdram_cfg & 0x10000000
1425 && ddr->ddr_sdram_cfg & 0x00008000) {
1426 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1427 " should not be set at the same time.\n");
1428 res++;
1429 }
1430
1431 return res;
1432}
1433
1434unsigned int
1435compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1436 fsl_ddr_cfg_regs_t *ddr,
1437 const common_timing_params_t *common_dimm,
1438 const dimm_params_t *dimm_params,
fc0c2b6f
HW		 1439 unsigned int dbw_cap_adj,
1440 unsigned int size_only)
58e5e9af
KG		 1441{
1442 unsigned int i;
1443 unsigned int cas_latency;
1444 unsigned int additive_latency;
22cca7e1 1445 unsigned int sr_it;
c360ceac
DL		 1446 unsigned int zq_en;
1447 unsigned int wrlvl_en;
e1fd16b6
YS		 1448 unsigned int ip_rev = 0;
1449 unsigned int unq_mrs_en = 0;
58edbc9c 1450 int cs_en = 1;
58e5e9af
KG		 1451
1452 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1453
1454 if (common_dimm == NULL) {
1455 printf("Error: subset DIMM params struct null pointer\n");
1456 return 1;
1457 }
1458
1459 /*
1460 * Process overrides first.
1461 *
1462 * FIXME: somehow add dereated caslat to this
1463 */
1464 cas_latency = (popts->cas_latency_override)
1465 ? popts->cas_latency_override_value
1466 : common_dimm->lowest_common_SPD_caslat;
1467
1468 additive_latency = (popts->additive_latency_override)
1469 ? popts->additive_latency_override_value
1470 : common_dimm->additive_latency;
1471
22cca7e1
DL		 1472 sr_it = (popts->auto_self_refresh_en)
1473 ? popts->sr_it
1474 : 0;
c360ceac
DL		 1475 /* ZQ calibration */
1476 zq_en = (popts->zq_en) ? 1 : 0;
1477 /* write leveling */
1478 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
22cca7e1 1479
58e5e9af
KG		 1480 /* Chip Select Memory Bounds (CSn_BNDS) */
1481 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
a4c66509 1482 unsigned long long ea, sa;
076bff8f
YS		 1483 unsigned int cs_per_dimm
1484 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1485 unsigned int dimm_number
1486 = i / cs_per_dimm;
1487 unsigned long long rank_density
a4c66509 1488 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
076bff8f 1489
076bff8f 1490 if (dimm_params[dimm_number].n_ranks == 0) {
58e5e9af 1491 debug("Skipping setup of CS%u "
5800e7ab 1492 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
58e5e9af
KG		 1493 continue;
1494 }
a4c66509 1495 if (popts->memctl_interleaving) {
076bff8f 1496 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
a4c66509
YS		 1497 case FSL_DDR_CS0_CS1_CS2_CS3:
1498 break;
076bff8f
YS		 1499 case FSL_DDR_CS0_CS1:
1500 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
58edbc9c
YS		 1501 if (i > 1)
1502 cs_en = 0;
076bff8f
YS		 1503 break;
1504 case FSL_DDR_CS2_CS3:
a4c66509 1505 default:
58edbc9c
YS		 1506 if (i > 0)
1507 cs_en = 0;
076bff8f 1508 break;
076bff8f 1509 }
a4c66509 1510 sa = common_dimm->base_address;
123922b1 1511 ea = sa + common_dimm->total_mem - 1;
a4c66509 1512 } else if (!popts->memctl_interleaving) {
58e5e9af
KG		 1513 /*
1514 * If memory interleaving between controllers is NOT
1515 * enabled, the starting address for each memory
1516 * controller is distinct. However, because rank
1517 * interleaving is enabled, the starting and ending
1518 * addresses of the total memory on that memory
1519 * controller needs to be programmed into its
1520 * respective CS0_BNDS.
1521 */
dbbbb3ab
HW		 1522 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1523 case FSL_DDR_CS0_CS1_CS2_CS3:
dbbbb3ab 1524 sa = common_dimm->base_address;
123922b1 1525 ea = sa + common_dimm->total_mem - 1;
dbbbb3ab
HW		 1526 break;
1527 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
a4c66509 1528 if ((i >= 2) && (dimm_number == 0)) {
076bff8f 1529 sa = dimm_params[dimm_number].base_address +
a4c66509
YS		 1530 2 * rank_density;
1531 ea = sa + 2 * rank_density - 1;
076bff8f
YS		 1532 } else {
1533 sa = dimm_params[dimm_number].base_address;
a4c66509 1534 ea = sa + 2 * rank_density - 1;
dbbbb3ab
HW		 1535 }
1536 break;
1537 case FSL_DDR_CS0_CS1:
076bff8f
YS		 1538 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1539 sa = dimm_params[dimm_number].base_address;
a4c66509
YS		 1540 ea = sa + rank_density - 1;
1541 if (i != 1)
1542 sa += (i % cs_per_dimm) * rank_density;
1543 ea += (i % cs_per_dimm) * rank_density;
076bff8f
YS		 1544 } else {
1545 sa = 0;
1546 ea = 0;
1547 }
1548 if (i == 0)
a4c66509 1549 ea += rank_density;
dbbbb3ab
HW		 1550 break;
1551 case FSL_DDR_CS2_CS3:
076bff8f
YS		 1552 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1553 sa = dimm_params[dimm_number].base_address;
a4c66509
YS		 1554 ea = sa + rank_density - 1;
1555 if (i != 3)
1556 sa += (i % cs_per_dimm) * rank_density;
1557 ea += (i % cs_per_dimm) * rank_density;
076bff8f
YS		 1558 } else {
1559 sa = 0;
1560 ea = 0;
dbbbb3ab 1561 }
076bff8f
YS		 1562 if (i == 2)
1563 ea += (rank_density >> dbw_cap_adj);
dbbbb3ab
HW		 1564 break;
1565 default: /* No bank(chip-select) interleaving */
a4c66509
YS		 1566 sa = dimm_params[dimm_number].base_address;
1567 ea = sa + rank_density - 1;
1568 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1569 sa += (i % cs_per_dimm) * rank_density;
1570 ea += (i % cs_per_dimm) * rank_density;
1571 } else {
1572 sa = 0;
1573 ea = 0;
1574 }
dbbbb3ab
HW		 1575 break;
1576 }
58e5e9af 1577 }
58e5e9af
KG		 1578
1579 sa >>= 24;
1580 ea >>= 24;
1581
123922b1
YS		 1582 if (cs_en) {
1583 ddr->cs[i].bnds = (0
1584 | ((sa & 0xFFF) << 16)/* starting address MSB */
1585 | ((ea & 0xFFF) << 0) /* ending address MSB */
1586 );
1587 } else {
1588 debug("FSLDDR: setting bnds to 0 for inactive CS\n");
1589 ddr->cs[i].bnds = 0;
1590 }
58e5e9af 1591
1f293b41 1592 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
123922b1
YS		 1593 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1594 set_csn_config_2(i, ddr);
58e5e9af
KG		 1595 }
1596
fc0c2b6f
HW		 1597 /*
1598 * In the case we only need to compute the ddr sdram size, we only need
1599 * to set csn registers, so return from here.
1600 */
1601 if (size_only)
1602 return 0;
1603
7fd101c9
YS		 1604 set_ddr_eor(ddr, popts);
1605
c360ceac 1606#if !defined(CONFIG_FSL_DDR1)
123922b1 1607 set_timing_cfg_0(ddr, popts, dimm_params);
58e5e9af
KG		 1608#endif
1609
45064adc 1610 set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
c360ceac 1611 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
58e5e9af
KG		 1612 set_timing_cfg_2(ddr, popts, common_dimm,
1613 cas_latency, additive_latency);
1614
e1fd16b6 1615 set_ddr_cdr1(ddr, popts);
57495e4e 1616 set_ddr_cdr2(ddr, popts);
58e5e9af 1617 set_ddr_sdram_cfg(ddr, popts, common_dimm);
e1fd16b6
YS		 1618 ip_rev = fsl_ddr_get_version();
1619 if (ip_rev > 0x40400)
1620 unq_mrs_en = 1;
58e5e9af 1621
e1fd16b6 1622 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
58e5e9af 1623 set_ddr_sdram_mode(ddr, popts, common_dimm,
e1fd16b6
YS		 1624 cas_latency, additive_latency, unq_mrs_en);
1625 set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
58e5e9af
KG		 1626 set_ddr_sdram_interval(ddr, popts, common_dimm);
1627 set_ddr_data_init(ddr);
1628 set_ddr_sdram_clk_cntl(ddr, popts);
1629 set_ddr_init_addr(ddr);
1630 set_ddr_init_ext_addr(ddr);
ec145e87 1631 set_timing_cfg_4(ddr, popts);
e1fd16b6 1632 set_timing_cfg_5(ddr, cas_latency);
58e5e9af 1633
c360ceac 1634 set_ddr_zq_cntl(ddr, zq_en);
bdc9f7b5 1635 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
58e5e9af 1636
22cca7e1 1637 set_ddr_sr_cntr(ddr, sr_it);
58e5e9af 1638
e1fd16b6 1639 set_ddr_sdram_rcw(ddr, popts, common_dimm);
58e5e9af
KG		 1640
1641 return check_fsl_memctl_config_regs(ddr);
1642}
"Das U-Boot" Source Tree