]> git.ipfire.org Git - people/ms/u-boot.git/blame - arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c
CommitLineData
58e5e9af 1/*
fcea3068 2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
58e5e9af 3 *
ec145e87
DL		 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
58e5e9af
KG		 8 */
9
10/*
11 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12 * Based on code from spd_sdram.c
13 * Author: James Yang [at freescale.com]
14 */
15
16#include <common.h>
17#include <asm/fsl_ddr_sdram.h>
18
19#include "ddr.h"
20
d29d17d7
YS		 21#ifdef CONFIG_MPC83xx
22 #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
23#elif defined(CONFIG_MPC85xx)
e1fd16b6
YS		 24 #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
25#elif defined(CONFIG_MPC86xx)
26 #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
27#else
28 #error "Undefined _DDR_ADDR"
29#endif
30
31u32 fsl_ddr_get_version(void)
32{
33 ccsr_ddr_t *ddr;
34 u32 ver_major_minor_errata;
35
36 ddr = (void *)_DDR_ADDR;
37 ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
38 ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
39
40 return ver_major_minor_errata;
41}
42
43unsigned int picos_to_mclk(unsigned int picos);
44
58e5e9af
KG		 45/*
46 * Determine Rtt value.
47 *
48 * This should likely be either board or controller specific.
49 *
c360ceac 50 * Rtt(nominal) - DDR2:
58e5e9af
KG		 51 * 0 = Rtt disabled
52 * 1 = 75 ohm
53 * 2 = 150 ohm
54 * 3 = 50 ohm
c360ceac
DL		 55 * Rtt(nominal) - DDR3:
56 * 0 = Rtt disabled
57 * 1 = 60 ohm
58 * 2 = 120 ohm
59 * 3 = 40 ohm
60 * 4 = 20 ohm
61 * 5 = 30 ohm
58e5e9af
KG		 62 *
63 * FIXME: Apparently 8641 needs a value of 2
64 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
65 *
66 * FIXME: There was some effort down this line earlier:
67 *
68 * unsigned int i;
69 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
70 * if (popts->dimmslot[i].num_valid_cs
71 * && (popts->cs_local_opts[2*i].odt_rd_cfg
72 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
73 * rtt = 2;
74 * break;
75 * }
76 * }
77 */
78static inline int fsl_ddr_get_rtt(void)
79{
80 int rtt;
81
82#if defined(CONFIG_FSL_DDR1)
83 rtt = 0;
84#elif defined(CONFIG_FSL_DDR2)
85 rtt = 3;
86#else
c360ceac 87 rtt = 0;
58e5e9af
KG		 88#endif
89
90 return rtt;
91}
92
c360ceac
DL		 93/*
94 * compute the CAS write latency according to DDR3 spec
95 * CWL = 5 if tCK >= 2.5ns
96 * 6 if 2.5ns > tCK >= 1.875ns
97 * 7 if 1.875ns > tCK >= 1.5ns
98 * 8 if 1.5ns > tCK >= 1.25ns
2bba85f4
YS		 99 * 9 if 1.25ns > tCK >= 1.07ns
100 * 10 if 1.07ns > tCK >= 0.935ns
101 * 11 if 0.935ns > tCK >= 0.833ns
102 * 12 if 0.833ns > tCK >= 0.75ns
c360ceac
DL		 103 */
104static inline unsigned int compute_cas_write_latency(void)
105{
106 unsigned int cwl;
107 const unsigned int mclk_ps = get_memory_clk_period_ps();
108
109 if (mclk_ps >= 2500)
110 cwl = 5;
111 else if (mclk_ps >= 1875)
112 cwl = 6;
113 else if (mclk_ps >= 1500)
114 cwl = 7;
115 else if (mclk_ps >= 1250)
116 cwl = 8;
2bba85f4
YS		 117 else if (mclk_ps >= 1070)
118 cwl = 9;
119 else if (mclk_ps >= 935)
120 cwl = 10;
121 else if (mclk_ps >= 833)
122 cwl = 11;
123 else if (mclk_ps >= 750)
124 cwl = 12;
125 else {
126 cwl = 12;
127 printf("Warning: CWL is out of range\n");
128 }
c360ceac
DL		 129 return cwl;
130}
131
58e5e9af 132/* Chip Select Configuration (CSn_CONFIG) */
5800e7ab 133static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
58e5e9af
KG		 134 const memctl_options_t *popts,
135 const dimm_params_t *dimm_params)
136{
137 unsigned int cs_n_en = 0; /* Chip Select enable */
138 unsigned int intlv_en = 0; /* Memory controller interleave enable */
139 unsigned int intlv_ctl = 0; /* Interleaving control */
140 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
141 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
142 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
143 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
144 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
145 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
5800e7ab 146 int go_config = 0;
58e5e9af
KG		 147
148 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
5800e7ab
YS		 149 switch (i) {
150 case 0:
151 if (dimm_params[dimm_number].n_ranks > 0) {
152 go_config = 1;
58e5e9af 153 /* These fields only available in CS0_CONFIG */
a4c66509
YS		 154 if (!popts->memctl_interleaving)
155 break;
156 switch (popts->memctl_interleaving_mode) {
157 case FSL_DDR_CACHE_LINE_INTERLEAVING:
158 case FSL_DDR_PAGE_INTERLEAVING:
159 case FSL_DDR_BANK_INTERLEAVING:
160 case FSL_DDR_SUPERBANK_INTERLEAVING:
161 intlv_en = popts->memctl_interleaving;
162 intlv_ctl = popts->memctl_interleaving_mode;
163 break;
164 default:
165 break;
166 }
58e5e9af 167 }
5800e7ab
YS		 168 break;
169 case 1:
170 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
171 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
172 go_config = 1;
173 break;
174 case 2:
175 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
cae7c1b5 176 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
5800e7ab
YS		 177 go_config = 1;
178 break;
179 case 3:
180 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
181 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
182 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
183 go_config = 1;
184 break;
185 default:
186 break;
187 }
188 if (go_config) {
189 unsigned int n_banks_per_sdram_device;
190 cs_n_en = 1;
58e5e9af
KG		 191 ap_n_en = popts->cs_local_opts[i].auto_precharge;
192 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
193 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
194 n_banks_per_sdram_device
5800e7ab 195 = dimm_params[dimm_number].n_banks_per_sdram_device;
58e5e9af 196 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
5800e7ab
YS		 197 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
198 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
58e5e9af 199 }
58e5e9af
KG		 200 ddr->cs[i].config = (0
201 | ((cs_n_en & 0x1) << 31)
202 | ((intlv_en & 0x3) << 29)
dbbbb3ab 203 | ((intlv_ctl & 0xf) << 24)
58e5e9af
KG		 204 | ((ap_n_en & 0x1) << 23)
205
206 /* XXX: some implementation only have 1 bit starting at left */
207 | ((odt_rd_cfg & 0x7) << 20)
208
209 /* XXX: Some implementation only have 1 bit starting at left */
210 | ((odt_wr_cfg & 0x7) << 16)
211
212 | ((ba_bits_cs_n & 0x3) << 14)
213 | ((row_bits_cs_n & 0x7) << 8)
214 | ((col_bits_cs_n & 0x7) << 0)
215 );
1f293b41 216 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
58e5e9af
KG		 217}
218
219/* Chip Select Configuration 2 (CSn_CONFIG_2) */
220/* FIXME: 8572 */
221static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
222{
223 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
224
225 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
1f293b41 226 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
58e5e9af
KG		 227}
228
229/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
230
c360ceac 231#if !defined(CONFIG_FSL_DDR1)
58e5e9af
KG		 232/*
233 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
234 *
235 * Avoid writing for DDR I. The new PQ38 DDR controller
236 * dreams up non-zero default values to be backwards compatible.
237 */
e1fd16b6
YS		 238static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
239 const memctl_options_t *popts)
58e5e9af
KG		 240{
241 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
242 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
243 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
244 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
245 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
246
247 /* Active powerdown exit timing (tXARD and tXARDS). */
248 unsigned char act_pd_exit_mclk;
249 /* Precharge powerdown exit timing (tXP). */
250 unsigned char pre_pd_exit_mclk;
5fb8a8a7 251 /* ODT powerdown exit timing (tAXPD). */
58e5e9af
KG		 252 unsigned char taxpd_mclk;
253 /* Mode register set cycle time (tMRD). */
254 unsigned char tmrd_mclk;
255
e1fd16b6 256#ifdef CONFIG_FSL_DDR3
c360ceac
DL		 257 /*
258 * (tXARD and tXARDS). Empirical?
259 * The DDR3 spec has not tXARD,
260 * we use the tXP instead of it.
261 * tXP=max(3nCK, 7.5ns) for DDR3.
c360ceac 262 * spec has not the tAXPD, we use
5fb8a8a7 263 * tAXPD=1, need design to confirm.
c360ceac 264 */
0a71c92c 265 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
5df4b0ad 266 unsigned int data_rate = get_ddr_freq(0);
c360ceac 267 tmrd_mclk = 4;
99bac479
DL		 268 /* set the turnaround time */
269 trwt_mclk = 1;
856e4b0d
YS		 270 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
271 twrt_mclk = 1;
e1fd16b6
YS		 272
273 if (popts->dynamic_power == 0) { /* powerdown is not used */
274 act_pd_exit_mclk = 1;
275 pre_pd_exit_mclk = 1;
276 taxpd_mclk = 1;
277 } else {
278 /* act_pd_exit_mclk = tXARD, see above */
279 act_pd_exit_mclk = picos_to_mclk(tXP);
280 /* Mode register MR0[A12] is '1' - fast exit */
281 pre_pd_exit_mclk = act_pd_exit_mclk;
282 taxpd_mclk = 1;
283 }
c360ceac
DL		 284#else /* CONFIG_FSL_DDR2 */
285 /*
286 * (tXARD and tXARDS). Empirical?
287 * tXARD = 2 for DDR2
288 * tXP=2
289 * tAXPD=8
290 */
291 act_pd_exit_mclk = 2;
292 pre_pd_exit_mclk = 2;
293 taxpd_mclk = 8;
58e5e9af 294 tmrd_mclk = 2;
c360ceac 295#endif
58e5e9af 296
23f9670f
YS		 297 if (popts->trwt_override)
298 trwt_mclk = popts->trwt;
299
58e5e9af
KG		 300 ddr->timing_cfg_0 = (0
301 | ((trwt_mclk & 0x3) << 30) /* RWT */
302 | ((twrt_mclk & 0x3) << 28) /* WRT */
303 | ((trrt_mclk & 0x3) << 26) /* RRT */
304 | ((twwt_mclk & 0x3) << 24) /* WWT */
305 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
22ff3d01 306 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
58e5e9af
KG		 307 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
308 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
309 );
310 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
311}
312#endif /* defined(CONFIG_FSL_DDR2) */
313
314/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
315static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
c360ceac
DL		 316 const common_timing_params_t *common_dimm,
317 unsigned int cas_latency)
58e5e9af
KG		 318{
319 /* Extended Activate to precharge interval (tRAS) */
320 unsigned int ext_acttopre = 0;
321 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
322 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
323 unsigned int cntl_adj = 0; /* Control Adjust */
324
80ee3ce6
DL		 325 /* If the tRAS > 19 MCLK, we use the ext mode */
326 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
327 ext_acttopre = 1;
328
58e5e9af 329 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
c360ceac
DL		 330
331 /* If the CAS latency more than 8, use the ext mode */
332 if (cas_latency > 8)
333 ext_caslat = 1;
334
58e5e9af
KG		 335 ddr->timing_cfg_3 = (0
336 | ((ext_acttopre & 0x1) << 24)
80ee3ce6 337 | ((ext_refrec & 0xF) << 16)
58e5e9af
KG		 338 | ((ext_caslat & 0x1) << 12)
339 | ((cntl_adj & 0x7) << 0)
340 );
1f293b41 341 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
58e5e9af
KG		 342}
343
344/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
345static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
c360ceac 346 const memctl_options_t *popts,
58e5e9af
KG		 347 const common_timing_params_t *common_dimm,
348 unsigned int cas_latency)
349{
350 /* Precharge-to-activate interval (tRP) */
351 unsigned char pretoact_mclk;
352 /* Activate to precharge interval (tRAS) */
353 unsigned char acttopre_mclk;
354 /* Activate to read/write interval (tRCD) */
355 unsigned char acttorw_mclk;
356 /* CASLAT */
357 unsigned char caslat_ctrl;
358 /* Refresh recovery time (tRFC) ; trfc_low */
359 unsigned char refrec_ctrl;
360 /* Last data to precharge minimum interval (tWR) */
361 unsigned char wrrec_mclk;
362 /* Activate-to-activate interval (tRRD) */
363 unsigned char acttoact_mclk;
364 /* Last write data pair to read command issue interval (tWTR) */
365 unsigned char wrtord_mclk;
f5b6fb7c
YS		 366 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
367 static const u8 wrrec_table[] = {
368 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
58e5e9af
KG		 369
370 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
371 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
372 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
373
374 /*
375 * Translate CAS Latency to a DDR controller field value:
376 *
377 * CAS Lat DDR I DDR II Ctrl
378 * Clocks SPD Bit SPD Bit Value
379 * ------- ------- ------- -----
380 * 1.0 0 0001
381 * 1.5 1 0010
382 * 2.0 2 2 0011
383 * 2.5 3 0100
384 * 3.0 4 3 0101
385 * 3.5 5 0110
386 * 4.0 4 0111
387 * 4.5 1000
388 * 5.0 5 1001
389 */
390#if defined(CONFIG_FSL_DDR1)
391 caslat_ctrl = (cas_latency + 1) & 0x07;
392#elif defined(CONFIG_FSL_DDR2)
393 caslat_ctrl = 2 * cas_latency - 1;
394#else
c360ceac
DL		 395 /*
396 * if the CAS latency more than 8 cycle,
397 * we need set extend bit for it at
398 * TIMING_CFG_3[EXT_CASLAT]
399 */
400 if (cas_latency > 8)
401 cas_latency -= 8;
402 caslat_ctrl = 2 * cas_latency - 1;
58e5e9af
KG		 403#endif
404
405 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
406 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
f5b6fb7c
YS		 407
408 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
c360ceac
DL		 409 if (popts->OTF_burst_chop_en)
410 wrrec_mclk += 2;
411
58e5e9af 412 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
c360ceac
DL		 413 /*
414 * JEDEC has min requirement for tRRD
415 */
416#if defined(CONFIG_FSL_DDR3)
417 if (acttoact_mclk < 4)
418 acttoact_mclk = 4;
419#endif
58e5e9af 420 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
c360ceac
DL		 421 /*
422 * JEDEC has some min requirements for tWTR
423 */
424#if defined(CONFIG_FSL_DDR2)
425 if (wrtord_mclk < 2)
426 wrtord_mclk = 2;
427#elif defined(CONFIG_FSL_DDR3)
428 if (wrtord_mclk < 4)
429 wrtord_mclk = 4;
430#endif
431 if (popts->OTF_burst_chop_en)
432 wrtord_mclk += 2;
58e5e9af
KG		 433
434 ddr->timing_cfg_1 = (0
80ee3ce6 435 | ((pretoact_mclk & 0x0F) << 28)
58e5e9af 436 | ((acttopre_mclk & 0x0F) << 24)
80ee3ce6 437 | ((acttorw_mclk & 0xF) << 20)
58e5e9af
KG		 438 | ((caslat_ctrl & 0xF) << 16)
439 | ((refrec_ctrl & 0xF) << 12)
80ee3ce6 440 | ((wrrec_mclk & 0x0F) << 8)
58e5e9af
KG		 441 | ((acttoact_mclk & 0x07) << 4)
442 | ((wrtord_mclk & 0x07) << 0)
443 );
1f293b41 444 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
58e5e9af
KG		 445}
446
447/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
448static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
449 const memctl_options_t *popts,
450 const common_timing_params_t *common_dimm,
451 unsigned int cas_latency,
452 unsigned int additive_latency)
453{
454 /* Additive latency */
455 unsigned char add_lat_mclk;
456 /* CAS-to-preamble override */
457 unsigned short cpo;
458 /* Write latency */
459 unsigned char wr_lat;
460 /* Read to precharge (tRTP) */
461 unsigned char rd_to_pre;
462 /* Write command to write data strobe timing adjustment */
463 unsigned char wr_data_delay;
464 /* Minimum CKE pulse width (tCKE) */
465 unsigned char cke_pls;
466 /* Window for four activates (tFAW) */
467 unsigned short four_act;
468
469 /* FIXME add check that this must be less than acttorw_mclk */
470 add_lat_mclk = additive_latency;
471 cpo = popts->cpo_override;
472
473#if defined(CONFIG_FSL_DDR1)
474 /*
475 * This is a lie. It should really be 1, but if it is
476 * set to 1, bits overlap into the old controller's
477 * otherwise unused ACSM field. If we leave it 0, then
478 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
479 */
480 wr_lat = 0;
481#elif defined(CONFIG_FSL_DDR2)
6a819783 482 wr_lat = cas_latency - 1;
58e5e9af 483#else
c360ceac 484 wr_lat = compute_cas_write_latency();
58e5e9af
KG		 485#endif
486
487 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
c360ceac
DL		 488 /*
489 * JEDEC has some min requirements for tRTP
490 */
6a819783 491#if defined(CONFIG_FSL_DDR2)
c360ceac
DL		 492 if (rd_to_pre < 2)
493 rd_to_pre = 2;
494#elif defined(CONFIG_FSL_DDR3)
495 if (rd_to_pre < 4)
496 rd_to_pre = 4;
6a819783 497#endif
c360ceac
DL		 498 if (additive_latency)
499 rd_to_pre += additive_latency;
500 if (popts->OTF_burst_chop_en)
501 rd_to_pre += 2; /* according to UM */
502
58e5e9af
KG		 503 wr_data_delay = popts->write_data_delay;
504 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
505 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
506
507 ddr->timing_cfg_2 = (0
22ff3d01 508 | ((add_lat_mclk & 0xf) << 28)
58e5e9af 509 | ((cpo & 0x1f) << 23)
22ff3d01 510 | ((wr_lat & 0xf) << 19)
c360ceac
DL		 511 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
512 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
58e5e9af 513 | ((cke_pls & 0x7) << 6)
22ff3d01 514 | ((four_act & 0x3f) << 0)
58e5e9af 515 );
1f293b41 516 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
58e5e9af
KG		 517}
518
9490ff48
YS		 519/* DDR SDRAM Register Control Word */
520static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
e1fd16b6 521 const memctl_options_t *popts,
9490ff48
YS		 522 const common_timing_params_t *common_dimm)
523{
524 if (common_dimm->all_DIMMs_registered
525 && !common_dimm->all_DIMMs_unbuffered) {
e1fd16b6
YS		 526 if (popts->rcw_override) {
527 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
528 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
529 } else {
530 ddr->ddr_sdram_rcw_1 =
531 common_dimm->rcw[0] << 28 | \
532 common_dimm->rcw[1] << 24 | \
533 common_dimm->rcw[2] << 20 | \
534 common_dimm->rcw[3] << 16 | \
535 common_dimm->rcw[4] << 12 | \
536 common_dimm->rcw[5] << 8 | \
537 common_dimm->rcw[6] << 4 | \
538 common_dimm->rcw[7];
539 ddr->ddr_sdram_rcw_2 =
540 common_dimm->rcw[8] << 28 | \
541 common_dimm->rcw[9] << 24 | \
542 common_dimm->rcw[10] << 20 | \
543 common_dimm->rcw[11] << 16 | \
544 common_dimm->rcw[12] << 12 | \
545 common_dimm->rcw[13] << 8 | \
546 common_dimm->rcw[14] << 4 | \
547 common_dimm->rcw[15];
548 }
9490ff48
YS		 549 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
550 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
551 }
552}
553
58e5e9af
KG		 554/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
555static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
556 const memctl_options_t *popts,
557 const common_timing_params_t *common_dimm)
558{
559 unsigned int mem_en; /* DDR SDRAM interface logic enable */
560 unsigned int sren; /* Self refresh enable (during sleep) */
561 unsigned int ecc_en; /* ECC enable. */
562 unsigned int rd_en; /* Registered DIMM enable */
563 unsigned int sdram_type; /* Type of SDRAM */
564 unsigned int dyn_pwr; /* Dynamic power management mode */
565 unsigned int dbw; /* DRAM dta bus width */
22ff3d01 566 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
58e5e9af
KG		 567 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
568 unsigned int threeT_en; /* Enable 3T timing */
569 unsigned int twoT_en; /* Enable 2T timing */
570 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
571 unsigned int x32_en = 0; /* x32 enable */
572 unsigned int pchb8 = 0; /* precharge bit 8 enable */
573 unsigned int hse; /* Global half strength override */
574 unsigned int mem_halt = 0; /* memory controller halt */
575 unsigned int bi = 0; /* Bypass initialization */
576
577 mem_en = 1;
578 sren = popts->self_refresh_in_sleep;
579 if (common_dimm->all_DIMMs_ECC_capable) {
580 /* Allow setting of ECC only if all DIMMs are ECC. */
581 ecc_en = popts->ECC_mode;
582 } else {
583 ecc_en = 0;
584 }
585
e1fd16b6
YS		 586 if (common_dimm->all_DIMMs_registered
587 && !common_dimm->all_DIMMs_unbuffered) {
588 rd_en = 1;
589 twoT_en = 0;
590 } else {
591 rd_en = 0;
592 twoT_en = popts->twoT_en;
593 }
58e5e9af
KG		 594
595 sdram_type = CONFIG_FSL_SDRAM_TYPE;
596
597 dyn_pwr = popts->dynamic_power;
598 dbw = popts->data_bus_width;
c360ceac
DL		 599 /* 8-beat burst enable DDR-III case
600 * we must clear it when use the on-the-fly mode,
601 * must set it when use the 32-bits bus mode.
602 */
603 if (sdram_type == SDRAM_TYPE_DDR3) {
604 if (popts->burst_length == DDR_BL8)
605 eight_be = 1;
606 if (popts->burst_length == DDR_OTF)
607 eight_be = 0;
608 if (dbw == 0x1)
609 eight_be = 1;
610 }
611
58e5e9af 612 threeT_en = popts->threeT_en;
58e5e9af
KG		 613 ba_intlv_ctl = popts->ba_intlv_ctl;
614 hse = popts->half_strength_driver_enable;
615
616 ddr->ddr_sdram_cfg = (0
617 | ((mem_en & 0x1) << 31)
618 | ((sren & 0x1) << 30)
619 | ((ecc_en & 0x1) << 29)
620 | ((rd_en & 0x1) << 28)
621 | ((sdram_type & 0x7) << 24)
622 | ((dyn_pwr & 0x1) << 21)
623 | ((dbw & 0x3) << 19)
624 | ((eight_be & 0x1) << 18)
625 | ((ncap & 0x1) << 17)
626 | ((threeT_en & 0x1) << 16)
627 | ((twoT_en & 0x1) << 15)
628 | ((ba_intlv_ctl & 0x7F) << 8)
629 | ((x32_en & 0x1) << 5)
630 | ((pchb8 & 0x1) << 4)
631 | ((hse & 0x1) << 3)
632 | ((mem_halt & 0x1) << 1)
633 | ((bi & 0x1) << 0)
634 );
1f293b41 635 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
58e5e9af
KG		 636}
637
638/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
639static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
e1fd16b6
YS		 640 const memctl_options_t *popts,
641 const unsigned int unq_mrs_en)
58e5e9af
KG		 642{
643 unsigned int frc_sr = 0; /* Force self refresh */
644 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
645 unsigned int dll_rst_dis; /* DLL reset disable */
646 unsigned int dqs_cfg; /* DQS configuration */
cae7c1b5 647 unsigned int odt_cfg = 0; /* ODT configuration */
58e5e9af
KG		 648 unsigned int num_pr; /* Number of posted refreshes */
649 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
650 unsigned int ap_en; /* Address Parity Enable */
651 unsigned int d_init; /* DRAM data initialization */
652 unsigned int rcw_en = 0; /* Register Control Word Enable */
653 unsigned int md_en = 0; /* Mirrored DIMM Enable */
5800e7ab 654 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
cae7c1b5 655 int i;
58e5e9af
KG		 656
657 dll_rst_dis = 1; /* Make this configurable */
658 dqs_cfg = popts->DQS_config;
cae7c1b5
YS		 659 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
660 if (popts->cs_local_opts[i].odt_rd_cfg
661 || popts->cs_local_opts[i].odt_wr_cfg) {
662 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
663 break;
664 }
58e5e9af
KG		 665 }
666
667 num_pr = 1; /* Make this configurable */
668
669 /*
670 * 8572 manual says
671 * {TIMING_CFG_1[PRETOACT]
672 * + [DDR_SDRAM_CFG_2[NUM_PR]
673 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
674 * << DDR_SDRAM_INTERVAL[REFINT]
675 */
c360ceac
DL		 676#if defined(CONFIG_FSL_DDR3)
677 obc_cfg = popts->OTF_burst_chop_en;
678#else
679 obc_cfg = 0;
680#endif
58e5e9af 681
e1fd16b6
YS		 682 if (popts->registered_dimm_en) {
683 rcw_en = 1;
684 ap_en = popts->ap_en;
685 } else {
e1fd16b6
YS		 686 ap_en = 0;
687 }
58e5e9af
KG		 688
689#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
690 /* Use the DDR controller to auto initialize memory. */
e1fd16b6 691 d_init = popts->ECC_init_using_memctl;
58e5e9af
KG		 692 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
693 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
694#else
695 /* Memory will be initialized via DMA, or not at all. */
696 d_init = 0;
697#endif
698
c360ceac
DL		 699#if defined(CONFIG_FSL_DDR3)
700 md_en = popts->mirrored_dimm;
701#endif
5800e7ab 702 qd_en = popts->quad_rank_present ? 1 : 0;
58e5e9af
KG		 703 ddr->ddr_sdram_cfg_2 = (0
704 | ((frc_sr & 0x1) << 31)
705 | ((sr_ie & 0x1) << 30)
706 | ((dll_rst_dis & 0x1) << 29)
707 | ((dqs_cfg & 0x3) << 26)
708 | ((odt_cfg & 0x3) << 21)
709 | ((num_pr & 0xf) << 12)
5800e7ab 710 | (qd_en << 9)
e1fd16b6 711 | (unq_mrs_en << 8)
58e5e9af
KG		 712 | ((obc_cfg & 0x1) << 6)
713 | ((ap_en & 0x1) << 5)
714 | ((d_init & 0x1) << 4)
715 | ((rcw_en & 0x1) << 2)
716 | ((md_en & 0x1) << 0)
717 );
1f293b41 718 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
58e5e9af
KG		 719}
720
721/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1aa3d08a 722static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
e1fd16b6
YS		 723 const memctl_options_t *popts,
724 const unsigned int unq_mrs_en)
58e5e9af
KG		 725{
726 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
727 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
728
c360ceac 729#if defined(CONFIG_FSL_DDR3)
92966835 730 int i;
1aa3d08a 731 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
c360ceac
DL		 732 unsigned int srt = 0; /* self-refresh temerature, normal range */
733 unsigned int asr = 0; /* auto self-refresh disable */
734 unsigned int cwl = compute_cas_write_latency() - 5;
735 unsigned int pasr = 0; /* partial array self refresh disable */
736
1aa3d08a
DL		 737 if (popts->rtt_override)
738 rtt_wr = popts->rtt_wr_override_value;
e1fd16b6
YS		 739 else
740 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
c360ceac
DL		 741 esdmode2 = (0
742 | ((rtt_wr & 0x3) << 9)
743 | ((srt & 0x1) << 7)
744 | ((asr & 0x1) << 6)
745 | ((cwl & 0x7) << 3)
746 | ((pasr & 0x7) << 0));
747#endif
58e5e9af
KG		 748 ddr->ddr_sdram_mode_2 = (0
749 | ((esdmode2 & 0xFFFF) << 16)
750 | ((esdmode3 & 0xFFFF) << 0)
751 );
1f293b41 752 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
e1fd16b6
YS		 753
754#ifdef CONFIG_FSL_DDR3
755 if (unq_mrs_en) { /* unique mode registers are supported */
dea7f887 756 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
e1fd16b6
YS		 757 if (popts->rtt_override)
758 rtt_wr = popts->rtt_wr_override_value;
759 else
760 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
761
762 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
763 esdmode2 |= (rtt_wr & 0x3) << 9;
764 switch (i) {
765 case 1:
766 ddr->ddr_sdram_mode_4 = (0
767 | ((esdmode2 & 0xFFFF) << 16)
768 | ((esdmode3 & 0xFFFF) << 0)
769 );
770 break;
771 case 2:
772 ddr->ddr_sdram_mode_6 = (0
773 | ((esdmode2 & 0xFFFF) << 16)
774 | ((esdmode3 & 0xFFFF) << 0)
775 );
776 break;
777 case 3:
778 ddr->ddr_sdram_mode_8 = (0
779 | ((esdmode2 & 0xFFFF) << 16)
780 | ((esdmode3 & 0xFFFF) << 0)
781 );
782 break;
783 }
784 }
785 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
786 ddr->ddr_sdram_mode_4);
787 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
788 ddr->ddr_sdram_mode_6);
789 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
790 ddr->ddr_sdram_mode_8);
791 }
792#endif
58e5e9af
KG		 793}
794
795/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
796static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
797 const memctl_options_t *popts,
798 const common_timing_params_t *common_dimm)
799{
800 unsigned int refint; /* Refresh interval */
801 unsigned int bstopre; /* Precharge interval */
802
803 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
804
805 bstopre = popts->bstopre;
806
807 /* refint field used 0x3FFF in earlier controllers */
808 ddr->ddr_sdram_interval = (0
809 | ((refint & 0xFFFF) << 16)
810 | ((bstopre & 0x3FFF) << 0)
811 );
1f293b41 812 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
58e5e9af
KG		 813}
814
c360ceac
DL		 815#if defined(CONFIG_FSL_DDR3)
816/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
817static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
818 const memctl_options_t *popts,
819 const common_timing_params_t *common_dimm,
820 unsigned int cas_latency,
e1fd16b6
YS		 821 unsigned int additive_latency,
822 const unsigned int unq_mrs_en)
c360ceac
DL		 823{
824 unsigned short esdmode; /* Extended SDRAM mode */
825 unsigned short sdmode; /* SDRAM mode */
826
827 /* Mode Register - MR1 */
828 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
829 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
830 unsigned int rtt;
831 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
832 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
e1fd16b6 833 unsigned int dic = 0; /* Output driver impedance, 40ohm */
c360ceac
DL		 834 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
835 1=Disable (Test/Debug) */
836
837 /* Mode Register - MR0 */
838 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
fcea3068 839 unsigned int wr = 0; /* Write Recovery */
c360ceac
DL		 840 unsigned int dll_rst; /* DLL Reset */
841 unsigned int mode; /* Normal=0 or Test=1 */
842 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
843 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
844 unsigned int bt;
845 unsigned int bl; /* BL: Burst Length */
846
847 unsigned int wr_mclk;
f5b6fb7c
YS		 848 /*
849 * DDR_SDRAM_MODE doesn't support 9,11,13,15
850 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
851 * for this table
852 */
853 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
c360ceac
DL		 854
855 const unsigned int mclk_ps = get_memory_clk_period_ps();
e1fd16b6 856 int i;
c360ceac 857
c360ceac
DL		 858 if (popts->rtt_override)
859 rtt = popts->rtt_override_value;
e1fd16b6
YS		 860 else
861 rtt = popts->cs_local_opts[0].odt_rtt_norm;
c360ceac
DL		 862
863 if (additive_latency == (cas_latency - 1))
864 al = 1;
865 if (additive_latency == (cas_latency - 2))
866 al = 2;
867
e1fd16b6
YS		 868 if (popts->quad_rank_present)
869 dic = 1; /* output driver impedance 240/7 ohm */
870
c360ceac
DL		 871 /*
872 * The esdmode value will also be used for writing
873 * MR1 during write leveling for DDR3, although the
874 * bits specifically related to the write leveling
875 * scheme will be handled automatically by the DDR
876 * controller. so we set the wrlvl_en = 0 here.
877 */
878 esdmode = (0
879 | ((qoff & 0x1) << 12)
880 | ((tdqs_en & 0x1) << 11)
6d8565a1 881 | ((rtt & 0x4) << 7) /* rtt field is split */
c360ceac 882 | ((wrlvl_en & 0x1) << 7)
6d8565a1
KG		 883 | ((rtt & 0x2) << 5) /* rtt field is split */
884 | ((dic & 0x2) << 4) /* DIC field is split */
c360ceac 885 | ((al & 0x3) << 3)
6d8565a1 886 | ((rtt & 0x1) << 2) /* rtt field is split */
c360ceac
DL		 887 | ((dic & 0x1) << 1) /* DIC field is split */
888 | ((dll_en & 0x1) << 0)
889 );
890
891 /*
892 * DLL control for precharge PD
893 * 0=slow exit DLL off (tXPDLL)
894 * 1=fast exit DLL on (tXP)
895 */
896 dll_on = 1;
f5b6fb7c 897
c360ceac 898 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
fcea3068
YS		 899 if (wr_mclk <= 16) {
900 wr = wr_table[wr_mclk - 5];
901 } else {
902 printf("Error: unsupported write recovery for mode register "
903 "wr_mclk = %d\n", wr_mclk);
904 }
f5b6fb7c 905
c360ceac
DL		 906 dll_rst = 0; /* dll no reset */
907 mode = 0; /* normal mode */
908
909 /* look up table to get the cas latency bits */
fcea3068
YS		 910 if (cas_latency >= 5 && cas_latency <= 16) {
911 unsigned char cas_latency_table[] = {
c360ceac
DL		 912 0x2, /* 5 clocks */
913 0x4, /* 6 clocks */
914 0x6, /* 7 clocks */
915 0x8, /* 8 clocks */
916 0xa, /* 9 clocks */
917 0xc, /* 10 clocks */
fcea3068
YS		 918 0xe, /* 11 clocks */
919 0x1, /* 12 clocks */
920 0x3, /* 13 clocks */
921 0x5, /* 14 clocks */
922 0x7, /* 15 clocks */
923 0x9, /* 16 clocks */
c360ceac
DL		 924 };
925 caslat = cas_latency_table[cas_latency - 5];
fcea3068
YS		 926 } else {
927 printf("Error: unsupported cas latency for mode register\n");
c360ceac 928 }
fcea3068 929
c360ceac
DL		 930 bt = 0; /* Nibble sequential */
931
932 switch (popts->burst_length) {
933 case DDR_BL8:
934 bl = 0;
935 break;
936 case DDR_OTF:
937 bl = 1;
938 break;
939 case DDR_BC4:
940 bl = 2;
941 break;
942 default:
943 printf("Error: invalid burst length of %u specified. "
944 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
945 popts->burst_length);
946 bl = 1;
947 break;
948 }
949
950 sdmode = (0
951 | ((dll_on & 0x1) << 12)
952 | ((wr & 0x7) << 9)
953 | ((dll_rst & 0x1) << 8)
954 | ((mode & 0x1) << 7)
955 | (((caslat >> 1) & 0x7) << 4)
956 | ((bt & 0x1) << 3)
fcea3068 957 | ((caslat & 1) << 2)
c360ceac
DL		 958 | ((bl & 0x3) << 0)
959 );
960
961 ddr->ddr_sdram_mode = (0
962 | ((esdmode & 0xFFFF) << 16)
963 | ((sdmode & 0xFFFF) << 0)
964 );
965
966 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
e1fd16b6
YS		 967
968 if (unq_mrs_en) { /* unique mode registers are supported */
dea7f887 969 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
e1fd16b6
YS		 970 if (popts->rtt_override)
971 rtt = popts->rtt_override_value;
972 else
973 rtt = popts->cs_local_opts[i].odt_rtt_norm;
974
975 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
976 esdmode |= (0
977 | ((rtt & 0x4) << 7) /* rtt field is split */
978 | ((rtt & 0x2) << 5) /* rtt field is split */
979 | ((rtt & 0x1) << 2) /* rtt field is split */
980 );
981 switch (i) {
982 case 1:
983 ddr->ddr_sdram_mode_3 = (0
984 | ((esdmode & 0xFFFF) << 16)
985 | ((sdmode & 0xFFFF) << 0)
986 );
987 break;
988 case 2:
989 ddr->ddr_sdram_mode_5 = (0
990 | ((esdmode & 0xFFFF) << 16)
991 | ((sdmode & 0xFFFF) << 0)
992 );
993 break;
994 case 3:
995 ddr->ddr_sdram_mode_7 = (0
996 | ((esdmode & 0xFFFF) << 16)
997 | ((sdmode & 0xFFFF) << 0)
998 );
999 break;
1000 }
1001 }
1002 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1003 ddr->ddr_sdram_mode_3);
1004 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1005 ddr->ddr_sdram_mode_5);
1006 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1007 ddr->ddr_sdram_mode_5);
1008 }
c360ceac
DL		 1009}
1010
1011#else /* !CONFIG_FSL_DDR3 */
1012
58e5e9af
KG		 1013/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1014static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1015 const memctl_options_t *popts,
1016 const common_timing_params_t *common_dimm,
1017 unsigned int cas_latency,
e1fd16b6
YS		 1018 unsigned int additive_latency,
1019 const unsigned int unq_mrs_en)
58e5e9af
KG		 1020{
1021 unsigned short esdmode; /* Extended SDRAM mode */
1022 unsigned short sdmode; /* SDRAM mode */
1023
1024 /*
1025 * FIXME: This ought to be pre-calculated in a
1026 * technology-specific routine,
1027 * e.g. compute_DDR2_mode_register(), and then the
1028 * sdmode and esdmode passed in as part of common_dimm.
1029 */
1030
1031 /* Extended Mode Register */
1032 unsigned int mrs = 0; /* Mode Register Set */
1033 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1034 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1035 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1036 unsigned int ocd = 0; /* 0x0=OCD not supported,
1037 0x7=OCD default state */
1038 unsigned int rtt;
1039 unsigned int al; /* Posted CAS# additive latency (AL) */
1040 unsigned int ods = 0; /* Output Drive Strength:
1041 0 = Full strength (18ohm)
1042 1 = Reduced strength (4ohm) */
1043 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1044 1=Disable (Test/Debug) */
1045
1046 /* Mode Register (MR) */
1047 unsigned int mr; /* Mode Register Definition */
1048 unsigned int pd; /* Power-Down Mode */
1049 unsigned int wr; /* Write Recovery */
1050 unsigned int dll_res; /* DLL Reset */
1051 unsigned int mode; /* Normal=0 or Test=1 */
302e52e0 1052 unsigned int caslat = 0;/* CAS# latency */
58e5e9af
KG		 1053 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1054 unsigned int bt;
1055 unsigned int bl; /* BL: Burst Length */
1056
1057#if defined(CONFIG_FSL_DDR2)
1058 const unsigned int mclk_ps = get_memory_clk_period_ps();
1059#endif
cae7c1b5 1060 dqs_en = !popts->DQS_config;
58e5e9af
KG		 1061 rtt = fsl_ddr_get_rtt();
1062
1063 al = additive_latency;
1064
1065 esdmode = (0
1066 | ((mrs & 0x3) << 14)
1067 | ((outputs & 0x1) << 12)
1068 | ((rdqs_en & 0x1) << 11)
1069 | ((dqs_en & 0x1) << 10)
1070 | ((ocd & 0x7) << 7)
1071 | ((rtt & 0x2) << 5) /* rtt field is split */
1072 | ((al & 0x7) << 3)
1073 | ((rtt & 0x1) << 2) /* rtt field is split */
1074 | ((ods & 0x1) << 1)
1075 | ((dll_en & 0x1) << 0)
1076 );
1077
1078 mr = 0; /* FIXME: CHECKME */
1079
1080 /*
1081 * 0 = Fast Exit (Normal)
1082 * 1 = Slow Exit (Low Power)
1083 */
1084 pd = 0;
1085
1086#if defined(CONFIG_FSL_DDR1)
1087 wr = 0; /* Historical */
1088#elif defined(CONFIG_FSL_DDR2)
1089 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
58e5e9af
KG		 1090#endif
1091 dll_res = 0;
1092 mode = 0;
1093
1094#if defined(CONFIG_FSL_DDR1)
1095 if (1 <= cas_latency && cas_latency <= 4) {
1096 unsigned char mode_caslat_table[4] = {
1097 0x5, /* 1.5 clocks */
1098 0x2, /* 2.0 clocks */
1099 0x6, /* 2.5 clocks */
1100 0x3 /* 3.0 clocks */
1101 };
302e52e0
KG		 1102 caslat = mode_caslat_table[cas_latency - 1];
1103 } else {
1104 printf("Warning: unknown cas_latency %d\n", cas_latency);
58e5e9af
KG		 1105 }
1106#elif defined(CONFIG_FSL_DDR2)
1107 caslat = cas_latency;
58e5e9af
KG		 1108#endif
1109 bt = 0;
1110
1111 switch (popts->burst_length) {
c360ceac 1112 case DDR_BL4:
58e5e9af
KG		 1113 bl = 2;
1114 break;
c360ceac 1115 case DDR_BL8:
58e5e9af
KG		 1116 bl = 3;
1117 break;
1118 default:
1119 printf("Error: invalid burst length of %u specified. "
1120 " Defaulting to 4 beats.\n",
1121 popts->burst_length);
1122 bl = 2;
1123 break;
1124 }
1125
1126 sdmode = (0
1127 | ((mr & 0x3) << 14)
1128 | ((pd & 0x1) << 12)
1129 | ((wr & 0x7) << 9)
1130 | ((dll_res & 0x1) << 8)
1131 | ((mode & 0x1) << 7)
1132 | ((caslat & 0x7) << 4)
1133 | ((bt & 0x1) << 3)
1134 | ((bl & 0x7) << 0)
1135 );
1136
1137 ddr->ddr_sdram_mode = (0
1138 | ((esdmode & 0xFFFF) << 16)
1139 | ((sdmode & 0xFFFF) << 0)
1140 );
1f293b41 1141 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
58e5e9af 1142}
c360ceac 1143#endif
58e5e9af
KG		 1144
1145/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1146static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1147{
1148 unsigned int init_value; /* Initialization value */
1149
1150 init_value = 0xDEADBEEF;
1151 ddr->ddr_data_init = init_value;
1152}
1153
1154/*
1155 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1156 * The old controller on the 8540/60 doesn't have this register.
1157 * Hope it's OK to set it (to 0) anyway.
1158 */
1159static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1160 const memctl_options_t *popts)
1161{
1162 unsigned int clk_adjust; /* Clock adjust */
1163
1164 clk_adjust = popts->clk_adjust;
1165 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
9490ff48 1166 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
58e5e9af
KG		 1167}
1168
1169/* DDR Initialization Address (DDR_INIT_ADDR) */
1170static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1171{
1172 unsigned int init_addr = 0; /* Initialization address */
1173
1174 ddr->ddr_init_addr = init_addr;
1175}
1176
1177/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1178static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1179{
1180 unsigned int uia = 0; /* Use initialization address */
1181 unsigned int init_ext_addr = 0; /* Initialization address */
1182
1183 ddr->ddr_init_ext_addr = (0
1184 | ((uia & 0x1) << 31)
1185 | (init_ext_addr & 0xF)
1186 );
1187}
1188
1189/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
ec145e87
DL		 1190static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1191 const memctl_options_t *popts)
58e5e9af
KG		 1192{
1193 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1194 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1195 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1196 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1197 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1198
c360ceac 1199#if defined(CONFIG_FSL_DDR3)
ec145e87
DL		 1200 if (popts->burst_length == DDR_BL8) {
1201 /* We set BL/2 for fixed BL8 */
1202 rrt = 0; /* BL/2 clocks */
1203 wwt = 0; /* BL/2 clocks */
1204 } else {
1205 /* We need to set BL/2 + 2 to BC4 and OTF */
1206 rrt = 2; /* BL/2 + 2 clocks */
1207 wwt = 2; /* BL/2 + 2 clocks */
1208 }
c360ceac
DL		 1209 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1210#endif
58e5e9af
KG		 1211 ddr->timing_cfg_4 = (0
1212 | ((rwt & 0xf) << 28)
1213 | ((wrt & 0xf) << 24)
1214 | ((rrt & 0xf) << 20)
1215 | ((wwt & 0xf) << 16)
1216 | (dll_lock & 0x3)
1217 );
1f293b41 1218 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
58e5e9af
KG		 1219}
1220
1221/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
e1fd16b6 1222static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
58e5e9af
KG		 1223{
1224 unsigned int rodt_on = 0; /* Read to ODT on */
1225 unsigned int rodt_off = 0; /* Read to ODT off */
1226 unsigned int wodt_on = 0; /* Write to ODT on */
1227 unsigned int wodt_off = 0; /* Write to ODT off */
1228
c360ceac 1229#if defined(CONFIG_FSL_DDR3)
e1fd16b6
YS		 1230 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1231 rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
c360ceac 1232 rodt_off = 4; /* 4 clocks */
5fb8a8a7 1233 wodt_on = 1; /* 1 clocks */
c360ceac
DL		 1234 wodt_off = 4; /* 4 clocks */
1235#endif
1236
58e5e9af 1237 ddr->timing_cfg_5 = (0
22ff3d01
DL		 1238 | ((rodt_on & 0x1f) << 24)
1239 | ((rodt_off & 0x7) << 20)
1240 | ((wodt_on & 0x1f) << 12)
1241 | ((wodt_off & 0x7) << 8)
58e5e9af 1242 );
1f293b41 1243 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
58e5e9af
KG		 1244}
1245
1246/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
c360ceac 1247static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
58e5e9af 1248{
58e5e9af
KG		 1249 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1250 /* Normal Operation Full Calibration Time (tZQoper) */
1251 unsigned int zqoper = 0;
1252 /* Normal Operation Short Calibration Time (tZQCS) */
1253 unsigned int zqcs = 0;
1254
c360ceac
DL		 1255 if (zq_en) {
1256 zqinit = 9; /* 512 clocks */
1257 zqoper = 8; /* 256 clocks */
1258 zqcs = 6; /* 64 clocks */
1259 }
1260
58e5e9af
KG		 1261 ddr->ddr_zq_cntl = (0
1262 | ((zq_en & 0x1) << 31)
1263 | ((zqinit & 0xF) << 24)
1264 | ((zqoper & 0xF) << 16)
1265 | ((zqcs & 0xF) << 8)
1266 );
e1fd16b6 1267 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
58e5e9af
KG		 1268}
1269
1270/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
bdc9f7b5
DL		 1271static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1272 const memctl_options_t *popts)
58e5e9af 1273{
58e5e9af
KG		 1274 /*
1275 * First DQS pulse rising edge after margining mode
1276 * is programmed (tWL_MRD)
1277 */
1278 unsigned int wrlvl_mrd = 0;
1279 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1280 unsigned int wrlvl_odten = 0;
1281 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1282 unsigned int wrlvl_dqsen = 0;
1283 /* WRLVL_SMPL: Write leveling sample time */
1284 unsigned int wrlvl_smpl = 0;
1285 /* WRLVL_WLR: Write leveling repeition time */
1286 unsigned int wrlvl_wlr = 0;
1287 /* WRLVL_START: Write leveling start time */
1288 unsigned int wrlvl_start = 0;
1289
c360ceac
DL		 1290 /* suggest enable write leveling for DDR3 due to fly-by topology */
1291 if (wrlvl_en) {
1292 /* tWL_MRD min = 40 nCK, we set it 64 */
1293 wrlvl_mrd = 0x6;
1294 /* tWL_ODTEN 128 */
1295 wrlvl_odten = 0x7;
1296 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1297 wrlvl_dqsen = 0x5;
1298 /*
bdc9f7b5
DL		 1299 * Write leveling sample time at least need 6 clocks
1300 * higher than tWLO to allow enough time for progagation
1301 * delay and sampling the prime data bits.
c360ceac
DL		 1302 */
1303 wrlvl_smpl = 0xf;
1304 /*
1305 * Write leveling repetition time
1306 * at least tWLO + 6 clocks clocks
5fb8a8a7 1307 * we set it 64
c360ceac 1308 */
5fb8a8a7 1309 wrlvl_wlr = 0x6;
c360ceac
DL		 1310 /*
1311 * Write leveling start time
1312 * The value use for the DQS_ADJUST for the first sample
e1fd16b6
YS		 1313 * when write leveling is enabled. It probably needs to be
1314 * overriden per platform.
c360ceac
DL		 1315 */
1316 wrlvl_start = 0x8;
bdc9f7b5
DL		 1317 /*
1318 * Override the write leveling sample and start time
1319 * according to specific board
1320 */
1321 if (popts->wrlvl_override) {
1322 wrlvl_smpl = popts->wrlvl_sample;
1323 wrlvl_start = popts->wrlvl_start;
1324 }
c360ceac
DL		 1325 }
1326
58e5e9af
KG		 1327 ddr->ddr_wrlvl_cntl = (0
1328 | ((wrlvl_en & 0x1) << 31)
1329 | ((wrlvl_mrd & 0x7) << 24)
1330 | ((wrlvl_odten & 0x7) << 20)
1331 | ((wrlvl_dqsen & 0x7) << 16)
1332 | ((wrlvl_smpl & 0xf) << 12)
1333 | ((wrlvl_wlr & 0x7) << 8)
22ff3d01 1334 | ((wrlvl_start & 0x1F) << 0)
58e5e9af 1335 );
e1fd16b6 1336 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
58e5e9af
KG		 1337}
1338
1339/* DDR Self Refresh Counter (DDR_SR_CNTR) */
22cca7e1 1340static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
58e5e9af 1341{
22cca7e1 1342 /* Self Refresh Idle Threshold */
58e5e9af
KG		 1343 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1344}
1345
7fd101c9
YS		 1346static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1347{
1348 if (popts->addr_hash) {
1349 ddr->ddr_eor = 0x40000000; /* address hash enable */
c2a63f48 1350 puts("Address hashing enabled.\n");
7fd101c9
YS		 1351 }
1352}
1353
e1fd16b6
YS		 1354static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1355{
1356 ddr->ddr_cdr1 = popts->ddr_cdr1;
1357 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1358}
1359
58e5e9af
KG		 1360unsigned int
1361check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1362{
1363 unsigned int res = 0;
1364
1365 /*
1366 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1367 * not set at the same time.
1368 */
1369 if (ddr->ddr_sdram_cfg & 0x10000000
1370 && ddr->ddr_sdram_cfg & 0x00008000) {
1371 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1372 " should not be set at the same time.\n");
1373 res++;
1374 }
1375
1376 return res;
1377}
1378
1379unsigned int
1380compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1381 fsl_ddr_cfg_regs_t *ddr,
1382 const common_timing_params_t *common_dimm,
1383 const dimm_params_t *dimm_params,
fc0c2b6f
HW		 1384 unsigned int dbw_cap_adj,
1385 unsigned int size_only)
58e5e9af
KG		 1386{
1387 unsigned int i;
1388 unsigned int cas_latency;
1389 unsigned int additive_latency;
22cca7e1 1390 unsigned int sr_it;
c360ceac
DL		 1391 unsigned int zq_en;
1392 unsigned int wrlvl_en;
e1fd16b6
YS		 1393 unsigned int ip_rev = 0;
1394 unsigned int unq_mrs_en = 0;
58edbc9c 1395 int cs_en = 1;
58e5e9af
KG		 1396
1397 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1398
1399 if (common_dimm == NULL) {
1400 printf("Error: subset DIMM params struct null pointer\n");
1401 return 1;
1402 }
1403
1404 /*
1405 * Process overrides first.
1406 *
1407 * FIXME: somehow add dereated caslat to this
1408 */
1409 cas_latency = (popts->cas_latency_override)
1410 ? popts->cas_latency_override_value
1411 : common_dimm->lowest_common_SPD_caslat;
1412
1413 additive_latency = (popts->additive_latency_override)
1414 ? popts->additive_latency_override_value
1415 : common_dimm->additive_latency;
1416
22cca7e1
DL		 1417 sr_it = (popts->auto_self_refresh_en)
1418 ? popts->sr_it
1419 : 0;
c360ceac
DL		 1420 /* ZQ calibration */
1421 zq_en = (popts->zq_en) ? 1 : 0;
1422 /* write leveling */
1423 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
22cca7e1 1424
58e5e9af
KG		 1425 /* Chip Select Memory Bounds (CSn_BNDS) */
1426 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
a4c66509 1427 unsigned long long ea, sa;
076bff8f
YS		 1428 unsigned int cs_per_dimm
1429 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1430 unsigned int dimm_number
1431 = i / cs_per_dimm;
1432 unsigned long long rank_density
a4c66509 1433 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
076bff8f 1434
076bff8f 1435 if (dimm_params[dimm_number].n_ranks == 0) {
58e5e9af 1436 debug("Skipping setup of CS%u "
5800e7ab 1437 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
58e5e9af
KG		 1438 continue;
1439 }
a4c66509 1440 if (popts->memctl_interleaving) {
076bff8f 1441 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
a4c66509
YS		 1442 case FSL_DDR_CS0_CS1_CS2_CS3:
1443 break;
076bff8f
YS		 1444 case FSL_DDR_CS0_CS1:
1445 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
58edbc9c
YS		 1446 if (i > 1)
1447 cs_en = 0;
076bff8f
YS		 1448 break;
1449 case FSL_DDR_CS2_CS3:
a4c66509 1450 default:
58edbc9c
YS		 1451 if (i > 0)
1452 cs_en = 0;
076bff8f 1453 break;
076bff8f 1454 }
a4c66509
YS		 1455 sa = common_dimm->base_address;
1456 ea = common_dimm->total_mem - 1;
1457 } else if (!popts->memctl_interleaving) {
58e5e9af
KG		 1458 /*
1459 * If memory interleaving between controllers is NOT
1460 * enabled, the starting address for each memory
1461 * controller is distinct. However, because rank
1462 * interleaving is enabled, the starting and ending
1463 * addresses of the total memory on that memory
1464 * controller needs to be programmed into its
1465 * respective CS0_BNDS.
1466 */
dbbbb3ab
HW		 1467 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1468 case FSL_DDR_CS0_CS1_CS2_CS3:
dbbbb3ab 1469 sa = common_dimm->base_address;
a4c66509 1470 ea = common_dimm->total_mem - 1;
dbbbb3ab
HW		 1471 break;
1472 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
a4c66509 1473 if ((i >= 2) && (dimm_number == 0)) {
076bff8f 1474 sa = dimm_params[dimm_number].base_address +
a4c66509
YS		 1475 2 * rank_density;
1476 ea = sa + 2 * rank_density - 1;
076bff8f
YS		 1477 } else {
1478 sa = dimm_params[dimm_number].base_address;
a4c66509 1479 ea = sa + 2 * rank_density - 1;
dbbbb3ab
HW		 1480 }
1481 break;
1482 case FSL_DDR_CS0_CS1:
076bff8f
YS		 1483 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1484 sa = dimm_params[dimm_number].base_address;
a4c66509
YS		 1485 ea = sa + rank_density - 1;
1486 if (i != 1)
1487 sa += (i % cs_per_dimm) * rank_density;
1488 ea += (i % cs_per_dimm) * rank_density;
076bff8f
YS		 1489 } else {
1490 sa = 0;
1491 ea = 0;
1492 }
1493 if (i == 0)
a4c66509 1494 ea += rank_density;
dbbbb3ab
HW		 1495 break;
1496 case FSL_DDR_CS2_CS3:
076bff8f
YS		 1497 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1498 sa = dimm_params[dimm_number].base_address;
a4c66509
YS		 1499 ea = sa + rank_density - 1;
1500 if (i != 3)
1501 sa += (i % cs_per_dimm) * rank_density;
1502 ea += (i % cs_per_dimm) * rank_density;
076bff8f
YS		 1503 } else {
1504 sa = 0;
1505 ea = 0;
dbbbb3ab 1506 }
076bff8f
YS		 1507 if (i == 2)
1508 ea += (rank_density >> dbw_cap_adj);
dbbbb3ab
HW		 1509 break;
1510 default: /* No bank(chip-select) interleaving */
a4c66509
YS		 1511 sa = dimm_params[dimm_number].base_address;
1512 ea = sa + rank_density - 1;
1513 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1514 sa += (i % cs_per_dimm) * rank_density;
1515 ea += (i % cs_per_dimm) * rank_density;
1516 } else {
1517 sa = 0;
1518 ea = 0;
1519 }
dbbbb3ab
HW		 1520 break;
1521 }
58e5e9af 1522 }
58e5e9af
KG		 1523
1524 sa >>= 24;
1525 ea >>= 24;
1526
1527 ddr->cs[i].bnds = (0
1528 | ((sa & 0xFFF) << 16) /* starting address MSB */
1529 | ((ea & 0xFFF) << 0) /* ending address MSB */
1530 );
1531
1f293b41 1532 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
58edbc9c
YS		 1533 if (cs_en) {
1534 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1535 set_csn_config_2(i, ddr);
1536 } else
fcea3068 1537 debug("CS%d is disabled.\n", i);
58e5e9af
KG		 1538 }
1539
fc0c2b6f
HW		 1540 /*
1541 * In the case we only need to compute the ddr sdram size, we only need
1542 * to set csn registers, so return from here.
1543 */
1544 if (size_only)
1545 return 0;
1546
7fd101c9
YS		 1547 set_ddr_eor(ddr, popts);
1548
c360ceac 1549#if !defined(CONFIG_FSL_DDR1)
e1fd16b6 1550 set_timing_cfg_0(ddr, popts);
58e5e9af
KG		 1551#endif
1552
c360ceac
DL		 1553 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1554 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
58e5e9af
KG		 1555 set_timing_cfg_2(ddr, popts, common_dimm,
1556 cas_latency, additive_latency);
1557
e1fd16b6 1558 set_ddr_cdr1(ddr, popts);
58e5e9af 1559 set_ddr_sdram_cfg(ddr, popts, common_dimm);
e1fd16b6
YS		 1560 ip_rev = fsl_ddr_get_version();
1561 if (ip_rev > 0x40400)
1562 unq_mrs_en = 1;
58e5e9af 1563
e1fd16b6 1564 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
58e5e9af 1565 set_ddr_sdram_mode(ddr, popts, common_dimm,
e1fd16b6
YS		 1566 cas_latency, additive_latency, unq_mrs_en);
1567 set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en);
58e5e9af
KG		 1568 set_ddr_sdram_interval(ddr, popts, common_dimm);
1569 set_ddr_data_init(ddr);
1570 set_ddr_sdram_clk_cntl(ddr, popts);
1571 set_ddr_init_addr(ddr);
1572 set_ddr_init_ext_addr(ddr);
ec145e87 1573 set_timing_cfg_4(ddr, popts);
e1fd16b6 1574 set_timing_cfg_5(ddr, cas_latency);
58e5e9af 1575
c360ceac 1576 set_ddr_zq_cntl(ddr, zq_en);
bdc9f7b5 1577 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
58e5e9af 1578
22cca7e1 1579 set_ddr_sr_cntr(ddr, sr_it);
58e5e9af 1580
e1fd16b6 1581 set_ddr_sdram_rcw(ddr, popts, common_dimm);
58e5e9af
KG		 1582
1583 return check_fsl_memctl_config_regs(ddr);
1584}
"Das U-Boot" Source Tree