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a09b9b68 KG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
a09b9b68 KG |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <config.h> | |
9 | #include <asm/fsl_law.h> | |
10 | #include <asm/fsl_serdes.h> | |
5ffa88ec | 11 | #include <asm/fsl_srio.h> |
1221ce45 | 12 | #include <linux/errno.h> |
5ffa88ec | 13 | |
c8b28152 | 14 | #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER |
5ffa88ec LG |
15 | #define SRIO_PORT_ACCEPT_ALL 0x10000001 |
16 | #define SRIO_IB_ATMU_AR 0x80f55000 | |
5056c8e0 LG |
17 | #define SRIO_OB_ATMU_AR_MAINT 0x80077000 |
18 | #define SRIO_OB_ATMU_AR_RW 0x80045000 | |
19 | #define SRIO_LCSBA1CSR_OFFSET 0x5c | |
20 | #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ | |
21 | #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ | |
22 | #define SRIO_LCSBA1CSR 0x60000000 | |
19e4a009 | 23 | #endif |
a09b9b68 KG |
24 | |
25 | #if defined(CONFIG_FSL_CORENET) | |
9e758758 YS |
26 | #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 |
27 | #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1 | |
28 | #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2 | |
29 | #else | |
a09b9b68 KG |
30 | #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 |
31 | #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 | |
9e758758 | 32 | #endif |
a09b9b68 KG |
33 | #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU |
34 | #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR | |
35 | #elif defined(CONFIG_MPC85xx) | |
36 | #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO | |
37 | #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO | |
38 | #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG | |
39 | #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR | |
40 | #elif defined(CONFIG_MPC86xx) | |
41 | #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO | |
42 | #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO | |
43 | #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG | |
44 | #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ | |
45 | (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) | |
46 | #else | |
47 | #error "No defines for DEVDISR_SRIO" | |
48 | #endif | |
49 | ||
d59c5570 LG |
50 | #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
51 | /* | |
52 | * Erratum A-004034 | |
53 | * Affects: SRIO | |
54 | * Description: During port initialization, the SRIO port performs | |
55 | * lane synchronization (detecting valid symbols on a lane) and | |
56 | * lane alignment (coordinating multiple lanes to receive valid data | |
57 | * across lanes). Internal errors in lane synchronization and lane | |
58 | * alignment may cause failure to achieve link initialization at | |
59 | * the configured port width. | |
60 | * An SRIO port configured as a 4x port may see one of these scenarios: | |
61 | * 1. One or more lanes fails to achieve lane synchronization. Depending | |
62 | * on which lanes fail, this may result in downtraining from 4x to 1x | |
63 | * on lane 0, 4x to 1x on lane R (redundant lane). | |
64 | * 2. The link may fail to achieve lane alignment as a 4x, even though | |
65 | * all 4 lanes achieve lane synchronization, and downtrain to a 1x. | |
66 | * An SRIO port configured as a 1x port may fail to complete port | |
67 | * initialization (PnESCSR[PU] never deasserts) because of scenario 1. | |
68 | * Impact: SRIO port may downtrain to 1x, or may fail to complete | |
69 | * link initialization. Once a port completes link initialization | |
70 | * successfully, it will operate normally. | |
71 | */ | |
72 | static int srio_erratum_a004034(u8 port) | |
73 | { | |
74 | serdes_corenet_t *srds_regs; | |
75 | u32 conf_lane; | |
76 | u32 init_lane; | |
77 | int idx, first, last; | |
78 | u32 i; | |
79 | unsigned long long end_tick; | |
80 | struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR; | |
81 | ||
82 | srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); | |
83 | conf_lane = (in_be32((void *)&srds_regs->srdspccr0) | |
84 | >> (12 - port * 4)) & 0x3; | |
85 | init_lane = (in_be32((void *)&srio_regs->lp_serial | |
86 | .port[port].pccsr) >> 27) & 0x7; | |
87 | ||
88 | /* | |
89 | * Start a counter set to ~2 ms after the SERDES reset is | |
90 | * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n | |
91 | * corresponding to the SERDES bank/PLL for the SRIO port). | |
92 | */ | |
93 | if (in_be32((void *)&srds_regs->bank[0].rstctl) | |
94 | & SRDS_RSTCTL_RSTDONE) { | |
95 | /* | |
96 | * Poll the port uninitialized status (SRIO PnESCSR[PO]) until | |
97 | * PO=1 or the counter expires. If the counter expires, the | |
98 | * port has failed initialization: go to recover steps. If PO=1 | |
99 | * and the desired port width is 1x, go to normal steps. If | |
100 | * PO = 1 and the desired port width is 4x, go to recover steps. | |
101 | */ | |
102 | end_tick = usec2ticks(2000) + get_ticks(); | |
103 | do { | |
104 | if (in_be32((void *)&srio_regs->lp_serial | |
105 | .port[port].pescsr) & 0x2) { | |
106 | if (conf_lane == 0x1) | |
107 | goto host_ok; | |
108 | else { | |
109 | if (init_lane == 0x2) | |
110 | goto host_ok; | |
111 | else | |
112 | break; | |
113 | } | |
114 | } | |
115 | } while (end_tick > get_ticks()); | |
116 | ||
117 | /* recover at most 3 times */ | |
118 | for (i = 0; i < 3; i++) { | |
119 | /* Set SRIO PnCCSR[PD]=1 */ | |
120 | setbits_be32((void *)&srio_regs->lp_serial | |
121 | .port[port].pccsr, | |
122 | 0x800000); | |
123 | /* | |
124 | * Set SRIO PnPCR[OBDEN] on the host to | |
125 | * enable the discarding of any pending packets. | |
126 | */ | |
127 | setbits_be32((void *)&srio_regs->impl.port[port].pcr, | |
128 | 0x04); | |
129 | /* Wait 50 us */ | |
130 | udelay(50); | |
131 | /* Run sync command */ | |
132 | isync(); | |
133 | ||
134 | if (port) | |
135 | first = serdes_get_first_lane(SRIO2); | |
136 | else | |
137 | first = serdes_get_first_lane(SRIO1); | |
138 | if (unlikely(first < 0)) | |
139 | return -ENODEV; | |
140 | if (conf_lane == 0x1) | |
141 | last = first; | |
142 | else | |
143 | last = first + 3; | |
144 | /* | |
145 | * Set SERDES BnGCRm0[RRST]=0 for each SRIO | |
146 | * bank n and lane m. | |
147 | */ | |
148 | for (idx = first; idx <= last; idx++) | |
149 | clrbits_be32(&srds_regs->lane[idx].gcr0, | |
150 | SRDS_GCR0_RRST); | |
151 | /* | |
152 | * Read SERDES BnGCRm0 for each SRIO | |
153 | * bank n and lane m | |
154 | */ | |
155 | for (idx = first; idx <= last; idx++) | |
156 | in_be32(&srds_regs->lane[idx].gcr0); | |
157 | /* Run sync command */ | |
158 | isync(); | |
159 | /* Wait >= 100 ns */ | |
160 | udelay(1); | |
161 | /* | |
162 | * Set SERDES BnGCRm0[RRST]=1 for each SRIO | |
163 | * bank n and lane m. | |
164 | */ | |
165 | for (idx = first; idx <= last; idx++) | |
166 | setbits_be32(&srds_regs->lane[idx].gcr0, | |
167 | SRDS_GCR0_RRST); | |
168 | /* | |
169 | * Read SERDES BnGCRm0 for each SRIO | |
170 | * bank n and lane m | |
171 | */ | |
172 | for (idx = first; idx <= last; idx++) | |
173 | in_be32(&srds_regs->lane[idx].gcr0); | |
174 | /* Run sync command */ | |
175 | isync(); | |
176 | /* Wait >= 300 ns */ | |
177 | udelay(1); | |
178 | ||
179 | /* Write 1 to clear all bits in SRIO PnSLCSR */ | |
180 | out_be32((void *)&srio_regs->impl.port[port].slcsr, | |
181 | 0xffffffff); | |
182 | /* Clear SRIO PnPCR[OBDEN] on the host */ | |
183 | clrbits_be32((void *)&srio_regs->impl.port[port].pcr, | |
184 | 0x04); | |
185 | /* Set SRIO PnCCSR[PD]=0 */ | |
186 | clrbits_be32((void *)&srio_regs->lp_serial | |
187 | .port[port].pccsr, | |
188 | 0x800000); | |
189 | /* Wait >= 24 ms */ | |
190 | udelay(24000); | |
191 | /* Poll the state of the port again */ | |
192 | init_lane = | |
193 | (in_be32((void *)&srio_regs->lp_serial | |
194 | .port[port].pccsr) >> 27) & 0x7; | |
195 | if (in_be32((void *)&srio_regs->lp_serial | |
196 | .port[port].pescsr) & 0x2) { | |
197 | if (conf_lane == 0x1) | |
198 | goto host_ok; | |
199 | else { | |
200 | if (init_lane == 0x2) | |
201 | goto host_ok; | |
202 | } | |
203 | } | |
204 | if (i == 2) | |
205 | return -ENODEV; | |
206 | } | |
207 | } else | |
208 | return -ENODEV; | |
209 | ||
210 | host_ok: | |
211 | /* Poll PnESCSR[OES] on the host until it is clear */ | |
212 | end_tick = usec2ticks(1000000) + get_ticks(); | |
213 | do { | |
214 | if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr) | |
215 | & 0x10000)) { | |
216 | out_be32(((void *)&srio_regs->lp_serial | |
217 | .port[port].pescsr), 0xffffffff); | |
218 | out_be32(((void *)&srio_regs->phys_err | |
219 | .port[port].edcsr), 0); | |
220 | out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0); | |
221 | return 0; | |
222 | } | |
223 | } while (end_tick > get_ticks()); | |
224 | ||
225 | return -ENODEV; | |
226 | } | |
227 | #endif | |
228 | ||
a09b9b68 KG |
229 | void srio_init(void) |
230 | { | |
231 | ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; | |
232 | int srio1_used = 0, srio2_used = 0; | |
9e758758 | 233 | u32 *devdisr; |
a09b9b68 | 234 | |
9e758758 YS |
235 | #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 |
236 | devdisr = &gur->devdisr3; | |
237 | #else | |
238 | devdisr = &gur->devdisr; | |
239 | #endif | |
a09b9b68 KG |
240 | if (is_serdes_configured(SRIO1)) { |
241 | set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, | |
242 | law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), | |
243 | LAW_TRGT_IF_RIO_1); | |
244 | srio1_used = 1; | |
d59c5570 LG |
245 | #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
246 | if (srio_erratum_a004034(0) < 0) | |
247 | printf("SRIO1: enabled but port error\n"); | |
248 | else | |
249 | #endif | |
a09b9b68 KG |
250 | printf("SRIO1: enabled\n"); |
251 | } else { | |
252 | printf("SRIO1: disabled\n"); | |
253 | } | |
254 | ||
255 | #ifdef CONFIG_SRIO2 | |
256 | if (is_serdes_configured(SRIO2)) { | |
257 | set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, | |
258 | law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), | |
259 | LAW_TRGT_IF_RIO_2); | |
260 | srio2_used = 1; | |
d59c5570 LG |
261 | #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
262 | if (srio_erratum_a004034(1) < 0) | |
263 | printf("SRIO2: enabled but port error\n"); | |
264 | else | |
265 | #endif | |
a09b9b68 | 266 | printf("SRIO2: enabled\n"); |
d59c5570 | 267 | |
a09b9b68 KG |
268 | } else { |
269 | printf("SRIO2: disabled\n"); | |
270 | } | |
271 | #endif | |
272 | ||
273 | #ifdef CONFIG_FSL_CORENET | |
274 | /* On FSL_CORENET devices we can disable individual ports */ | |
275 | if (!srio1_used) | |
9e758758 | 276 | setbits_be32(devdisr, _DEVDISR_SRIO1); |
a09b9b68 | 277 | if (!srio2_used) |
9e758758 | 278 | setbits_be32(devdisr, _DEVDISR_SRIO2); |
a09b9b68 KG |
279 | #endif |
280 | ||
281 | /* neither port is used - disable everything */ | |
282 | if (!srio1_used && !srio2_used) { | |
9e758758 YS |
283 | setbits_be32(devdisr, _DEVDISR_SRIO1); |
284 | setbits_be32(devdisr, _DEVDISR_SRIO2); | |
285 | setbits_be32(devdisr, _DEVDISR_RMU); | |
a09b9b68 KG |
286 | } |
287 | } | |
5ffa88ec | 288 | |
c8b28152 | 289 | #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER |
ff65f126 | 290 | void srio_boot_master(int port) |
5ffa88ec LG |
291 | { |
292 | struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; | |
293 | ||
294 | /* set port accept-all */ | |
ff65f126 | 295 | out_be32((void *)&srio->impl.port[port - 1].ptaacr, |
5ffa88ec LG |
296 | SRIO_PORT_ACCEPT_ALL); |
297 | ||
ff65f126 | 298 | debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port); |
3f1af81b LG |
299 | /* configure inbound window for slave's u-boot image */ |
300 | debug("SRIOBOOT - MASTER: Inbound window for slave's image; " | |
5ffa88ec | 301 | "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", |
b5f7c873 LG |
302 | (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, |
303 | (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, | |
304 | CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); | |
ff65f126 | 305 | out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, |
b5f7c873 | 306 | CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); |
ff65f126 | 307 | out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, |
b5f7c873 | 308 | CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); |
ff65f126 | 309 | out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, |
5ffa88ec | 310 | SRIO_IB_ATMU_AR |
b5f7c873 | 311 | | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); |
5ffa88ec | 312 | |
3f1af81b LG |
313 | /* configure inbound window for slave's u-boot image */ |
314 | debug("SRIOBOOT - MASTER: Inbound window for slave's image; " | |
5ffa88ec | 315 | "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", |
b5f7c873 LG |
316 | (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, |
317 | (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, | |
318 | CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); | |
ff65f126 | 319 | out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, |
b5f7c873 | 320 | CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); |
ff65f126 | 321 | out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, |
b5f7c873 | 322 | CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); |
ff65f126 | 323 | out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar, |
5ffa88ec | 324 | SRIO_IB_ATMU_AR |
b5f7c873 | 325 | | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); |
3f1af81b | 326 | |
ff65f126 LG |
327 | /* configure inbound window for slave's ucode and ENV */ |
328 | debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; " | |
3f1af81b | 329 | "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", |
b5f7c873 LG |
330 | (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, |
331 | (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, | |
332 | CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); | |
ff65f126 | 333 | out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar, |
b5f7c873 | 334 | CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); |
ff65f126 | 335 | out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar, |
b5f7c873 | 336 | CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); |
ff65f126 | 337 | out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar, |
0a85a9e7 | 338 | SRIO_IB_ATMU_AR |
b5f7c873 | 339 | | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); |
5ffa88ec | 340 | } |
5056c8e0 | 341 | |
ff65f126 | 342 | void srio_boot_master_release_slave(int port) |
5056c8e0 LG |
343 | { |
344 | struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; | |
345 | u32 escsr; | |
346 | debug("SRIOBOOT - MASTER: " | |
347 | "Check the port status and release slave core ...\n"); | |
348 | ||
ff65f126 | 349 | escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr); |
5056c8e0 LG |
350 | if (escsr & 0x2) { |
351 | if (escsr & 0x10100) { | |
352 | debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n", | |
ff65f126 | 353 | port); |
5056c8e0 LG |
354 | } else { |
355 | debug("SRIOBOOT - MASTER: " | |
ff65f126 LG |
356 | "Port [ %d ] is ready, now release slave's core ...\n", |
357 | port); | |
5056c8e0 LG |
358 | /* |
359 | * configure outbound window | |
360 | * with maintenance attribute to set slave's LCSBA1CSR | |
361 | */ | |
ff65f126 | 362 | out_be32((void *)&srio->atmu.port[port - 1] |
5056c8e0 | 363 | .outbw[1].rowtar, 0); |
ff65f126 | 364 | out_be32((void *)&srio->atmu.port[port - 1] |
5056c8e0 | 365 | .outbw[1].rowtear, 0); |
ff65f126 LG |
366 | if (port - 1) |
367 | out_be32((void *)&srio->atmu.port[port - 1] | |
5056c8e0 LG |
368 | .outbw[1].rowbar, |
369 | CONFIG_SYS_SRIO2_MEM_PHYS >> 12); | |
370 | else | |
ff65f126 | 371 | out_be32((void *)&srio->atmu.port[port - 1] |
5056c8e0 LG |
372 | .outbw[1].rowbar, |
373 | CONFIG_SYS_SRIO1_MEM_PHYS >> 12); | |
ff65f126 | 374 | out_be32((void *)&srio->atmu.port[port - 1] |
5056c8e0 LG |
375 | .outbw[1].rowar, |
376 | SRIO_OB_ATMU_AR_MAINT | |
377 | | atmu_size_mask(SRIO_MAINT_WIN_SIZE)); | |
378 | ||
379 | /* | |
380 | * configure outbound window | |
381 | * with R/W attribute to set slave's BRR | |
382 | */ | |
ff65f126 | 383 | out_be32((void *)&srio->atmu.port[port - 1] |
5056c8e0 LG |
384 | .outbw[2].rowtar, |
385 | SRIO_LCSBA1CSR >> 9); | |
ff65f126 | 386 | out_be32((void *)&srio->atmu.port[port - 1] |
5056c8e0 | 387 | .outbw[2].rowtear, 0); |
ff65f126 LG |
388 | if (port - 1) |
389 | out_be32((void *)&srio->atmu.port[port - 1] | |
5056c8e0 LG |
390 | .outbw[2].rowbar, |
391 | (CONFIG_SYS_SRIO2_MEM_PHYS | |
392 | + SRIO_MAINT_WIN_SIZE) >> 12); | |
393 | else | |
ff65f126 | 394 | out_be32((void *)&srio->atmu.port[port - 1] |
5056c8e0 LG |
395 | .outbw[2].rowbar, |
396 | (CONFIG_SYS_SRIO1_MEM_PHYS | |
397 | + SRIO_MAINT_WIN_SIZE) >> 12); | |
ff65f126 | 398 | out_be32((void *)&srio->atmu.port[port - 1] |
5056c8e0 LG |
399 | .outbw[2].rowar, |
400 | SRIO_OB_ATMU_AR_RW | |
401 | | atmu_size_mask(SRIO_RW_WIN_SIZE)); | |
402 | ||
403 | /* | |
404 | * Set the LCSBA1CSR register in slave | |
405 | * by the maint-outbound window | |
406 | */ | |
ff65f126 | 407 | if (port - 1) { |
5056c8e0 LG |
408 | out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT |
409 | + SRIO_LCSBA1CSR_OFFSET, | |
410 | SRIO_LCSBA1CSR); | |
411 | while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT | |
412 | + SRIO_LCSBA1CSR_OFFSET) | |
413 | != SRIO_LCSBA1CSR) | |
414 | ; | |
415 | /* | |
416 | * And then set the BRR register | |
417 | * to release slave core | |
418 | */ | |
419 | out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT | |
420 | + SRIO_MAINT_WIN_SIZE | |
b5f7c873 LG |
421 | + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, |
422 | CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); | |
5056c8e0 LG |
423 | } else { |
424 | out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT | |
425 | + SRIO_LCSBA1CSR_OFFSET, | |
426 | SRIO_LCSBA1CSR); | |
427 | while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT | |
428 | + SRIO_LCSBA1CSR_OFFSET) | |
429 | != SRIO_LCSBA1CSR) | |
430 | ; | |
431 | /* | |
432 | * And then set the BRR register | |
433 | * to release slave core | |
434 | */ | |
435 | out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT | |
436 | + SRIO_MAINT_WIN_SIZE | |
b5f7c873 LG |
437 | + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, |
438 | CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); | |
5056c8e0 LG |
439 | } |
440 | debug("SRIOBOOT - MASTER: " | |
441 | "Release slave successfully! Now the slave should start up!\n"); | |
442 | } | |
443 | } else | |
ff65f126 | 444 | debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port); |
5056c8e0 LG |
445 | } |
446 | #endif |