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692519b1 | 1 | /* |
8ac41e3e | 2 | * (C) Copyright 2006 - 2008 |
692519b1 RJ |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
6 | * Roland Dreier <rolandd@cisco.com> | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | */ | |
22 | ||
4dbee8a9 | 23 | /* define DEBUG for debugging output (obviously ;-)) */ |
ff68f66b | 24 | #if 0 |
4dbee8a9 SR |
25 | #define DEBUG |
26 | #endif | |
27 | ||
692519b1 RJ |
28 | #include <common.h> |
29 | #include <pci.h> | |
b578fb47 SR |
30 | #include <ppc4xx.h> |
31 | #include <asm/processor.h> | |
61f2b38a | 32 | #include <asm/io.h> |
06dfaeef | 33 | #include <asm/errno.h> |
692519b1 | 34 | |
8ac41e3e SR |
35 | #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ |
36 | defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ | |
59d1bda7 | 37 | defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE) |
692519b1 | 38 | |
c7c6da23 | 39 | #include <asm/4xx_pcie.h> |
692519b1 RJ |
40 | |
41 | enum { | |
42 | PTYPE_ENDPOINT = 0x0, | |
43 | PTYPE_LEGACY_ENDPOINT = 0x1, | |
44 | PTYPE_ROOT_PORT = 0x4, | |
45 | ||
46 | LNKW_X1 = 0x1, | |
47 | LNKW_X4 = 0x4, | |
48 | LNKW_X8 = 0x8 | |
49 | }; | |
50 | ||
b0b86746 SR |
51 | static struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS]; |
52 | ||
53 | /* | |
54 | * Per default, all cards are present, so we need to check if the | |
55 | * link comes up. | |
56 | */ | |
57 | int __board_pcie_card_present(int port) | |
58 | { | |
59 | return 1; | |
60 | } | |
61 | int board_pcie_card_present(int port) | |
62 | __attribute__((weak, alias("__board_pcie_card_present"))); | |
63 | ||
64 | /* | |
65 | * Some boards have runtime detection of the first and last PCIe | |
66 | * slot used, so let's provide weak default functions for the | |
67 | * common version. | |
68 | */ | |
69 | int __board_pcie_first(void) | |
70 | { | |
71 | return 0; | |
72 | } | |
73 | int board_pcie_first(void) | |
74 | __attribute__((weak, alias("__board_pcie_first"))); | |
75 | ||
76 | int __board_pcie_last(void) | |
77 | { | |
78 | return CONFIG_SYS_PCIE_NR_PORTS - 1; | |
79 | } | |
80 | int board_pcie_last(void) | |
81 | __attribute__((weak, alias("__board_pcie_last"))); | |
82 | ||
83 | void __board_pcie_setup_port(int port, int rootpoint) | |
84 | { | |
85 | /* noting in this weak default implementation */ | |
86 | } | |
87 | void board_pcie_setup_port(int port, int rootpoint) | |
88 | __attribute__((weak, alias("__board_pcie_setup_port"))); | |
89 | ||
90 | void pcie_setup_hoses(int busno) | |
91 | { | |
92 | struct pci_controller *hose; | |
93 | int i, bus; | |
94 | int ret = 0; | |
95 | char *env; | |
96 | unsigned int delay; | |
97 | int first = board_pcie_first(); | |
98 | int last = board_pcie_last(); | |
99 | ||
100 | /* | |
101 | * Assume we're called after the PCI(X) hose(s) are initialized, | |
102 | * which takes bus ID 0... and therefore start numbering PCIe's | |
103 | * from the next number. | |
104 | */ | |
105 | bus = busno; | |
106 | ||
107 | for (i = first; i <= last; i++) { | |
108 | /* | |
109 | * Some boards (e.g. Katmai) can detects via hardware | |
110 | * if a PCIe card is plugged, so let's check this. | |
111 | */ | |
112 | if (!board_pcie_card_present(i)) | |
113 | continue; | |
114 | ||
115 | if (is_end_point(i)) { | |
116 | board_pcie_setup_port(i, 0); | |
117 | ret = ppc4xx_init_pcie_endport(i); | |
118 | } else { | |
119 | board_pcie_setup_port(i, 1); | |
120 | ret = ppc4xx_init_pcie_rootport(i); | |
121 | } | |
122 | if (ret == -ENODEV) | |
123 | continue; | |
124 | if (ret) { | |
125 | printf("PCIE%d: initialization as %s failed\n", i, | |
126 | is_end_point(i) ? "endpoint" : "root-complex"); | |
127 | continue; | |
128 | } | |
129 | ||
130 | hose = &pcie_hose[i]; | |
131 | hose->first_busno = bus; | |
132 | hose->last_busno = bus; | |
133 | hose->current_busno = bus; | |
134 | ||
135 | /* setup mem resource */ | |
136 | pci_set_region(hose->regions + 0, | |
137 | CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, | |
138 | CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, | |
139 | CONFIG_SYS_PCIE_MEMSIZE, | |
140 | PCI_REGION_MEM); | |
141 | hose->region_count = 1; | |
142 | pci_register_hose(hose); | |
143 | ||
144 | if (is_end_point(i)) { | |
145 | ppc4xx_setup_pcie_endpoint(hose, i); | |
146 | /* | |
147 | * Reson for no scanning is endpoint can not generate | |
148 | * upstream configuration accesses. | |
149 | */ | |
150 | } else { | |
151 | ppc4xx_setup_pcie_rootpoint(hose, i); | |
152 | env = getenv ("pciscandelay"); | |
153 | if (env != NULL) { | |
154 | delay = simple_strtoul(env, NULL, 10); | |
155 | if (delay > 5) | |
156 | printf("Warning, expect noticable delay before " | |
157 | "PCIe scan due to 'pciscandelay' value!\n"); | |
158 | mdelay(delay * 1000); | |
159 | } | |
160 | ||
161 | /* | |
162 | * Config access can only go down stream | |
163 | */ | |
164 | hose->last_busno = pci_hose_scan(hose); | |
165 | bus = hose->last_busno + 1; | |
166 | } | |
167 | } | |
168 | } | |
b0b86746 | 169 | |
d4cb2d17 SR |
170 | static int validate_endpoint(struct pci_controller *hose) |
171 | { | |
6d0f6bcf | 172 | if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE) |
d4cb2d17 | 173 | return (is_end_point(0)); |
6d0f6bcf | 174 | else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE) |
d4cb2d17 | 175 | return (is_end_point(1)); |
6d0f6bcf JCPV |
176 | #if CONFIG_SYS_PCIE_NR_PORTS > 2 |
177 | else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE) | |
d4cb2d17 SR |
178 | return (is_end_point(2)); |
179 | #endif | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
7f191393 GB |
184 | static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) |
185 | { | |
186 | u8 *base = (u8*)hose->cfg_data; | |
187 | ||
188 | /* use local configuration space for the first bus */ | |
189 | if (PCI_BUS(devfn) == 0) { | |
6d0f6bcf JCPV |
190 | if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE) |
191 | base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE; | |
192 | if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE) | |
193 | base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE; | |
194 | #if CONFIG_SYS_PCIE_NR_PORTS > 2 | |
195 | if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE) | |
196 | base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE; | |
97923770 | 197 | #endif |
7f191393 GB |
198 | } |
199 | ||
200 | return base; | |
201 | } | |
202 | ||
15ee4734 | 203 | static void pcie_dmer_disable(void) |
c9240981 | 204 | { |
15ee4734 GB |
205 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), |
206 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); | |
207 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), | |
208 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); | |
6d0f6bcf | 209 | #if CONFIG_SYS_PCIE_NR_PORTS > 2 |
15ee4734 GB |
210 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), |
211 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); | |
97923770 | 212 | #endif |
c9240981 GB |
213 | } |
214 | ||
15ee4734 | 215 | static void pcie_dmer_enable(void) |
c9240981 | 216 | { |
15ee4734 GB |
217 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), |
218 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); | |
219 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), | |
220 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); | |
6d0f6bcf | 221 | #if CONFIG_SYS_PCIE_NR_PORTS > 2 |
15ee4734 GB |
222 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), |
223 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); | |
97923770 | 224 | #endif |
c9240981 GB |
225 | } |
226 | ||
692519b1 RJ |
227 | static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, |
228 | int offset, int len, u32 *val) { | |
229 | ||
7f191393 | 230 | u8 *address; |
692519b1 | 231 | *val = 0; |
7f191393 | 232 | |
d4cb2d17 SR |
233 | if (validate_endpoint(hose)) |
234 | return 0; /* No upstream config access */ | |
235 | ||
7f191393 GB |
236 | /* |
237 | * Bus numbers are relative to hose->first_busno | |
238 | */ | |
239 | devfn -= PCI_BDF(hose->first_busno, 0, 0); | |
240 | ||
692519b1 | 241 | /* |
7f191393 GB |
242 | * NOTICE: configuration space ranges are currenlty mapped only for |
243 | * the first 16 buses, so such limit must be imposed. In case more | |
244 | * buses are required the TLB settings in board/amcc/<board>/init.S | |
245 | * need to be altered accordingly (one bus takes 1 MB of memory space). | |
692519b1 | 246 | */ |
7f191393 | 247 | if (PCI_BUS(devfn) >= 16) |
692519b1 RJ |
248 | return 0; |
249 | ||
7f191393 GB |
250 | /* |
251 | * Only single device/single function is supported for the primary and | |
252 | * secondary buses of the 440SPe host bridge. | |
253 | */ | |
254 | if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && | |
255 | ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) | |
256 | return 0; | |
738815c0 | 257 | |
7f191393 | 258 | address = pcie_get_base(hose, devfn); |
692519b1 RJ |
259 | offset += devfn << 4; |
260 | ||
15ee4734 GB |
261 | /* |
262 | * Reading from configuration space of non-existing device can | |
263 | * generate transaction errors. For the read duration we suppress | |
264 | * assertion of machine check exceptions to avoid those. | |
265 | */ | |
266 | pcie_dmer_disable (); | |
267 | ||
97923770 | 268 | debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset); |
692519b1 RJ |
269 | switch (len) { |
270 | case 1: | |
15ee4734 | 271 | *val = in_8(hose->cfg_data + offset); |
692519b1 RJ |
272 | break; |
273 | case 2: | |
15ee4734 | 274 | *val = in_le16((u16 *)(hose->cfg_data + offset)); |
692519b1 RJ |
275 | break; |
276 | default: | |
15ee4734 | 277 | *val = in_le32((u32*)(hose->cfg_data + offset)); |
692519b1 RJ |
278 | break; |
279 | } | |
15ee4734 GB |
280 | |
281 | pcie_dmer_enable (); | |
282 | ||
692519b1 RJ |
283 | return 0; |
284 | } | |
285 | ||
286 | static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, | |
287 | int offset, int len, u32 val) { | |
288 | ||
7f191393 | 289 | u8 *address; |
738815c0 | 290 | |
d4cb2d17 SR |
291 | if (validate_endpoint(hose)) |
292 | return 0; /* No upstream config access */ | |
293 | ||
692519b1 | 294 | /* |
7f191393 | 295 | * Bus numbers are relative to hose->first_busno |
692519b1 | 296 | */ |
7f191393 | 297 | devfn -= PCI_BDF(hose->first_busno, 0, 0); |
738815c0 | 298 | |
7f191393 GB |
299 | /* |
300 | * Same constraints as in pcie_read_config(). | |
301 | */ | |
302 | if (PCI_BUS(devfn) >= 16) | |
692519b1 RJ |
303 | return 0; |
304 | ||
7f191393 GB |
305 | if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && |
306 | ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) | |
307 | return 0; | |
738815c0 | 308 | |
7f191393 | 309 | address = pcie_get_base(hose, devfn); |
692519b1 RJ |
310 | offset += devfn << 4; |
311 | ||
15ee4734 GB |
312 | /* |
313 | * Suppress MCK exceptions, similar to pcie_read_config() | |
314 | */ | |
315 | pcie_dmer_disable (); | |
316 | ||
692519b1 RJ |
317 | switch (len) { |
318 | case 1: | |
319 | out_8(hose->cfg_data + offset, val); | |
320 | break; | |
321 | case 2: | |
322 | out_le16((u16 *)(hose->cfg_data + offset), val); | |
323 | break; | |
324 | default: | |
325 | out_le32((u32 *)(hose->cfg_data + offset), val); | |
326 | break; | |
327 | } | |
15ee4734 GB |
328 | |
329 | pcie_dmer_enable (); | |
330 | ||
692519b1 RJ |
331 | return 0; |
332 | } | |
333 | ||
334 | int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) | |
335 | { | |
336 | u32 v; | |
337 | int rv; | |
338 | ||
7f191393 | 339 | rv = pcie_read_config(hose, dev, offset, 1, &v); |
692519b1 RJ |
340 | *val = (u8)v; |
341 | return rv; | |
342 | } | |
343 | ||
344 | int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) | |
345 | { | |
346 | u32 v; | |
347 | int rv; | |
348 | ||
349 | rv = pcie_read_config(hose, dev, offset, 2, &v); | |
350 | *val = (u16)v; | |
351 | return rv; | |
352 | } | |
353 | ||
354 | int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) | |
355 | { | |
356 | u32 v; | |
357 | int rv; | |
358 | ||
359 | rv = pcie_read_config(hose, dev, offset, 3, &v); | |
360 | *val = (u32)v; | |
361 | return rv; | |
362 | } | |
363 | ||
364 | int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) | |
365 | { | |
366 | return pcie_write_config(hose,(u32)dev,offset,1,val); | |
367 | } | |
368 | ||
369 | int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) | |
370 | { | |
371 | return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); | |
372 | } | |
373 | ||
374 | int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) | |
375 | { | |
376 | return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); | |
377 | } | |
378 | ||
97923770 | 379 | #if defined(CONFIG_440SPE) |
026f7110 | 380 | static void ppc4xx_setup_utl(u32 port) { |
692519b1 RJ |
381 | |
382 | volatile void *utl_base = NULL; | |
383 | ||
384 | /* | |
385 | * Map UTL registers | |
386 | */ | |
387 | switch (port) { | |
388 | case 0: | |
36b904a7 RJ |
389 | mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); |
390 | mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); | |
391 | mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); | |
692519b1 | 392 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); |
692519b1 RJ |
393 | break; |
394 | ||
395 | case 1: | |
36b904a7 RJ |
396 | mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); |
397 | mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); | |
398 | mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); | |
692519b1 | 399 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); |
692519b1 RJ |
400 | break; |
401 | ||
402 | case 2: | |
36b904a7 RJ |
403 | mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); |
404 | mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); | |
405 | mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); | |
692519b1 | 406 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); |
692519b1 RJ |
407 | break; |
408 | } | |
6d0f6bcf | 409 | utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); |
16850919 | 410 | |
692519b1 RJ |
411 | /* |
412 | * Set buffer allocations and then assert VRB and TXE. | |
413 | */ | |
414 | out_be32(utl_base + PEUTL_OUTTR, 0x08000000); | |
415 | out_be32(utl_base + PEUTL_INTR, 0x02000000); | |
416 | out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); | |
417 | out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); | |
418 | out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); | |
419 | out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); | |
420 | out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
36b904a7 | 421 | out_be32(utl_base + PEUTL_PCTL, 0x80800066); |
692519b1 RJ |
422 | } |
423 | ||
424 | static int check_error(void) | |
425 | { | |
426 | u32 valPE0, valPE1, valPE2; | |
427 | int err = 0; | |
428 | ||
429 | /* SDR0_PEGPLLLCT1 reset */ | |
8ac41e3e | 430 | if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) |
692519b1 | 431 | printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); |
692519b1 RJ |
432 | |
433 | valPE0 = SDR_READ(PESDR0_RCSSET); | |
434 | valPE1 = SDR_READ(PESDR1_RCSSET); | |
435 | valPE2 = SDR_READ(PESDR2_RCSSET); | |
436 | ||
437 | /* SDR0_PExRCSSET rstgu */ | |
438 | if (!(valPE0 & 0x01000000) || | |
439 | !(valPE1 & 0x01000000) || | |
440 | !(valPE2 & 0x01000000)) { | |
441 | printf("PCIE: SDR0_PExRCSSET rstgu error\n"); | |
442 | err = -1; | |
443 | } | |
444 | ||
445 | /* SDR0_PExRCSSET rstdl */ | |
446 | if (!(valPE0 & 0x00010000) || | |
447 | !(valPE1 & 0x00010000) || | |
448 | !(valPE2 & 0x00010000)) { | |
449 | printf("PCIE: SDR0_PExRCSSET rstdl error\n"); | |
450 | err = -1; | |
451 | } | |
452 | ||
453 | /* SDR0_PExRCSSET rstpyn */ | |
454 | if ((valPE0 & 0x00001000) || | |
455 | (valPE1 & 0x00001000) || | |
456 | (valPE2 & 0x00001000)) { | |
457 | printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); | |
458 | err = -1; | |
459 | } | |
460 | ||
461 | /* SDR0_PExRCSSET hldplb */ | |
462 | if ((valPE0 & 0x10000000) || | |
463 | (valPE1 & 0x10000000) || | |
464 | (valPE2 & 0x10000000)) { | |
465 | printf("PCIE: SDR0_PExRCSSET hldplb error\n"); | |
466 | err = -1; | |
467 | } | |
468 | ||
469 | /* SDR0_PExRCSSET rdy */ | |
470 | if ((valPE0 & 0x00100000) || | |
471 | (valPE1 & 0x00100000) || | |
472 | (valPE2 & 0x00100000)) { | |
473 | printf("PCIE: SDR0_PExRCSSET rdy error\n"); | |
474 | err = -1; | |
475 | } | |
476 | ||
477 | /* SDR0_PExRCSSET shutdown */ | |
478 | if ((valPE0 & 0x00000100) || | |
479 | (valPE1 & 0x00000100) || | |
480 | (valPE2 & 0x00000100)) { | |
481 | printf("PCIE: SDR0_PExRCSSET shutdown error\n"); | |
482 | err = -1; | |
483 | } | |
484 | return err; | |
485 | } | |
486 | ||
487 | /* | |
488 | * Initialize PCI Express core | |
489 | */ | |
026f7110 | 490 | int ppc4xx_init_pcie(void) |
692519b1 RJ |
491 | { |
492 | int time_out = 20; | |
493 | ||
494 | /* Set PLL clock receiver to LVPECL */ | |
495 | SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); | |
496 | ||
fcdb36b8 RS |
497 | if (check_error()) { |
498 | printf("ERROR: failed to set PCIe reference clock receiver --" | |
499 | "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1)); | |
500 | ||
692519b1 | 501 | return -1; |
fcdb36b8 RS |
502 | } |
503 | ||
504 | /* Did resistance calibration work? */ | |
505 | if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) { | |
506 | printf("ERROR: PCIe resistance calibration failed --" | |
507 | "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2)); | |
692519b1 | 508 | |
692519b1 RJ |
509 | return -1; |
510 | } | |
511 | /* De-assert reset of PCIe PLL, wait for lock */ | |
512 | SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); | |
fcdb36b8 | 513 | udelay(300); /* 300 uS is maximum time lock should take */ |
692519b1 | 514 | |
2b393b0f | 515 | while (time_out) { |
692519b1 RJ |
516 | if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { |
517 | time_out--; | |
fcdb36b8 | 518 | udelay(20); /* Wait 20 uS more if needed */ |
692519b1 RJ |
519 | } else |
520 | break; | |
521 | } | |
522 | if (!time_out) { | |
fcdb36b8 RS |
523 | printf("ERROR: PCIe PLL VCO output not locked to ref clock --" |
524 | "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3)); | |
525 | ||
692519b1 RJ |
526 | return -1; |
527 | } | |
528 | return 0; | |
529 | } | |
8ac41e3e SR |
530 | #endif |
531 | ||
532 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
533 | static void ppc4xx_setup_utl(u32 port) | |
534 | { | |
535 | volatile void *utl_base = NULL; | |
536 | ||
537 | /* | |
538 | * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK | |
539 | */ | |
540 | switch (port) { | |
541 | case 0: | |
6d0f6bcf JCPV |
542 | mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); |
543 | mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)); | |
8ac41e3e SR |
544 | mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */ |
545 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); | |
546 | break; | |
547 | ||
548 | case 1: | |
6d0f6bcf JCPV |
549 | mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); |
550 | mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE) | |
8ac41e3e SR |
551 | + 0x1000); |
552 | mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */ | |
553 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); | |
554 | break; | |
555 | } | |
6d0f6bcf | 556 | utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); |
8ac41e3e SR |
557 | |
558 | /* | |
559 | * Set buffer allocations and then assert VRB and TXE. | |
560 | */ | |
561 | out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */ | |
562 | out_be32(utl_base + PEUTL_OUTTR, 0x08000000); | |
563 | out_be32(utl_base + PEUTL_INTR, 0x02000000); | |
564 | out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */ | |
565 | out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */ | |
566 | out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000); | |
567 | out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */ | |
568 | out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
569 | out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */ | |
570 | } | |
571 | ||
572 | /* | |
573 | * TODO: double check PCI express SDR based on the latest user manual | |
53677ef1 WD |
574 | * Some registers specified here no longer exist.. has to be |
575 | * updated based on the final EAS spec. | |
8ac41e3e SR |
576 | */ |
577 | static int check_error(void) | |
578 | { | |
579 | u32 valPE0, valPE1; | |
580 | int err = 0; | |
581 | ||
582 | valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0)); | |
583 | valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1)); | |
584 | ||
585 | /* SDR0_PExRCSSET rstgu */ | |
586 | if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) { | |
587 | printf("PCIE: SDR0_PExRCSSET rstgu error\n"); | |
588 | err = -1; | |
589 | } | |
590 | ||
591 | /* SDR0_PExRCSSET rstdl */ | |
592 | if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) { | |
593 | printf("PCIE: SDR0_PExRCSSET rstdl error\n"); | |
594 | err = -1; | |
595 | } | |
596 | ||
597 | /* SDR0_PExRCSSET rstpyn */ | |
598 | if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) { | |
599 | printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); | |
600 | err = -1; | |
601 | } | |
602 | ||
603 | /* SDR0_PExRCSSET hldplb */ | |
604 | if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) { | |
605 | printf("PCIE: SDR0_PExRCSSET hldplb error\n"); | |
606 | err = -1; | |
607 | } | |
608 | ||
609 | /* SDR0_PExRCSSET rdy */ | |
610 | if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) { | |
611 | printf("PCIE: SDR0_PExRCSSET rdy error\n"); | |
612 | err = -1; | |
613 | } | |
614 | ||
615 | return err; | |
616 | } | |
617 | ||
618 | /* | |
619 | * Initialize PCI Express core as described in User Manual | |
620 | * TODO: double check PE SDR PLL Register with the updated user manual. | |
621 | */ | |
622 | int ppc4xx_init_pcie(void) | |
623 | { | |
624 | if (check_error()) | |
625 | return -1; | |
626 | ||
627 | return 0; | |
628 | } | |
629 | #endif /* CONFIG_460EX */ | |
630 | ||
631 | #if defined(CONFIG_405EX) | |
f31d38b9 SR |
632 | static void ppc4xx_setup_utl(u32 port) |
633 | { | |
634 | u32 utl_base; | |
635 | ||
636 | /* | |
637 | * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK | |
638 | */ | |
639 | switch (port) { | |
640 | case 0: | |
641 | mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); | |
6d0f6bcf | 642 | mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE); |
653811a3 | 643 | mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */ |
f31d38b9 SR |
644 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); |
645 | break; | |
646 | ||
647 | case 1: | |
648 | mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); | |
6d0f6bcf | 649 | mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE); |
653811a3 | 650 | mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */ |
f31d38b9 SR |
651 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); |
652 | ||
653 | break; | |
654 | } | |
6d0f6bcf | 655 | utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE; |
f31d38b9 SR |
656 | |
657 | /* | |
658 | * Set buffer allocations and then assert VRB and TXE. | |
659 | */ | |
660 | out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000); | |
661 | out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000); | |
662 | out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000); | |
663 | out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000); | |
664 | out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000); | |
665 | out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000); | |
666 | out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000); | |
667 | out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066); | |
668 | ||
669 | out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c); | |
670 | out_be32((u32 *)(utl_base + PEUTL_RCSTA), | |
671 | in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000); | |
672 | } | |
673 | ||
97923770 SR |
674 | int ppc4xx_init_pcie(void) |
675 | { | |
676 | /* | |
677 | * Nothing to do on 405EX | |
678 | */ | |
679 | return 0; | |
680 | } | |
8ac41e3e | 681 | #endif /* CONFIG_405EX */ |
692519b1 | 682 | |
2b393b0f | 683 | /* |
03d344bb SR |
684 | * Board-specific pcie initialization |
685 | * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed | |
686 | */ | |
687 | ||
688 | /* | |
689 | * Initialize various parts of the PCI Express core for our port: | |
690 | * | |
691 | * - Set as a root port and enable max width | |
692 | * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). | |
693 | * - Set up UTL configuration. | |
694 | * - Increase SERDES drive strength to levels suggested by AMCC. | |
695 | * - De-assert RSTPYN, RSTDL and RSTGU. | |
696 | * | |
697 | * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it | |
698 | * with default setting 0x11310000. The register has new fields, | |
699 | * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core | |
700 | * hang. | |
701 | */ | |
702 | #if defined(CONFIG_440SPE) | |
703 | int __ppc4xx_init_pcie_port_hw(int port, int rootport) | |
704 | { | |
705 | u32 val = 1 << 24; | |
706 | u32 utlset1; | |
707 | ||
708 | if (rootport) { | |
709 | val = PTYPE_ROOT_PORT << 20; | |
710 | utlset1 = 0x21222222; | |
711 | } else { | |
712 | val = PTYPE_LEGACY_ENDPOINT << 20; | |
713 | utlset1 = 0x20222222; | |
714 | } | |
715 | ||
716 | if (port == 0) | |
717 | val |= LNKW_X8 << 12; | |
718 | else | |
719 | val |= LNKW_X4 << 12; | |
720 | ||
721 | SDR_WRITE(SDRN_PESDR_DLPSET(port), val); | |
722 | SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); | |
723 | if (!ppc440spe_revB()) | |
724 | SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000); | |
725 | SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000); | |
726 | SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000); | |
727 | SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000); | |
728 | SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000); | |
729 | if (port == 0) { | |
730 | SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); | |
731 | SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); | |
732 | SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); | |
733 | SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); | |
734 | } | |
735 | SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) & | |
736 | ~(1 << 24 | 1 << 16)) | 1 << 12); | |
737 | ||
738 | return 0; | |
739 | } | |
740 | #endif /* CONFIG_440SPE */ | |
741 | ||
8ac41e3e SR |
742 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
743 | int __ppc4xx_init_pcie_port_hw(int port, int rootport) | |
744 | { | |
dd1c5523 | 745 | u32 val; |
8ac41e3e SR |
746 | u32 utlset1; |
747 | ||
dd1c5523 | 748 | if (rootport) |
8ac41e3e | 749 | val = PTYPE_ROOT_PORT << 20; |
dd1c5523 | 750 | else |
8ac41e3e | 751 | val = PTYPE_LEGACY_ENDPOINT << 20; |
8ac41e3e SR |
752 | |
753 | if (port == 0) { | |
754 | val |= LNKW_X1 << 12; | |
dd1c5523 | 755 | utlset1 = 0x20000000; |
8ac41e3e SR |
756 | } else { |
757 | val |= LNKW_X4 << 12; | |
dd1c5523 | 758 | utlset1 = 0x20101101; |
8ac41e3e SR |
759 | } |
760 | ||
761 | SDR_WRITE(SDRN_PESDR_DLPSET(port), val); | |
762 | SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); | |
763 | SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000); | |
764 | ||
765 | switch (port) { | |
766 | case 0: | |
767 | SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230); | |
5d4b3d2b | 768 | SDR_WRITE(PESDR0_L0DRV, 0x00000130); |
8ac41e3e SR |
769 | SDR_WRITE(PESDR0_L0CLK, 0x00000006); |
770 | ||
771 | SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000); | |
772 | break; | |
773 | ||
774 | case 1: | |
775 | SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230); | |
776 | SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230); | |
777 | SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230); | |
778 | SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230); | |
5d4b3d2b TM |
779 | SDR_WRITE(PESDR1_L0DRV, 0x00000130); |
780 | SDR_WRITE(PESDR1_L1DRV, 0x00000130); | |
781 | SDR_WRITE(PESDR1_L2DRV, 0x00000130); | |
782 | SDR_WRITE(PESDR1_L3DRV, 0x00000130); | |
8ac41e3e SR |
783 | SDR_WRITE(PESDR1_L0CLK, 0x00000006); |
784 | SDR_WRITE(PESDR1_L1CLK, 0x00000006); | |
785 | SDR_WRITE(PESDR1_L2CLK, 0x00000006); | |
786 | SDR_WRITE(PESDR1_L3CLK, 0x00000006); | |
787 | ||
788 | SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000); | |
789 | break; | |
790 | } | |
791 | ||
792 | SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) | | |
793 | (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); | |
794 | ||
795 | /* Poll for PHY reset */ | |
796 | switch (port) { | |
797 | case 0: | |
798 | while (!(SDR_READ(PESDR0_RSTSTA) & 0x1)) | |
799 | udelay(10); | |
800 | break; | |
801 | case 1: | |
802 | while (!(SDR_READ(PESDR1_RSTSTA) & 0x1)) | |
803 | udelay(10); | |
804 | break; | |
805 | } | |
806 | ||
807 | SDR_WRITE(SDRN_PESDR_RCSSET(port), | |
808 | (SDR_READ(SDRN_PESDR_RCSSET(port)) & | |
809 | ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | | |
810 | PESDRx_RCSSET_RSTPYN); | |
811 | ||
812 | return 0; | |
813 | } | |
814 | #endif /* CONFIG_440SPE */ | |
815 | ||
03d344bb SR |
816 | #if defined(CONFIG_405EX) |
817 | int __ppc4xx_init_pcie_port_hw(int port, int rootport) | |
818 | { | |
819 | u32 val; | |
820 | ||
821 | if (rootport) | |
822 | val = 0x00401000; | |
823 | else | |
824 | val = 0x00101000; | |
825 | ||
826 | SDR_WRITE(SDRN_PESDR_DLPSET(port), val); | |
7d0a4066 SR |
827 | SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000); |
828 | SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000); | |
03d344bb SR |
829 | SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); |
830 | SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); | |
831 | ||
832 | /* Assert the PE0_PHY reset */ | |
833 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000); | |
834 | udelay(1000); | |
835 | ||
836 | /* deassert the PE0_hotreset */ | |
5cb4af47 SR |
837 | if (is_end_point(port)) |
838 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000); | |
839 | else | |
840 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); | |
03d344bb SR |
841 | |
842 | /* poll for phy !reset */ | |
843 | while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) | |
844 | ; | |
845 | ||
846 | /* deassert the PE0_gpl_utl_reset */ | |
847 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000); | |
848 | ||
849 | if (port == 0) | |
850 | mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */ | |
851 | else | |
852 | mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */ | |
853 | ||
854 | return 0; | |
855 | } | |
856 | #endif /* CONFIG_405EX */ | |
857 | ||
858 | int ppc4xx_init_pcie_port_hw(int port, int rootport) | |
653811a3 | 859 | __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); |
03d344bb SR |
860 | |
861 | /* | |
862 | * We map PCI Express configuration access into the 512MB regions | |
863 | * | |
864 | * NOTICE: revB is very strict about PLB real addressess and ranges to | |
865 | * be mapped for config space; it seems to only work with d_nnnn_nnnn | |
866 | * range (hangs the core upon config transaction attempts when set | |
867 | * otherwise) while revA uses c_nnnn_nnnn. | |
868 | * | |
8ac41e3e | 869 | * For 440SPe revA: |
03d344bb SR |
870 | * PCIE0: 0xc_4000_0000 |
871 | * PCIE1: 0xc_8000_0000 | |
872 | * PCIE2: 0xc_c000_0000 | |
873 | * | |
8ac41e3e | 874 | * For 440SPe revB: |
03d344bb SR |
875 | * PCIE0: 0xd_0000_0000 |
876 | * PCIE1: 0xd_2000_0000 | |
877 | * PCIE2: 0xd_4000_0000 | |
878 | * | |
879 | * For 405EX: | |
880 | * PCIE0: 0xa000_0000 | |
881 | * PCIE1: 0xc000_0000 | |
8ac41e3e SR |
882 | * |
883 | * For 460EX/GT: | |
884 | * PCIE0: 0xd_0000_0000 | |
885 | * PCIE1: 0xd_2000_0000 | |
03d344bb SR |
886 | */ |
887 | static inline u64 ppc4xx_get_cfgaddr(int port) | |
888 | { | |
889 | #if defined(CONFIG_405EX) | |
890 | if (port == 0) | |
6d0f6bcf | 891 | return (u64)CONFIG_SYS_PCIE0_CFGBASE; |
03d344bb | 892 | else |
6d0f6bcf | 893 | return (u64)CONFIG_SYS_PCIE1_CFGBASE; |
03d344bb SR |
894 | #endif |
895 | #if defined(CONFIG_440SPE) | |
896 | if (ppc440spe_revB()) { | |
897 | switch (port) { | |
898 | default: /* to satisfy compiler */ | |
899 | case 0: | |
900 | return 0x0000000d00000000ULL; | |
901 | case 1: | |
902 | return 0x0000000d20000000ULL; | |
903 | case 2: | |
904 | return 0x0000000d40000000ULL; | |
905 | } | |
906 | } else { | |
907 | switch (port) { | |
908 | default: /* to satisfy compiler */ | |
909 | case 0: | |
910 | return 0x0000000c40000000ULL; | |
911 | case 1: | |
912 | return 0x0000000c80000000ULL; | |
913 | case 2: | |
914 | return 0x0000000cc0000000ULL; | |
915 | } | |
916 | } | |
917 | #endif | |
8ac41e3e SR |
918 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
919 | if (port == 0) | |
920 | return 0x0000000d00000000ULL; | |
921 | else | |
922 | return 0x0000000d20000000ULL; | |
923 | #endif | |
03d344bb SR |
924 | } |
925 | ||
926 | /* | |
64917ca3 | 927 | * 4xx boards as endpoint and root point setup |
2b393b0f SR |
928 | * and |
929 | * testing inbound and out bound windows | |
930 | * | |
03d344bb | 931 | * 4xx boards can be plugged into another 4xx boards or you can get PCI-E |
2b393b0f SR |
932 | * cable which can be used to setup loop back from one port to another port. |
933 | * Please rememeber that unless there is a endpoint plugged in to root port it | |
934 | * will not initialize. It is the same in case of endpoint , unless there is | |
935 | * root port attached it will not initialize. | |
936 | * | |
937 | * In this release of software all the PCI-E ports are configured as either | |
938 | * endpoint or rootpoint.In future we will have support for selective ports | |
939 | * setup as endpoint and root point in single board. | |
940 | * | |
941 | * Once your board came up as root point , you can verify by reading | |
942 | * /proc/bus/pci/devices. Where you can see the configuration registers | |
64917ca3 | 943 | * of endpoint device attached to the port. |
2b393b0f | 944 | * |
03d344bb SR |
945 | * Enpoint cofiguration can be verified by connecting 4xx board to any |
946 | * host or another 4xx board. Then try to scan the device. In case of | |
2b393b0f SR |
947 | * linux use "lspci" or appripriate os command. |
948 | * | |
03d344bb | 949 | * How do I verify the inbound and out bound windows ? (4xx to 4xx) |
2b393b0f SR |
950 | * in this configuration inbound and outbound windows are setup to access |
951 | * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address | |
952 | * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, | |
953 | * This is waere your POM(PLB out bound memory window) mapped. then | |
03d344bb | 954 | * read the data from other 4xx board's u-boot prompt at address |
2b393b0f SR |
955 | * 0x9000 0000(SRAM). Data should match. |
956 | * In case of inbound , write data to u-boot command prompt at 0xb000 0000 | |
957 | * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check | |
958 | * data at 0x9000 0000(SRAM).Data should match. | |
959 | */ | |
03d344bb | 960 | int ppc4xx_init_pcie_port(int port, int rootport) |
692519b1 RJ |
961 | { |
962 | static int core_init; | |
963 | volatile u32 val = 0; | |
964 | int attempts; | |
03d344bb SR |
965 | u64 addr; |
966 | u32 low, high; | |
692519b1 RJ |
967 | |
968 | if (!core_init) { | |
026f7110 | 969 | if (ppc4xx_init_pcie()) |
692519b1 | 970 | return -1; |
d4cb2d17 | 971 | ++core_init; |
692519b1 RJ |
972 | } |
973 | ||
974 | /* | |
03d344bb | 975 | * Initialize various parts of the PCI Express core for our port |
692519b1 | 976 | */ |
03d344bb | 977 | ppc4xx_init_pcie_port_hw(port, rootport); |
692519b1 | 978 | |
2b393b0f SR |
979 | /* |
980 | * Notice: the following delay has critical impact on device | |
981 | * initialization - if too short (<50ms) the link doesn't get up. | |
982 | */ | |
983 | mdelay(100); | |
984 | ||
6d952892 | 985 | val = SDR_READ(SDRN_PESDR_RCSSTS(port)); |
2b393b0f SR |
986 | if (val & (1 << 20)) { |
987 | printf("PCIE%d: PGRST failed %08x\n", port, val); | |
988 | return -1; | |
989 | } | |
990 | ||
991 | /* | |
992 | * Verify link is up | |
993 | */ | |
6d952892 | 994 | val = SDR_READ(SDRN_PESDR_LOOP(port)); |
2b393b0f SR |
995 | if (!(val & 0x00001000)) { |
996 | printf("PCIE%d: link is not up.\n", port); | |
06dfaeef | 997 | return -ENODEV; |
2b393b0f SR |
998 | } |
999 | ||
1000 | /* | |
1001 | * Setup UTL registers - but only on revA! | |
1002 | * We use default settings for revB chip. | |
1003 | */ | |
1004 | if (!ppc440spe_revB()) | |
026f7110 | 1005 | ppc4xx_setup_utl(port); |
2b393b0f SR |
1006 | |
1007 | /* | |
1008 | * We map PCI Express configuration access into the 512MB regions | |
2b393b0f | 1009 | */ |
03d344bb | 1010 | addr = ppc4xx_get_cfgaddr(port); |
97923770 SR |
1011 | low = U64_TO_U32_LOW(addr); |
1012 | high = U64_TO_U32_HIGH(addr); | |
2b393b0f SR |
1013 | |
1014 | switch (port) { | |
1015 | case 0: | |
03d344bb SR |
1016 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high); |
1017 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low); | |
2b393b0f SR |
1018 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ |
1019 | break; | |
2b393b0f | 1020 | case 1: |
03d344bb SR |
1021 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high); |
1022 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); | |
2b393b0f SR |
1023 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ |
1024 | break; | |
6d0f6bcf | 1025 | #if CONFIG_SYS_PCIE_NR_PORTS > 2 |
2b393b0f | 1026 | case 2: |
03d344bb SR |
1027 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); |
1028 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); | |
2b393b0f SR |
1029 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ |
1030 | break; | |
97923770 | 1031 | #endif |
2b393b0f SR |
1032 | } |
1033 | ||
1034 | /* | |
1035 | * Check for VC0 active and assert RDY. | |
1036 | */ | |
1037 | attempts = 10; | |
6d952892 | 1038 | while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { |
03d344bb SR |
1039 | if (!(attempts--)) { |
1040 | printf("PCIE%d: VC0 not active\n", port); | |
1041 | return -1; | |
2b393b0f | 1042 | } |
03d344bb | 1043 | mdelay(1000); |
2b393b0f | 1044 | } |
6d952892 SR |
1045 | SDR_WRITE(SDRN_PESDR_RCSSET(port), |
1046 | SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20); | |
2b393b0f SR |
1047 | mdelay(100); |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
03d344bb | 1052 | int ppc4xx_init_pcie_rootport(int port) |
2b393b0f | 1053 | { |
03d344bb SR |
1054 | return ppc4xx_init_pcie_port(port, 1); |
1055 | } | |
692519b1 | 1056 | |
03d344bb SR |
1057 | int ppc4xx_init_pcie_endport(int port) |
1058 | { | |
1059 | return ppc4xx_init_pcie_port(port, 0); | |
692519b1 RJ |
1060 | } |
1061 | ||
026f7110 | 1062 | void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) |
692519b1 RJ |
1063 | { |
1064 | volatile void *mbase = NULL; | |
2b393b0f | 1065 | volatile void *rmbase = NULL; |
692519b1 RJ |
1066 | |
1067 | pci_set_ops(hose, | |
03d344bb SR |
1068 | pcie_read_config_byte, |
1069 | pcie_read_config_word, | |
1070 | pcie_read_config_dword, | |
1071 | pcie_write_config_byte, | |
1072 | pcie_write_config_word, | |
1073 | pcie_write_config_dword); | |
2b393b0f SR |
1074 | |
1075 | switch (port) { | |
692519b1 | 1076 | case 0: |
6d0f6bcf JCPV |
1077 | mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; |
1078 | rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE; | |
1079 | hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; | |
692519b1 RJ |
1080 | break; |
1081 | case 1: | |
6d0f6bcf JCPV |
1082 | mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; |
1083 | rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE; | |
1084 | hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; | |
692519b1 | 1085 | break; |
6d0f6bcf | 1086 | #if CONFIG_SYS_PCIE_NR_PORTS > 2 |
692519b1 | 1087 | case 2: |
6d0f6bcf JCPV |
1088 | mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; |
1089 | rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE; | |
1090 | hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; | |
692519b1 | 1091 | break; |
97923770 | 1092 | #endif |
692519b1 RJ |
1093 | } |
1094 | ||
1095 | /* | |
1096 | * Set bus numbers on our root port | |
1097 | */ | |
7f191393 GB |
1098 | out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); |
1099 | out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); | |
1100 | out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); | |
692519b1 RJ |
1101 | |
1102 | /* | |
1103 | * Set up outbound translation to hose->mem_space from PLB | |
1104 | * addresses at an offset of 0xd_0000_0000. We set the low | |
1105 | * bits of the mask to 11 to turn off splitting into 8 | |
1106 | * subregions and to enable the outbound translation. | |
1107 | */ | |
1108 | out_le32(mbase + PECFG_POM0LAH, 0x00000000); | |
6d0f6bcf JCPV |
1109 | out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE + |
1110 | port * CONFIG_SYS_PCIE_MEMSIZE); | |
4dbee8a9 SR |
1111 | debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH), |
1112 | in_le32(mbase + PECFG_POM0LAL)); | |
692519b1 RJ |
1113 | |
1114 | switch (port) { | |
1115 | case 0: | |
6d0f6bcf JCPV |
1116 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); |
1117 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + | |
1118 | port * CONFIG_SYS_PCIE_MEMSIZE); | |
692519b1 RJ |
1119 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); |
1120 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), | |
6d0f6bcf | 1121 | ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); |
4dbee8a9 SR |
1122 | debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", |
1123 | mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)), | |
1124 | mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)), | |
1125 | mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)), | |
1126 | mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); | |
692519b1 RJ |
1127 | break; |
1128 | case 1: | |
6d0f6bcf JCPV |
1129 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); |
1130 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + | |
1131 | port * CONFIG_SYS_PCIE_MEMSIZE); | |
692519b1 RJ |
1132 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); |
1133 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), | |
6d0f6bcf | 1134 | ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); |
4dbee8a9 SR |
1135 | debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", |
1136 | mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)), | |
1137 | mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)), | |
1138 | mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), | |
1139 | mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); | |
692519b1 | 1140 | break; |
6d0f6bcf | 1141 | #if CONFIG_SYS_PCIE_NR_PORTS > 2 |
692519b1 | 1142 | case 2: |
6d0f6bcf JCPV |
1143 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); |
1144 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + | |
1145 | port * CONFIG_SYS_PCIE_MEMSIZE); | |
692519b1 RJ |
1146 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); |
1147 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), | |
6d0f6bcf | 1148 | ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); |
4dbee8a9 SR |
1149 | debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", |
1150 | mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)), | |
1151 | mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)), | |
1152 | mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)), | |
1153 | mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2))); | |
692519b1 | 1154 | break; |
97923770 | 1155 | #endif |
692519b1 RJ |
1156 | } |
1157 | ||
b4996d6b | 1158 | /* Set up 4GB inbound memory window at 0 */ |
692519b1 RJ |
1159 | out_le32(mbase + PCI_BASE_ADDRESS_0, 0); |
1160 | out_le32(mbase + PCI_BASE_ADDRESS_1, 0); | |
b4996d6b | 1161 | out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff); |
692519b1 | 1162 | out_le32(mbase + PECFG_BAR0LMPA, 0); |
2b393b0f SR |
1163 | |
1164 | out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); | |
1165 | out_le32(mbase + PECFG_PIM01SAL, 0x00000000); | |
692519b1 RJ |
1166 | out_le32(mbase + PECFG_PIM0LAL, 0); |
1167 | out_le32(mbase + PECFG_PIM0LAH, 0); | |
97923770 SR |
1168 | out_le32(mbase + PECFG_PIM1LAL, 0x00000000); |
1169 | out_le32(mbase + PECFG_PIM1LAH, 0x00000004); | |
2b393b0f SR |
1170 | out_le32(mbase + PECFG_PIMEN, 0x1); |
1171 | ||
1172 | /* Enable I/O, Mem, and Busmaster cycles */ | |
1173 | out_le16((u16 *)(mbase + PCI_COMMAND), | |
1174 | in_le16((u16 *)(mbase + PCI_COMMAND)) | | |
1175 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
738815c0 | 1176 | |
7f191393 | 1177 | /* Set Device and Vendor Id */ |
97923770 SR |
1178 | out_le16(mbase + 0x200, 0xaaa0 + port); |
1179 | out_le16(mbase + 0x202, 0xbed0 + port); | |
7f191393 GB |
1180 | |
1181 | /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ | |
1182 | out_le32(mbase + 0x208, 0x06040001); | |
1183 | ||
19e93b1e | 1184 | printf("PCIE%d: successfully set as root-complex\n", port); |
2b393b0f SR |
1185 | } |
1186 | ||
026f7110 | 1187 | int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) |
2b393b0f SR |
1188 | { |
1189 | volatile void *mbase = NULL; | |
1190 | int attempts = 0; | |
1191 | ||
1192 | pci_set_ops(hose, | |
1193 | pcie_read_config_byte, | |
1194 | pcie_read_config_word, | |
1195 | pcie_read_config_dword, | |
1196 | pcie_write_config_byte, | |
1197 | pcie_write_config_word, | |
1198 | pcie_write_config_dword); | |
1199 | ||
1200 | switch (port) { | |
1201 | case 0: | |
6d0f6bcf JCPV |
1202 | mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; |
1203 | hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; | |
2b393b0f SR |
1204 | break; |
1205 | case 1: | |
6d0f6bcf JCPV |
1206 | mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; |
1207 | hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; | |
2b393b0f | 1208 | break; |
6d0f6bcf | 1209 | #if defined(CONFIG_SYS_PCIE2_CFGBASE) |
2b393b0f | 1210 | case 2: |
6d0f6bcf JCPV |
1211 | mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; |
1212 | hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; | |
2b393b0f | 1213 | break; |
97923770 | 1214 | #endif |
2b393b0f SR |
1215 | } |
1216 | ||
1217 | /* | |
1218 | * Set up outbound translation to hose->mem_space from PLB | |
1219 | * addresses at an offset of 0xd_0000_0000. We set the low | |
1220 | * bits of the mask to 11 to turn off splitting into 8 | |
1221 | * subregions and to enable the outbound translation. | |
1222 | */ | |
1223 | out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); | |
1224 | out_le32(mbase + PECFG_POM0LAL, 0x00001000); | |
1225 | ||
1226 | switch (port) { | |
1227 | case 0: | |
6d0f6bcf JCPV |
1228 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); |
1229 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + | |
1230 | port * CONFIG_SYS_PCIE_MEMSIZE); | |
2b393b0f SR |
1231 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); |
1232 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), | |
6d0f6bcf | 1233 | ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); |
2b393b0f SR |
1234 | break; |
1235 | case 1: | |
6d0f6bcf JCPV |
1236 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); |
1237 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + | |
1238 | port * CONFIG_SYS_PCIE_MEMSIZE); | |
2b393b0f SR |
1239 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); |
1240 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), | |
6d0f6bcf | 1241 | ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); |
2b393b0f | 1242 | break; |
6d0f6bcf | 1243 | #if CONFIG_SYS_PCIE_NR_PORTS > 2 |
2b393b0f | 1244 | case 2: |
6d0f6bcf JCPV |
1245 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); |
1246 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + | |
1247 | port * CONFIG_SYS_PCIE_MEMSIZE); | |
2b393b0f SR |
1248 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); |
1249 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), | |
6d0f6bcf | 1250 | ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); |
2b393b0f | 1251 | break; |
97923770 | 1252 | #endif |
2b393b0f SR |
1253 | } |
1254 | ||
5cb4af47 | 1255 | /* Set up 64MB inbound memory window at 0 */ |
2b393b0f SR |
1256 | out_le32(mbase + PCI_BASE_ADDRESS_0, 0); |
1257 | out_le32(mbase + PCI_BASE_ADDRESS_1, 0); | |
5cb4af47 SR |
1258 | |
1259 | out_le32(mbase + PECFG_PIM01SAH, 0xffffffff); | |
1260 | out_le32(mbase + PECFG_PIM01SAL, 0xfc000000); | |
1261 | ||
1262 | /* Setup BAR0 */ | |
1263 | out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff); | |
1264 | out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64); | |
1265 | ||
1266 | /* Disable BAR1 & BAR2 */ | |
1267 | out_le32(mbase + PECFG_BAR1MPA, 0); | |
1268 | out_le32(mbase + PECFG_BAR2HMPA, 0); | |
1269 | out_le32(mbase + PECFG_BAR2LMPA, 0); | |
1270 | ||
6d0f6bcf JCPV |
1271 | out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE)); |
1272 | out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE)); | |
692519b1 RJ |
1273 | out_le32(mbase + PECFG_PIMEN, 0x1); |
1274 | ||
1275 | /* Enable I/O, Mem, and Busmaster cycles */ | |
1276 | out_le16((u16 *)(mbase + PCI_COMMAND), | |
03d344bb SR |
1277 | in_le16((u16 *)(mbase + PCI_COMMAND)) | |
1278 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
97923770 SR |
1279 | out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */ |
1280 | out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */ | |
03d344bb | 1281 | |
5cb4af47 SR |
1282 | /* Set Class Code to Processor/PPC */ |
1283 | out_le32(mbase + 0x208, 0x0b200001); | |
1284 | ||
2b393b0f | 1285 | attempts = 10; |
6d952892 | 1286 | while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { |
03d344bb SR |
1287 | if (!(attempts--)) { |
1288 | printf("PCIE%d: BME not active\n", port); | |
1289 | return -1; | |
2b393b0f | 1290 | } |
03d344bb | 1291 | mdelay(1000); |
2b393b0f | 1292 | } |
03d344bb | 1293 | |
19e93b1e | 1294 | printf("PCIE%d: successfully set as endpoint\n", port); |
2b393b0f SR |
1295 | |
1296 | return 0; | |
692519b1 | 1297 | } |
5fb692ca | 1298 | #endif /* CONFIG_440SPE && CONFIG_PCI */ |