[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / fdt.c

/*
 * (C) Copyright 2007-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <ppc4xx.h>

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
#include <asm/4xx_pcie.h>

DECLARE_GLOBAL_DATA_PTR;

void __ft_board_setup(void *blob, bd_t *bd)
{
	int rc;
	int i;
	u32 bxcr;
	u32 ranges[EBC_NUM_BANKS * 4];
	u32 *p = ranges;
	char ebc_path[] = "/plb/opb/ebc";

	ft_cpu_setup(blob, bd);

	/*
	 * Read 4xx EBC bus bridge registers to get mappings of the
	 * peripheral banks into the OPB/PLB address space
	 */
	for (i = 0; i < EBC_NUM_BANKS; i++) {
		mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
		bxcr = mfdcr(EBC0_CFGDATA);

		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
			*p++ = i;
			*p++ = 0;
			*p++ = bxcr & EBC_BXCR_BAS_MASK;
			*p++ = EBC_BXCR_BANK_SIZE(bxcr);

#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
			/* Try to update reg property in nor flash node too */
			fdt_fixup_nor_flash_size(blob, i,
						 EBC_BXCR_BANK_SIZE(bxcr));
#endif
		}
	}

	/* Some 405 PPC's have EBC as direct PLB child in the dts */
	if (fdt_path_offset(blob, ebc_path) < 0)
		strcpy(ebc_path, "/plb/ebc");
	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
				  (p - ranges) * sizeof(u32), 1);
	if (rc) {
		printf("Unable to update property EBC mappings, err=%s\n",
		       fdt_strerror(rc));
	}
}
void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));

/*
 * Fixup all PCIe nodes by setting the device_type property
 * to "pci-endpoint" instead is "pci" for endpoint ports.
 * This property will get checked later by the Linux driver
 * to properly configure the PCIe port in Linux (again).
 */
void fdt_pcie_setup(void *blob)
{
	const char *compat = "ibm,plb-pciex";
	const char *prop = "device_type";
	const char *prop_val = "pci-endpoint";
	const u32 *port;
	int no;
	int rc;

	/* Search first PCIe node */
	no = fdt_node_offset_by_compatible(blob, -1, compat);
	while (no != -FDT_ERR_NOTFOUND) {
		port = fdt_getprop(blob, no, "port", NULL);
		if (port == NULL) {
			printf("WARNING: could not find port property\n");
		} else {
			if (is_end_point(*port)) {
				rc = fdt_setprop(blob, no, prop, prop_val,
						 strlen(prop_val) + 1);
				if (rc < 0)
					printf("WARNING: could not set %s for %s: %s.\n",
					       prop, compat, fdt_strerror(rc));
			}
		}

		/* Jump to next PCIe node */
		no = fdt_node_offset_by_compatible(blob, no, compat);
	}
}

void ft_cpu_setup(void *blob, bd_t *bd)
{
	sys_info_t sys_info;
	int off, ndepth = 0;

	get_sys_info(&sys_info);

	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
			     bd->bi_intfreq, 1);
	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
			     bd->bi_intfreq, 1);
	do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
	do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);

	if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
		do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
			sys_info.freqEBC, 1);
	else
		do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
			sys_info.freqEBC, 1);

	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);

	/*
	 * Fixup all UART clocks for CPU internal UARTs
	 * (only these UARTs are definitely clocked by gd->uart_clk)
	 *
	 * These UARTs are direct childs of /plb/opb. This code
	 * does not touch any UARTs that are connected to the ebc.
	 */
	off = fdt_path_offset(blob, "/plb/opb");
	while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
		/*
		 * process all sub nodes and stop when we are back
		 * at the starting depth
		 */
		if (ndepth <= 0)
			break;

		/* only update direct childs */
		if ((ndepth == 1) &&
		    (fdt_node_check_compatible(blob, off, "ns16550") == 0))
			fdt_setprop(blob, off,
				    "clock-frequency",
				    (void*)&(gd->uart_clk), 4);
	}

	/*
	 * Fixup all ethernet nodes
	 * Note: aliases in the dts are required for this
	 */
	fdt_fixup_ethernet(blob);

	/*
	 * Fixup all available PCIe nodes by setting the device_type property
	 */
	fdt_pcie_setup(blob);
}
#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
4f14ed62	1	/*
cb5d88b9	2	* (C) Copyright 2007-2008
4f14ed62 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
4f14ed62 SR	24	#include <common.h>
	25	#include <watchdog.h>
	26	#include <command.h>
	27	#include <asm/cache.h>
	28	#include <ppc4xx.h>
	29
cb5d88b9	30	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
4f14ed62 SR	31	#include <libfdt.h>
4f14ed62 SR	32	#include <libfdt_env.h>
13628884	33	#include <fdt_support.h>
24bfedbd	34	#include <asm/4xx_pcie.h>
4f14ed62	35
f10493c6 SR	36	DECLARE_GLOBAL_DATA_PTR;
f10493c6 SR	37
cb5d88b9 SR	38	void __ft_board_setup(void blob, bd_t bd)
cb5d88b9 SR	39	{
cb5d88b9	40	int rc;
43cbce69 SR	41	int i;
	42	u32 bxcr;
	43	u32 ranges[EBC_NUM_BANKS * 4];
	44	u32 *p = ranges;
76706cb8	45	char ebc_path[] = "/plb/opb/ebc";
cb5d88b9 SR	46
	47	ft_cpu_setup(blob, bd);
	48
43cbce69 SR	49	/*
	50	* Read 4xx EBC bus bridge registers to get mappings of the
	51	* peripheral banks into the OPB/PLB address space
	52	*/
	53	for (i = 0; i < EBC_NUM_BANKS; i++) {
d1c3b275 SR	54	mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
d1c3b275 SR	55	bxcr = mfdcr(EBC0_CFGDATA);
43cbce69 SR	56
	57	if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
	58	*p++ = i;
	59	*p++ = 0;
	60	*p++ = bxcr & EBC_BXCR_BAS_MASK;
	61	*p++ = EBC_BXCR_BANK_SIZE(bxcr);
92b8964b SR	62
	63	#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
	64	/* Try to update reg property in nor flash node too */
	65	fdt_fixup_nor_flash_size(blob, i,
	66	EBC_BXCR_BANK_SIZE(bxcr));
	67	#endif
43cbce69	68	}
e321801b	69	}
43cbce69 SR	70
43cbce69 SR	71	/* Some 405 PPC's have EBC as direct PLB child in the dts */
92b8964b	72	if (fdt_path_offset(blob, ebc_path) < 0)
43cbce69 SR	73	strcpy(ebc_path, "/plb/ebc");
	74	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
	75	(p - ranges) * sizeof(u32), 1);
	76	if (rc) {
	77	printf("Unable to update property EBC mappings, err=%s\n",
cb5d88b9	78	fdt_strerror(rc));
43cbce69	79	}
cb5d88b9 SR	80	}
	81	void ft_board_setup(void blob, bd_t bd) __attribute__((weak, alias("__ft_board_setup")));
	82
24bfedbd SR	83	/*
	84	* Fixup all PCIe nodes by setting the device_type property
	85	* to "pci-endpoint" instead is "pci" for endpoint ports.
	86	* This property will get checked later by the Linux driver
	87	* to properly configure the PCIe port in Linux (again).
	88	*/
	89	void fdt_pcie_setup(void *blob)
	90	{
	91	const char *compat = "ibm,plb-pciex";
	92	const char *prop = "device_type";
	93	const char *prop_val = "pci-endpoint";
	94	const u32 *port;
	95	int no;
	96	int rc;
	97
	98	/* Search first PCIe node */
	99	no = fdt_node_offset_by_compatible(blob, -1, compat);
	100	while (no != -FDT_ERR_NOTFOUND) {
	101	port = fdt_getprop(blob, no, "port", NULL);
	102	if (port == NULL) {
	103	printf("WARNING: could not find port property\n");
	104	} else {
	105	if (is_end_point(*port)) {
	106	rc = fdt_setprop(blob, no, prop, prop_val,
	107	strlen(prop_val) + 1);
	108	if (rc < 0)
	109	printf("WARNING: could not set %s for %s: %s.\n",
	110	prop, compat, fdt_strerror(rc));
	111	}
	112	}
	113
	114	/* Jump to next PCIe node */
	115	no = fdt_node_offset_by_compatible(blob, no, compat);
	116	}
	117	}
	118
4f14ed62 SR	119	void ft_cpu_setup(void blob, bd_t bd)
4f14ed62 SR	120	{
4f14ed62	121	sys_info_t sys_info;
b129eff5	122	int off, ndepth = 0;
4f14ed62	123
13628884	124	get_sys_info(&sys_info);
4f14ed62	125
328a3403 SR	126	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
	127	bd->bi_intfreq, 1);
	128	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
	129	bd->bi_intfreq, 1);
13628884 SR	130	do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
13628884 SR	131	do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
eea5a743 MB	132
	133	if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
	134	do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
	135	sys_info.freqEBC, 1);
	136	else
	137	do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
	138	sys_info.freqEBC, 1);
	139
13628884	140	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
4f14ed62 SR	141
4f14ed62 SR	142	/*
b129eff5 MF	143	* Fixup all UART clocks for CPU internal UARTs
	144	* (only these UARTs are definitely clocked by gd->uart_clk)
	145	*
	146	* These UARTs are direct childs of /plb/opb. This code
	147	* does not touch any UARTs that are connected to the ebc.
4f14ed62	148	*/
b129eff5 MF	149	off = fdt_path_offset(blob, "/plb/opb");
	150	while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
	151	/*
	152	* process all sub nodes and stop when we are back
	153	* at the starting depth
	154	*/
	155	if (ndepth <= 0)
	156	break;
	157
	158	/* only update direct childs */
	159	if ((ndepth == 1) &&
	160	(fdt_node_check_compatible(blob, off, "ns16550") == 0))
	161	fdt_setprop(blob, off,
	162	"clock-frequency",
	163	(void*)&(gd->uart_clk), 4);
	164	}
4f14ed62 SR	165
4f14ed62 SR	166	/*
871e6ce1 SR	167	* Fixup all ethernet nodes
871e6ce1 SR	168	* Note: aliases in the dts are required for this
4f14ed62	169	*/
ba37aa03	170	fdt_fixup_ethernet(blob);
24bfedbd SR	171
	172	/*
	173	* Fixup all available PCIe nodes by setting the device_type property
	174	*/
	175	fdt_pcie_setup(blob);
4f14ed62	176	}
cb5d88b9	177	#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */