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Commit | Line | Data |
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c157d8e2 | 1 | /* |
7770ce47 | 2 | * URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP. |
c157d8e2 SR |
3 | * |
4 | * (C) Copyright 2003-2004 | |
792a09eb | 5 | * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> |
c157d8e2 SR |
6 | * |
7 | * (C) Copyright 2004 | |
8 | * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com> | |
9 | * | |
10 | * Note: Much of this code has been derived from Linux 2.4 | |
11 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
12 | * (C) Copyright 2000-2002 David Brownell | |
13 | * | |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
c157d8e2 SR |
15 | */ |
16 | /* | |
17 | * IMPORTANT NOTES | |
18 | * 1 - this driver is intended for use with USB Mass Storage Devices | |
19 | * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! | |
20 | */ | |
21 | ||
22 | #include <common.h> | |
23 | ||
24 | #ifdef CONFIG_USB_OHCI | |
25 | ||
26 | #include <malloc.h> | |
27 | #include <usb.h> | |
28 | #include "usb_ohci.h" | |
7770ce47 | 29 | |
c157d8e2 SR |
30 | #define OHCI_USE_NPS /* force NoPowerSwitching mode */ |
31 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ | |
32 | #undef DEBUG | |
33 | #undef SHOW_INFO | |
34 | #undef OHCI_FILL_TRACE | |
35 | ||
36 | /* For initializing controller (mask in an HCFS mode too) */ | |
37 | #define OHCI_CONTROL_INIT \ | |
38 | (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE | |
39 | ||
d00ce090 WD |
40 | #define readl(a) (*((volatile u32 *)(a))) |
41 | #define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) | |
c157d8e2 | 42 | |
c157d8e2 SR |
43 | #ifdef DEBUG |
44 | #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) | |
45 | #else | |
46 | #define dbg(format, arg...) do {} while(0) | |
7770ce47 | 47 | #endif /* DEBUG */ |
c157d8e2 SR |
48 | #define err(format, arg...) printf("ERROR: " format "\n", ## arg) |
49 | #ifdef SHOW_INFO | |
50 | #define info(format, arg...) printf("INFO: " format "\n", ## arg) | |
51 | #else | |
52 | #define info(format, arg...) do {} while(0) | |
53 | #endif | |
54 | ||
55 | #define m16_swap(x) swap_16(x) | |
56 | #define m32_swap(x) swap_32(x) | |
57 | ||
e01bd218 | 58 | #if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX) |
c157d8e2 SR |
59 | #define ohci_cpu_to_le16(x) (x) |
60 | #define ohci_cpu_to_le32(x) (x) | |
61 | #else | |
62 | #define ohci_cpu_to_le16(x) swap_16(x) | |
63 | #define ohci_cpu_to_le32(x) swap_32(x) | |
64 | #endif | |
65 | ||
66 | /* global ohci_t */ | |
67 | static ohci_t gohci; | |
68 | /* this must be aligned to a 256 byte boundary */ | |
69 | struct ohci_hcca ghcca[1]; | |
70 | /* a pointer to the aligned storage */ | |
71 | struct ohci_hcca *phcca; | |
72 | /* this allocates EDs for all possible endpoints */ | |
73 | struct ohci_device ohci_dev; | |
74 | /* urb_priv */ | |
75 | urb_priv_t urb_priv; | |
76 | /* RHSC flag */ | |
77 | int got_rhsc; | |
78 | /* device which was disconnected */ | |
79 | struct usb_device *devgone; | |
7770ce47 SR |
80 | /* flag guarding URB transation */ |
81 | int urb_finished = 0; | |
c157d8e2 SR |
82 | |
83 | /*-------------------------------------------------------------------------*/ | |
84 | ||
85 | /* AMD-756 (D2 rev) reports corrupt register contents in some cases. | |
86 | * The erratum (#4) description is incorrect. AMD's workaround waits | |
87 | * till some bits (mostly reserved) are clear; ok for all revs. | |
88 | */ | |
89 | #define OHCI_QUIRK_AMD756 0xabcd | |
90 | #define read_roothub(hc, register, mask) ({ \ | |
91 | u32 temp = readl (&hc->regs->roothub.register); \ | |
92 | if (hc->flags & OHCI_QUIRK_AMD756) \ | |
93 | while (temp & mask) \ | |
94 | temp = readl (&hc->regs->roothub.register); \ | |
95 | temp; }) | |
96 | ||
7770ce47 SR |
97 | static u32 roothub_a (struct ohci *hc) |
98 | { return read_roothub (hc, a, 0xfc0fe000); } | |
99 | static inline u32 roothub_b (struct ohci *hc) | |
100 | { return readl (&hc->regs->roothub.b); } | |
101 | static inline u32 roothub_status (struct ohci *hc) | |
102 | { return readl (&hc->regs->roothub.status); } | |
103 | static u32 roothub_portstatus (struct ohci *hc, int i) | |
104 | { return read_roothub (hc, portstatus [i], 0xffe0fce0); } | |
105 | ||
c157d8e2 SR |
106 | |
107 | /* forward declaration */ | |
7770ce47 | 108 | static int hc_interrupt (void); |
c157d8e2 | 109 | static void |
7770ce47 SR |
110 | td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, |
111 | int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); | |
c157d8e2 SR |
112 | |
113 | /*-------------------------------------------------------------------------* | |
114 | * URB support functions | |
115 | *-------------------------------------------------------------------------*/ | |
116 | ||
117 | /* free HCD-private data associated with this URB */ | |
118 | ||
7770ce47 | 119 | static void urb_free_priv (urb_priv_t * urb) |
c157d8e2 | 120 | { |
7770ce47 SR |
121 | int i; |
122 | int last; | |
123 | struct td * td; | |
c157d8e2 SR |
124 | |
125 | last = urb->length - 1; | |
126 | if (last >= 0) { | |
127 | for (i = 0; i <= last; i++) { | |
128 | td = urb->td[i]; | |
129 | if (td) { | |
130 | td->usb_dev = NULL; | |
131 | urb->td[i] = NULL; | |
132 | } | |
133 | } | |
134 | } | |
135 | } | |
136 | ||
137 | /*-------------------------------------------------------------------------*/ | |
138 | ||
139 | #ifdef DEBUG | |
7770ce47 | 140 | static int sohci_get_current_frame_number (struct usb_device * dev); |
c157d8e2 SR |
141 | |
142 | /* debug| print the main components of an URB | |
143 | * small: 0) header + data packets 1) just header */ | |
144 | ||
7770ce47 SR |
145 | static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, |
146 | int transfer_len, struct devrequest * setup, char * str, int small) | |
c157d8e2 | 147 | { |
7770ce47 | 148 | urb_priv_t * purb = &urb_priv; |
c157d8e2 SR |
149 | |
150 | dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", | |
7770ce47 SR |
151 | str, |
152 | sohci_get_current_frame_number (dev), | |
153 | usb_pipedevice (pipe), | |
154 | usb_pipeendpoint (pipe), | |
155 | usb_pipeout (pipe)? 'O': 'I', | |
156 | usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): | |
157 | (usb_pipecontrol (pipe)? "CTRL": "BULK"), | |
158 | purb->actual_length, | |
159 | transfer_len, dev->status); | |
c157d8e2 SR |
160 | #ifdef OHCI_VERBOSE_DEBUG |
161 | if (!small) { | |
162 | int i, len; | |
163 | ||
7770ce47 SR |
164 | if (usb_pipecontrol (pipe)) { |
165 | printf (__FILE__ ": cmd(8):"); | |
166 | for (i = 0; i < 8 ; i++) | |
167 | printf (" %02x", ((__u8 *) setup) [i]); | |
168 | printf ("\n"); | |
c157d8e2 SR |
169 | } |
170 | if (transfer_len > 0 && buffer) { | |
7770ce47 SR |
171 | printf (__FILE__ ": data(%d/%d):", |
172 | purb->actual_length, | |
173 | transfer_len); | |
174 | len = usb_pipeout (pipe)? | |
175 | transfer_len: purb->actual_length; | |
c157d8e2 | 176 | for (i = 0; i < 16 && i < len; i++) |
7770ce47 SR |
177 | printf (" %02x", ((__u8 *) buffer) [i]); |
178 | printf ("%s\n", i < len? "...": ""); | |
c157d8e2 SR |
179 | } |
180 | } | |
181 | #endif | |
182 | } | |
183 | ||
184 | /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ | |
7770ce47 | 185 | void ep_print_int_eds (ohci_t *ohci, char * str) { |
c157d8e2 | 186 | int i, j; |
7770ce47 SR |
187 | __u32 * ed_p; |
188 | for (i= 0; i < 32; i++) { | |
c157d8e2 | 189 | j = 5; |
7770ce47 | 190 | ed_p = &(ohci->hcca->int_table [i]); |
c157d8e2 | 191 | if (*ed_p == 0) |
7770ce47 SR |
192 | continue; |
193 | printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); | |
c157d8e2 | 194 | while (*ed_p != 0 && j--) { |
7770ce47 SR |
195 | ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); |
196 | printf (" ed: %4x;", ed->hwINFO); | |
c157d8e2 SR |
197 | ed_p = &ed->hwNextED; |
198 | } | |
7770ce47 | 199 | printf ("\n"); |
c157d8e2 SR |
200 | } |
201 | } | |
202 | ||
7770ce47 | 203 | static void ohci_dump_intr_mask (char *label, __u32 mask) |
c157d8e2 | 204 | { |
7770ce47 SR |
205 | dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", |
206 | label, | |
207 | mask, | |
208 | (mask & OHCI_INTR_MIE) ? " MIE" : "", | |
209 | (mask & OHCI_INTR_OC) ? " OC" : "", | |
210 | (mask & OHCI_INTR_RHSC) ? " RHSC" : "", | |
211 | (mask & OHCI_INTR_FNO) ? " FNO" : "", | |
212 | (mask & OHCI_INTR_UE) ? " UE" : "", | |
213 | (mask & OHCI_INTR_RD) ? " RD" : "", | |
214 | (mask & OHCI_INTR_SF) ? " SF" : "", | |
215 | (mask & OHCI_INTR_WDH) ? " WDH" : "", | |
216 | (mask & OHCI_INTR_SO) ? " SO" : "" | |
217 | ); | |
c157d8e2 SR |
218 | } |
219 | ||
7770ce47 | 220 | static void maybe_print_eds (char *label, __u32 value) |
c157d8e2 | 221 | { |
7770ce47 | 222 | ed_t *edp = (ed_t *)value; |
c157d8e2 SR |
223 | |
224 | if (value) { | |
7770ce47 SR |
225 | dbg ("%s %08x", label, value); |
226 | dbg ("%08x", edp->hwINFO); | |
227 | dbg ("%08x", edp->hwTailP); | |
228 | dbg ("%08x", edp->hwHeadP); | |
229 | dbg ("%08x", edp->hwNextED); | |
c157d8e2 SR |
230 | } |
231 | } | |
232 | ||
7770ce47 | 233 | static char * hcfs2string (int state) |
c157d8e2 SR |
234 | { |
235 | switch (state) { | |
7770ce47 SR |
236 | case OHCI_USB_RESET: return "reset"; |
237 | case OHCI_USB_RESUME: return "resume"; | |
238 | case OHCI_USB_OPER: return "operational"; | |
239 | case OHCI_USB_SUSPEND: return "suspend"; | |
c157d8e2 SR |
240 | } |
241 | return "?"; | |
242 | } | |
243 | ||
244 | /* dump control and status registers */ | |
7770ce47 | 245 | static void ohci_dump_status (ohci_t *controller) |
c157d8e2 | 246 | { |
7770ce47 SR |
247 | struct ohci_regs *regs = controller->regs; |
248 | __u32 temp; | |
c157d8e2 | 249 | |
7770ce47 | 250 | temp = readl (®s->revision) & 0xff; |
c157d8e2 | 251 | if (temp != 0x10) |
7770ce47 SR |
252 | dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); |
253 | ||
254 | temp = readl (®s->control); | |
255 | dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, | |
256 | (temp & OHCI_CTRL_RWE) ? " RWE" : "", | |
257 | (temp & OHCI_CTRL_RWC) ? " RWC" : "", | |
258 | (temp & OHCI_CTRL_IR) ? " IR" : "", | |
259 | hcfs2string (temp & OHCI_CTRL_HCFS), | |
260 | (temp & OHCI_CTRL_BLE) ? " BLE" : "", | |
261 | (temp & OHCI_CTRL_CLE) ? " CLE" : "", | |
262 | (temp & OHCI_CTRL_IE) ? " IE" : "", | |
263 | (temp & OHCI_CTRL_PLE) ? " PLE" : "", | |
264 | temp & OHCI_CTRL_CBSR | |
265 | ); | |
266 | ||
267 | temp = readl (®s->cmdstatus); | |
268 | dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, | |
269 | (temp & OHCI_SOC) >> 16, | |
270 | (temp & OHCI_OCR) ? " OCR" : "", | |
271 | (temp & OHCI_BLF) ? " BLF" : "", | |
272 | (temp & OHCI_CLF) ? " CLF" : "", | |
273 | (temp & OHCI_HCR) ? " HCR" : "" | |
274 | ); | |
275 | ||
276 | ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); | |
277 | ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); | |
278 | ||
279 | maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); | |
280 | ||
281 | maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); | |
282 | maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); | |
283 | ||
284 | maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); | |
285 | maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); | |
286 | ||
287 | maybe_print_eds ("donehead", readl (®s->donehead)); | |
c157d8e2 SR |
288 | } |
289 | ||
7770ce47 | 290 | static void ohci_dump_roothub (ohci_t *controller, int verbose) |
c157d8e2 | 291 | { |
7770ce47 | 292 | __u32 temp, ndp, i; |
c157d8e2 | 293 | |
7770ce47 | 294 | temp = roothub_a (controller); |
c157d8e2 SR |
295 | ndp = (temp & RH_A_NDP); |
296 | ||
297 | if (verbose) { | |
7770ce47 SR |
298 | dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, |
299 | ((temp & RH_A_POTPGT) >> 24) & 0xff, | |
300 | (temp & RH_A_NOCP) ? " NOCP" : "", | |
301 | (temp & RH_A_OCPM) ? " OCPM" : "", | |
302 | (temp & RH_A_DT) ? " DT" : "", | |
303 | (temp & RH_A_NPS) ? " NPS" : "", | |
304 | (temp & RH_A_PSM) ? " PSM" : "", | |
305 | ndp | |
306 | ); | |
307 | temp = roothub_b (controller); | |
308 | dbg ("roothub.b: %08x PPCM=%04x DR=%04x", | |
309 | temp, | |
310 | (temp & RH_B_PPCM) >> 16, | |
311 | (temp & RH_B_DR) | |
312 | ); | |
313 | temp = roothub_status (controller); | |
314 | dbg ("roothub.status: %08x%s%s%s%s%s%s", | |
315 | temp, | |
316 | (temp & RH_HS_CRWE) ? " CRWE" : "", | |
317 | (temp & RH_HS_OCIC) ? " OCIC" : "", | |
318 | (temp & RH_HS_LPSC) ? " LPSC" : "", | |
319 | (temp & RH_HS_DRWE) ? " DRWE" : "", | |
320 | (temp & RH_HS_OCI) ? " OCI" : "", | |
321 | (temp & RH_HS_LPS) ? " LPS" : "" | |
322 | ); | |
c157d8e2 SR |
323 | } |
324 | ||
325 | for (i = 0; i < ndp; i++) { | |
7770ce47 SR |
326 | temp = roothub_portstatus (controller, i); |
327 | dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", | |
328 | i, | |
329 | temp, | |
330 | (temp & RH_PS_PRSC) ? " PRSC" : "", | |
331 | (temp & RH_PS_OCIC) ? " OCIC" : "", | |
332 | (temp & RH_PS_PSSC) ? " PSSC" : "", | |
333 | (temp & RH_PS_PESC) ? " PESC" : "", | |
334 | (temp & RH_PS_CSC) ? " CSC" : "", | |
335 | ||
336 | (temp & RH_PS_LSDA) ? " LSDA" : "", | |
337 | (temp & RH_PS_PPS) ? " PPS" : "", | |
338 | (temp & RH_PS_PRS) ? " PRS" : "", | |
339 | (temp & RH_PS_POCI) ? " POCI" : "", | |
340 | (temp & RH_PS_PSS) ? " PSS" : "", | |
341 | ||
342 | (temp & RH_PS_PES) ? " PES" : "", | |
343 | (temp & RH_PS_CCS) ? " CCS" : "" | |
344 | ); | |
c157d8e2 SR |
345 | } |
346 | } | |
347 | ||
7770ce47 | 348 | static void ohci_dump (ohci_t *controller, int verbose) |
c157d8e2 | 349 | { |
7770ce47 | 350 | dbg ("OHCI controller usb-%s state", controller->slot_name); |
c157d8e2 SR |
351 | |
352 | /* dumps some of the state we know about */ | |
7770ce47 | 353 | ohci_dump_status (controller); |
c157d8e2 | 354 | if (verbose) |
7770ce47 SR |
355 | ep_print_int_eds (controller, "hcca"); |
356 | dbg ("hcca frame #%04x", controller->hcca->frame_no); | |
357 | ohci_dump_roothub (controller, 1); | |
c157d8e2 SR |
358 | } |
359 | ||
7770ce47 SR |
360 | |
361 | #endif /* DEBUG */ | |
c157d8e2 SR |
362 | |
363 | /*-------------------------------------------------------------------------* | |
364 | * Interface functions (URB) | |
365 | *-------------------------------------------------------------------------*/ | |
366 | ||
367 | /* get a transfer request */ | |
368 | ||
369 | int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 370 | int transfer_len, struct devrequest *setup, int interval) |
c157d8e2 SR |
371 | { |
372 | ohci_t *ohci; | |
7770ce47 | 373 | ed_t * ed; |
c157d8e2 SR |
374 | urb_priv_t *purb_priv; |
375 | int i, size = 0; | |
376 | ||
377 | ohci = &gohci; | |
378 | ||
379 | /* when controller's hung, permit only roothub cleanup attempts | |
380 | * such as powering down ports */ | |
381 | if (ohci->disabled) { | |
382 | err("sohci_submit_job: EPIPE"); | |
383 | return -1; | |
384 | } | |
385 | ||
7770ce47 SR |
386 | /* if we have an unfinished URB from previous transaction let's |
387 | * fail and scream as quickly as possible so as not to corrupt | |
388 | * further communication */ | |
389 | if (!urb_finished) { | |
390 | err("sohci_submit_job: URB NOT FINISHED"); | |
391 | return -1; | |
392 | } | |
393 | /* we're about to begin a new transaction here so mark the URB unfinished */ | |
394 | urb_finished = 0; | |
395 | ||
c157d8e2 | 396 | /* every endpoint has a ed, locate and fill it */ |
7770ce47 | 397 | if (!(ed = ep_add_ed (dev, pipe))) { |
c157d8e2 SR |
398 | err("sohci_submit_job: ENOMEM"); |
399 | return -1; | |
400 | } | |
401 | ||
402 | /* for the private part of the URB we need the number of TDs (size) */ | |
7770ce47 SR |
403 | switch (usb_pipetype (pipe)) { |
404 | case PIPE_BULK: /* one TD for every 4096 Byte */ | |
405 | size = (transfer_len - 1) / 4096 + 1; | |
406 | break; | |
407 | case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ | |
408 | size = (transfer_len == 0)? 2: | |
409 | (transfer_len - 1) / 4096 + 3; | |
410 | break; | |
c157d8e2 SR |
411 | } |
412 | ||
413 | if (size >= (N_URB_TD - 1)) { | |
414 | err("need %d TDs, only have %d", size, N_URB_TD); | |
415 | return -1; | |
416 | } | |
417 | purb_priv = &urb_priv; | |
418 | purb_priv->pipe = pipe; | |
419 | ||
420 | /* fill the private part of the URB */ | |
421 | purb_priv->length = size; | |
422 | purb_priv->ed = ed; | |
423 | purb_priv->actual_length = 0; | |
424 | ||
425 | /* allocate the TDs */ | |
426 | /* note that td[0] was allocated in ep_add_ed */ | |
427 | for (i = 0; i < size; i++) { | |
7770ce47 | 428 | purb_priv->td[i] = td_alloc (dev); |
c157d8e2 SR |
429 | if (!purb_priv->td[i]) { |
430 | purb_priv->length = i; | |
7770ce47 | 431 | urb_free_priv (purb_priv); |
c157d8e2 SR |
432 | err("sohci_submit_job: ENOMEM"); |
433 | return -1; | |
434 | } | |
435 | } | |
436 | ||
437 | if (ed->state == ED_NEW || (ed->state & ED_DEL)) { | |
7770ce47 | 438 | urb_free_priv (purb_priv); |
c157d8e2 SR |
439 | err("sohci_submit_job: EINVAL"); |
440 | return -1; | |
441 | } | |
442 | ||
443 | /* link the ed into a chain if is not already */ | |
444 | if (ed->state != ED_OPER) | |
7770ce47 | 445 | ep_link (ohci, ed); |
c157d8e2 SR |
446 | |
447 | /* fill the TDs and link it to the ed */ | |
7770ce47 | 448 | td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); |
c157d8e2 SR |
449 | |
450 | return 0; | |
451 | } | |
452 | ||
453 | /*-------------------------------------------------------------------------*/ | |
454 | ||
455 | #ifdef DEBUG | |
456 | /* tell us the current USB frame number */ | |
457 | ||
7770ce47 | 458 | static int sohci_get_current_frame_number (struct usb_device *usb_dev) |
c157d8e2 SR |
459 | { |
460 | ohci_t *ohci = &gohci; | |
461 | ||
7770ce47 | 462 | return ohci_cpu_to_le16 (ohci->hcca->frame_no); |
c157d8e2 SR |
463 | } |
464 | #endif | |
465 | ||
466 | /*-------------------------------------------------------------------------* | |
467 | * ED handling functions | |
468 | *-------------------------------------------------------------------------*/ | |
469 | ||
470 | /* link an ed into one of the HC chains */ | |
471 | ||
7770ce47 | 472 | static int ep_link (ohci_t *ohci, ed_t *edi) |
c157d8e2 SR |
473 | { |
474 | volatile ed_t *ed = edi; | |
475 | ||
476 | ed->state = ED_OPER; | |
477 | ||
478 | switch (ed->type) { | |
479 | case PIPE_CONTROL: | |
480 | ed->hwNextED = 0; | |
481 | if (ohci->ed_controltail == NULL) { | |
7770ce47 | 482 | writel (ed, &ohci->regs->ed_controlhead); |
c157d8e2 | 483 | } else { |
7770ce47 | 484 | ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); |
c157d8e2 SR |
485 | } |
486 | ed->ed_prev = ohci->ed_controltail; | |
487 | if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && | |
7770ce47 | 488 | !ohci->ed_rm_list[1] && !ohci->sleeping) { |
c157d8e2 | 489 | ohci->hc_control |= OHCI_CTRL_CLE; |
7770ce47 | 490 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 SR |
491 | } |
492 | ohci->ed_controltail = edi; | |
493 | break; | |
494 | ||
495 | case PIPE_BULK: | |
496 | ed->hwNextED = 0; | |
497 | if (ohci->ed_bulktail == NULL) { | |
7770ce47 | 498 | writel (ed, &ohci->regs->ed_bulkhead); |
c157d8e2 | 499 | } else { |
7770ce47 | 500 | ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); |
c157d8e2 SR |
501 | } |
502 | ed->ed_prev = ohci->ed_bulktail; | |
503 | if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && | |
7770ce47 | 504 | !ohci->ed_rm_list[1] && !ohci->sleeping) { |
c157d8e2 | 505 | ohci->hc_control |= OHCI_CTRL_BLE; |
7770ce47 | 506 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 SR |
507 | } |
508 | ohci->ed_bulktail = edi; | |
509 | break; | |
510 | } | |
511 | return 0; | |
512 | } | |
513 | ||
514 | /*-------------------------------------------------------------------------*/ | |
515 | ||
516 | /* unlink an ed from one of the HC chains. | |
517 | * just the link to the ed is unlinked. | |
518 | * the link from the ed still points to another operational ed or 0 | |
519 | * so the HC can eventually finish the processing of the unlinked ed */ | |
520 | ||
7770ce47 | 521 | static int ep_unlink (ohci_t *ohci, ed_t *edi) |
c157d8e2 SR |
522 | { |
523 | volatile ed_t *ed = edi; | |
524 | ||
7770ce47 | 525 | ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); |
c157d8e2 SR |
526 | |
527 | switch (ed->type) { | |
528 | case PIPE_CONTROL: | |
529 | if (ed->ed_prev == NULL) { | |
530 | if (!ed->hwNextED) { | |
531 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
7770ce47 | 532 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 | 533 | } |
7770ce47 | 534 | writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); |
c157d8e2 SR |
535 | } else { |
536 | ed->ed_prev->hwNextED = ed->hwNextED; | |
537 | } | |
538 | if (ohci->ed_controltail == ed) { | |
539 | ohci->ed_controltail = ed->ed_prev; | |
540 | } else { | |
7770ce47 | 541 | ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; |
c157d8e2 SR |
542 | } |
543 | break; | |
544 | ||
545 | case PIPE_BULK: | |
546 | if (ed->ed_prev == NULL) { | |
547 | if (!ed->hwNextED) { | |
548 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
7770ce47 | 549 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 | 550 | } |
7770ce47 | 551 | writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); |
c157d8e2 SR |
552 | } else { |
553 | ed->ed_prev->hwNextED = ed->hwNextED; | |
554 | } | |
555 | if (ohci->ed_bulktail == ed) { | |
556 | ohci->ed_bulktail = ed->ed_prev; | |
557 | } else { | |
7770ce47 | 558 | ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; |
c157d8e2 SR |
559 | } |
560 | break; | |
561 | } | |
562 | ed->state = ED_UNLINK; | |
563 | return 0; | |
564 | } | |
565 | ||
7770ce47 | 566 | |
c157d8e2 SR |
567 | /*-------------------------------------------------------------------------*/ |
568 | ||
569 | /* add/reinit an endpoint; this should be done once at the usb_set_configuration command, | |
570 | * but the USB stack is a little bit stateless so we do it at every transaction | |
571 | * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK | |
572 | * in all other cases the state is left unchanged | |
573 | * the ed info fields are setted anyway even though most of them should not change */ | |
574 | ||
7770ce47 | 575 | static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) |
c157d8e2 SR |
576 | { |
577 | td_t *td; | |
578 | ed_t *ed_ret; | |
579 | volatile ed_t *ed; | |
580 | ||
7770ce47 SR |
581 | ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | |
582 | (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; | |
c157d8e2 SR |
583 | |
584 | if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { | |
585 | err("ep_add_ed: pending delete"); | |
586 | /* pending delete request */ | |
587 | return NULL; | |
588 | } | |
589 | ||
590 | if (ed->state == ED_NEW) { | |
7770ce47 | 591 | ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ |
c157d8e2 | 592 | /* dummy td; end of td list for ed */ |
7770ce47 SR |
593 | td = td_alloc (usb_dev); |
594 | ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); | |
c157d8e2 SR |
595 | ed->hwHeadP = ed->hwTailP; |
596 | ed->state = ED_UNLINK; | |
7770ce47 | 597 | ed->type = usb_pipetype (pipe); |
c157d8e2 SR |
598 | ohci_dev.ed_cnt++; |
599 | } | |
600 | ||
7770ce47 SR |
601 | ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) |
602 | | usb_pipeendpoint (pipe) << 7 | |
603 | | (usb_pipeisoc (pipe)? 0x8000: 0) | |
604 | | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) | |
c60795f4 | 605 | | (usb_dev->speed == USB_SPEED_LOW) << 13 |
7770ce47 | 606 | | usb_maxpacket (usb_dev, pipe) << 16); |
c157d8e2 SR |
607 | |
608 | return ed_ret; | |
609 | } | |
610 | ||
611 | /*-------------------------------------------------------------------------* | |
612 | * TD handling functions | |
613 | *-------------------------------------------------------------------------*/ | |
614 | ||
615 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
616 | ||
7770ce47 SR |
617 | static void td_fill (ohci_t *ohci, unsigned int info, |
618 | void *data, int len, | |
619 | struct usb_device *dev, int index, urb_priv_t *urb_priv) | |
c157d8e2 | 620 | { |
7770ce47 | 621 | volatile td_t *td, *td_pt; |
c157d8e2 SR |
622 | #ifdef OHCI_FILL_TRACE |
623 | int i; | |
624 | #endif | |
625 | ||
626 | if (index > urb_priv->length) { | |
627 | err("index > length"); | |
628 | return; | |
629 | } | |
630 | /* use this td as the next dummy */ | |
7770ce47 | 631 | td_pt = urb_priv->td [index]; |
c157d8e2 SR |
632 | td_pt->hwNextTD = 0; |
633 | ||
634 | /* fill the old dummy TD */ | |
7770ce47 | 635 | td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); |
c157d8e2 SR |
636 | |
637 | td->ed = urb_priv->ed; | |
638 | td->next_dl_td = NULL; | |
639 | td->index = index; | |
7770ce47 | 640 | td->data = (__u32)data; |
c157d8e2 | 641 | #ifdef OHCI_FILL_TRACE |
9dbc3667 | 642 | if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { |
c157d8e2 | 643 | for (i = 0; i < len; i++) |
7770ce47 | 644 | printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); |
c157d8e2 SR |
645 | printf("\n"); |
646 | } | |
647 | #endif | |
648 | if (!len) | |
649 | data = 0; | |
650 | ||
7770ce47 SR |
651 | td->hwINFO = ohci_cpu_to_le32 (info); |
652 | td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); | |
c157d8e2 | 653 | if (data) |
7770ce47 | 654 | td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); |
c157d8e2 SR |
655 | else |
656 | td->hwBE = 0; | |
7770ce47 | 657 | td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); |
c157d8e2 SR |
658 | |
659 | /* append to queue */ | |
660 | td->ed->hwTailP = td->hwNextTD; | |
661 | } | |
662 | ||
663 | /*-------------------------------------------------------------------------*/ | |
664 | ||
665 | /* prepare all TDs of a transfer */ | |
7770ce47 SR |
666 | static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, |
667 | int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) | |
c157d8e2 SR |
668 | { |
669 | ohci_t *ohci = &gohci; | |
670 | int data_len = transfer_len; | |
671 | void *data; | |
672 | int cnt = 0; | |
673 | __u32 info = 0; | |
674 | unsigned int toggle = 0; | |
675 | ||
676 | /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ | |
7770ce47 | 677 | if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { |
c157d8e2 SR |
678 | toggle = TD_T_TOGGLE; |
679 | } else { | |
680 | toggle = TD_T_DATA0; | |
7770ce47 | 681 | usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); |
c157d8e2 SR |
682 | } |
683 | urb->td_cnt = 0; | |
684 | if (data_len) | |
685 | data = buffer; | |
686 | else | |
687 | data = 0; | |
688 | ||
7770ce47 | 689 | switch (usb_pipetype (pipe)) { |
c157d8e2 | 690 | case PIPE_BULK: |
7770ce47 SR |
691 | info = usb_pipeout (pipe)? |
692 | TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; | |
693 | while(data_len > 4096) { | |
694 | td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); | |
695 | data += 4096; data_len -= 4096; cnt++; | |
c157d8e2 | 696 | } |
7770ce47 SR |
697 | info = usb_pipeout (pipe)? |
698 | TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; | |
699 | td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); | |
c157d8e2 SR |
700 | cnt++; |
701 | ||
702 | if (!ohci->sleeping) | |
7770ce47 | 703 | writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ |
c157d8e2 SR |
704 | break; |
705 | ||
706 | case PIPE_CONTROL: | |
707 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; | |
7770ce47 | 708 | td_fill (ohci, info, setup, 8, dev, cnt++, urb); |
c157d8e2 | 709 | if (data_len > 0) { |
7770ce47 SR |
710 | info = usb_pipeout (pipe)? |
711 | TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; | |
c157d8e2 | 712 | /* NOTE: mishandles transfers >8K, some >4K */ |
7770ce47 | 713 | td_fill (ohci, info, data, data_len, dev, cnt++, urb); |
c157d8e2 | 714 | } |
7770ce47 SR |
715 | info = usb_pipeout (pipe)? |
716 | TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; | |
717 | td_fill (ohci, info, data, 0, dev, cnt++, urb); | |
c157d8e2 | 718 | if (!ohci->sleeping) |
7770ce47 | 719 | writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ |
c157d8e2 SR |
720 | break; |
721 | } | |
722 | if (urb->length != cnt) | |
723 | dbg("TD LENGTH %d != CNT %d", urb->length, cnt); | |
724 | } | |
725 | ||
726 | /*-------------------------------------------------------------------------* | |
727 | * Done List handling functions | |
728 | *-------------------------------------------------------------------------*/ | |
729 | ||
7770ce47 | 730 | |
c157d8e2 SR |
731 | /* calculate the transfer length and update the urb */ |
732 | ||
733 | static void dl_transfer_length(td_t * td) | |
734 | { | |
af0af524 | 735 | __u32 tdBE, tdCBP; |
c157d8e2 SR |
736 | urb_priv_t *lurb_priv = &urb_priv; |
737 | ||
7770ce47 SR |
738 | tdBE = ohci_cpu_to_le32 (td->hwBE); |
739 | tdCBP = ohci_cpu_to_le32 (td->hwCBP); | |
c157d8e2 | 740 | |
7770ce47 | 741 | |
9dbc3667 | 742 | if (!(usb_pipecontrol(lurb_priv->pipe) && |
7770ce47 | 743 | ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { |
c157d8e2 SR |
744 | if (tdBE != 0) { |
745 | if (td->hwCBP == 0) | |
746 | lurb_priv->actual_length += tdBE - td->data + 1; | |
747 | else | |
748 | lurb_priv->actual_length += tdCBP - td->data; | |
749 | } | |
750 | } | |
751 | } | |
752 | ||
753 | /*-------------------------------------------------------------------------*/ | |
754 | ||
755 | /* replies to the request have to be on a FIFO basis so | |
756 | * we reverse the reversed done-list */ | |
757 | ||
7770ce47 | 758 | static td_t * dl_reverse_done_list (ohci_t *ohci) |
c157d8e2 SR |
759 | { |
760 | __u32 td_list_hc; | |
761 | td_t *td_rev = NULL; | |
762 | td_t *td_list = NULL; | |
763 | urb_priv_t *lurb_priv = NULL; | |
764 | ||
7770ce47 | 765 | td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; |
c157d8e2 SR |
766 | ohci->hcca->done_head = 0; |
767 | ||
768 | while (td_list_hc) { | |
7770ce47 | 769 | td_list = (td_t *)td_list_hc; |
c157d8e2 | 770 | |
7770ce47 | 771 | if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { |
c157d8e2 SR |
772 | lurb_priv = &urb_priv; |
773 | dbg(" USB-error/status: %x : %p", | |
7770ce47 SR |
774 | TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); |
775 | if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { | |
776 | if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { | |
c157d8e2 | 777 | td_list->ed->hwHeadP = |
7770ce47 SR |
778 | (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | |
779 | (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); | |
780 | lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; | |
c157d8e2 | 781 | } else |
7770ce47 | 782 | td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); |
c157d8e2 SR |
783 | } |
784 | #ifdef CONFIG_MPC5200 | |
785 | td_list->hwNextTD = 0; | |
786 | #endif | |
787 | } | |
788 | ||
789 | td_list->next_dl_td = td_rev; | |
790 | td_rev = td_list; | |
7770ce47 | 791 | td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; |
c157d8e2 SR |
792 | } |
793 | return td_list; | |
794 | } | |
795 | ||
796 | /*-------------------------------------------------------------------------*/ | |
797 | ||
798 | /* td done list */ | |
7770ce47 | 799 | static int dl_done_list (ohci_t *ohci, td_t *td_list) |
c157d8e2 SR |
800 | { |
801 | td_t *td_list_next = NULL; | |
802 | ed_t *ed; | |
803 | int cc = 0; | |
7770ce47 | 804 | int stat = 0; |
c157d8e2 SR |
805 | /* urb_t *urb; */ |
806 | urb_priv_t *lurb_priv; | |
807 | __u32 tdINFO, edHeadP, edTailP; | |
808 | ||
809 | while (td_list) { | |
810 | td_list_next = td_list->next_dl_td; | |
811 | ||
812 | lurb_priv = &urb_priv; | |
7770ce47 | 813 | tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); |
c157d8e2 SR |
814 | |
815 | ed = td_list->ed; | |
816 | ||
817 | dl_transfer_length(td_list); | |
818 | ||
819 | /* error code of transfer */ | |
7770ce47 | 820 | cc = TD_CC_GET (tdINFO); |
c157d8e2 SR |
821 | if (++(lurb_priv->td_cnt) == lurb_priv->length) { |
822 | if ((ed->state & (ED_OPER | ED_UNLINK)) | |
7770ce47 | 823 | && (lurb_priv->state != URB_DEL)) { |
c157d8e2 SR |
824 | dbg("ConditionCode %#x", cc); |
825 | stat = cc_to_error[cc]; | |
7770ce47 | 826 | urb_finished = 1; |
c157d8e2 SR |
827 | } |
828 | } | |
829 | ||
830 | if (ed->state != ED_NEW) { | |
7770ce47 SR |
831 | edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; |
832 | edTailP = ohci_cpu_to_le32 (ed->hwTailP); | |
c157d8e2 SR |
833 | |
834 | /* unlink eds if they are not busy */ | |
835 | if ((edHeadP == edTailP) && (ed->state == ED_OPER)) | |
7770ce47 | 836 | ep_unlink (ohci, ed); |
c157d8e2 SR |
837 | } |
838 | ||
839 | td_list = td_list_next; | |
840 | } | |
841 | return stat; | |
842 | } | |
843 | ||
844 | /*-------------------------------------------------------------------------* | |
845 | * Virtual Root Hub | |
846 | *-------------------------------------------------------------------------*/ | |
847 | ||
eb838e7d | 848 | #include <usbroothubdes.h> |
c157d8e2 SR |
849 | |
850 | /* Hub class-specific descriptor is constructed dynamically */ | |
851 | ||
7770ce47 | 852 | |
c157d8e2 SR |
853 | /*-------------------------------------------------------------------------*/ |
854 | ||
855 | #define OK(x) len = (x); break | |
856 | #ifdef DEBUG | |
857 | #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} | |
858 | #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} | |
859 | #else | |
860 | #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) | |
861 | #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) | |
862 | #endif | |
863 | #define RD_RH_STAT roothub_status(&gohci) | |
864 | #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) | |
865 | ||
866 | /* request to virtual root hub */ | |
867 | ||
7770ce47 | 868 | int rh_check_port_status(ohci_t *controller) |
c157d8e2 SR |
869 | { |
870 | __u32 temp, ndp, i; | |
871 | int res; | |
872 | ||
873 | res = -1; | |
7770ce47 | 874 | temp = roothub_a (controller); |
c157d8e2 SR |
875 | ndp = (temp & RH_A_NDP); |
876 | for (i = 0; i < ndp; i++) { | |
7770ce47 | 877 | temp = roothub_portstatus (controller, i); |
c157d8e2 SR |
878 | /* check for a device disconnect */ |
879 | if (((temp & (RH_PS_PESC | RH_PS_CSC)) == | |
7770ce47 SR |
880 | (RH_PS_PESC | RH_PS_CSC)) && |
881 | ((temp & RH_PS_CCS) == 0)) { | |
c157d8e2 SR |
882 | res = i; |
883 | break; | |
884 | } | |
885 | } | |
886 | return res; | |
887 | } | |
888 | ||
889 | static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, | |
7770ce47 | 890 | void *buffer, int transfer_len, struct devrequest *cmd) |
c157d8e2 | 891 | { |
7770ce47 | 892 | void * data = buffer; |
c157d8e2 SR |
893 | int leni = transfer_len; |
894 | int len = 0; | |
895 | int stat = 0; | |
896 | __u32 datab[4]; | |
7770ce47 | 897 | __u8 *data_buf = (__u8 *)datab; |
c157d8e2 SR |
898 | __u16 bmRType_bReq; |
899 | __u16 wValue; | |
900 | __u16 wIndex; | |
901 | __u16 wLength; | |
902 | ||
903 | #ifdef DEBUG | |
7770ce47 SR |
904 | urb_priv.actual_length = 0; |
905 | pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); | |
c157d8e2 | 906 | #endif |
9dbc3667 | 907 | if (usb_pipeint(pipe)) { |
c157d8e2 SR |
908 | info("Root-Hub submit IRQ: NOT implemented"); |
909 | return 0; | |
910 | } | |
911 | ||
7770ce47 SR |
912 | bmRType_bReq = cmd->requesttype | (cmd->request << 8); |
913 | wValue = m16_swap (cmd->value); | |
914 | wIndex = m16_swap (cmd->index); | |
915 | wLength = m16_swap (cmd->length); | |
c157d8e2 SR |
916 | |
917 | info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", | |
7770ce47 | 918 | dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); |
c157d8e2 SR |
919 | |
920 | switch (bmRType_bReq) { | |
7770ce47 SR |
921 | /* Request Destination: |
922 | without flags: Device, | |
923 | RH_INTERFACE: interface, | |
924 | RH_ENDPOINT: endpoint, | |
925 | RH_CLASS means HUB here, | |
926 | RH_OTHER | RH_CLASS almost ever means HUB_PORT here | |
927 | */ | |
c157d8e2 SR |
928 | |
929 | case RH_GET_STATUS: | |
7770ce47 | 930 | *(__u16 *) data_buf = m16_swap (1); OK (2); |
c157d8e2 | 931 | case RH_GET_STATUS | RH_INTERFACE: |
7770ce47 | 932 | *(__u16 *) data_buf = m16_swap (0); OK (2); |
c157d8e2 | 933 | case RH_GET_STATUS | RH_ENDPOINT: |
7770ce47 | 934 | *(__u16 *) data_buf = m16_swap (0); OK (2); |
c157d8e2 | 935 | case RH_GET_STATUS | RH_CLASS: |
7770ce47 SR |
936 | *(__u32 *) data_buf = m32_swap ( |
937 | RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); | |
938 | OK (4); | |
c157d8e2 | 939 | case RH_GET_STATUS | RH_OTHER | RH_CLASS: |
7770ce47 | 940 | *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); |
c157d8e2 SR |
941 | |
942 | case RH_CLEAR_FEATURE | RH_ENDPOINT: | |
943 | switch (wValue) { | |
7770ce47 | 944 | case (RH_ENDPOINT_STALL): OK (0); |
c157d8e2 SR |
945 | } |
946 | break; | |
947 | ||
948 | case RH_CLEAR_FEATURE | RH_CLASS: | |
949 | switch (wValue) { | |
7770ce47 SR |
950 | case RH_C_HUB_LOCAL_POWER: |
951 | OK(0); | |
952 | case (RH_C_HUB_OVER_CURRENT): | |
953 | WR_RH_STAT(RH_HS_OCIC); OK (0); | |
c157d8e2 SR |
954 | } |
955 | break; | |
956 | ||
957 | case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: | |
958 | switch (wValue) { | |
7770ce47 SR |
959 | case (RH_PORT_ENABLE): |
960 | WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); | |
961 | case (RH_PORT_SUSPEND): | |
962 | WR_RH_PORTSTAT (RH_PS_POCI); OK (0); | |
963 | case (RH_PORT_POWER): | |
964 | WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); | |
965 | case (RH_C_PORT_CONNECTION): | |
966 | WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); | |
967 | case (RH_C_PORT_ENABLE): | |
968 | WR_RH_PORTSTAT (RH_PS_PESC); OK (0); | |
969 | case (RH_C_PORT_SUSPEND): | |
970 | WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); | |
971 | case (RH_C_PORT_OVER_CURRENT): | |
972 | WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); | |
973 | case (RH_C_PORT_RESET): | |
974 | WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); | |
c157d8e2 SR |
975 | } |
976 | break; | |
977 | ||
978 | case RH_SET_FEATURE | RH_OTHER | RH_CLASS: | |
979 | switch (wValue) { | |
7770ce47 SR |
980 | case (RH_PORT_SUSPEND): |
981 | WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); | |
982 | case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ | |
983 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
984 | WR_RH_PORTSTAT (RH_PS_PRS); | |
985 | OK (0); | |
986 | case (RH_PORT_POWER): | |
987 | WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); | |
988 | case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ | |
989 | if (RD_RH_PORTSTAT & RH_PS_CCS) | |
990 | WR_RH_PORTSTAT (RH_PS_PES ); | |
991 | OK (0); | |
c157d8e2 SR |
992 | } |
993 | break; | |
994 | ||
7770ce47 | 995 | case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); |
c157d8e2 SR |
996 | |
997 | case RH_GET_DESCRIPTOR: | |
998 | switch ((wValue & 0xff00) >> 8) { | |
7770ce47 | 999 | case (0x01): /* device descriptor */ |
c157d8e2 | 1000 | len = min_t(unsigned int, |
7770ce47 SR |
1001 | leni, |
1002 | min_t(unsigned int, | |
1003 | sizeof (root_hub_dev_des), | |
1004 | wLength)); | |
1005 | data_buf = root_hub_dev_des; OK(len); | |
1006 | case (0x02): /* configuration descriptor */ | |
c157d8e2 | 1007 | len = min_t(unsigned int, |
7770ce47 SR |
1008 | leni, |
1009 | min_t(unsigned int, | |
1010 | sizeof (root_hub_config_des), | |
1011 | wLength)); | |
1012 | data_buf = root_hub_config_des; OK(len); | |
1013 | case (0x03): /* string descriptors */ | |
1014 | if(wValue==0x0300) { | |
1015 | len = min_t(unsigned int, | |
1016 | leni, | |
1017 | min_t(unsigned int, | |
1018 | sizeof (root_hub_str_index0), | |
1019 | wLength)); | |
1020 | data_buf = root_hub_str_index0; | |
1021 | OK(len); | |
1022 | } | |
1023 | if(wValue==0x0301) { | |
1024 | len = min_t(unsigned int, | |
1025 | leni, | |
1026 | min_t(unsigned int, | |
1027 | sizeof (root_hub_str_index1), | |
1028 | wLength)); | |
1029 | data_buf = root_hub_str_index1; | |
1030 | OK(len); | |
c157d8e2 | 1031 | } |
7770ce47 SR |
1032 | default: |
1033 | stat = USB_ST_STALLED; | |
c157d8e2 SR |
1034 | } |
1035 | break; | |
1036 | ||
1037 | case RH_GET_DESCRIPTOR | RH_CLASS: | |
7770ce47 SR |
1038 | { |
1039 | __u32 temp = roothub_a (&gohci); | |
1040 | ||
1041 | data_buf [0] = 9; /* min length; */ | |
1042 | data_buf [1] = 0x29; | |
1043 | data_buf [2] = temp & RH_A_NDP; | |
1044 | data_buf [3] = 0; | |
1045 | if (temp & RH_A_PSM) /* per-port power switching? */ | |
1046 | data_buf [3] |= 0x1; | |
1047 | if (temp & RH_A_NOCP) /* no overcurrent reporting? */ | |
1048 | data_buf [3] |= 0x10; | |
1049 | else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ | |
1050 | data_buf [3] |= 0x8; | |
1051 | ||
1052 | /* corresponds to data_buf[4-7] */ | |
1053 | datab [1] = 0; | |
1054 | data_buf [5] = (temp & RH_A_POTPGT) >> 24; | |
1055 | temp = roothub_b (&gohci); | |
1056 | data_buf [7] = temp & RH_B_DR; | |
1057 | if (data_buf [2] < 7) { | |
1058 | data_buf [8] = 0xff; | |
1059 | } else { | |
1060 | data_buf [0] += 2; | |
1061 | data_buf [8] = (temp & RH_B_DR) >> 8; | |
1062 | data_buf [10] = data_buf [9] = 0xff; | |
1063 | } | |
1064 | ||
1065 | len = min_t(unsigned int, leni, | |
1066 | min_t(unsigned int, data_buf [0], wLength)); | |
1067 | OK (len); | |
c157d8e2 SR |
1068 | } |
1069 | ||
7770ce47 | 1070 | case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); |
c157d8e2 | 1071 | |
7770ce47 | 1072 | case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); |
c157d8e2 SR |
1073 | |
1074 | default: | |
7770ce47 | 1075 | dbg ("unsupported root hub command"); |
c157d8e2 SR |
1076 | stat = USB_ST_STALLED; |
1077 | } | |
1078 | ||
1079 | #ifdef DEBUG | |
7770ce47 | 1080 | ohci_dump_roothub (&gohci, 1); |
c157d8e2 SR |
1081 | #endif |
1082 | ||
1083 | len = min_t(int, len, leni); | |
1084 | if (data != data_buf) | |
7770ce47 | 1085 | memcpy (data, data_buf, len); |
c157d8e2 SR |
1086 | dev->act_len = len; |
1087 | dev->status = stat; | |
1088 | ||
1089 | #ifdef DEBUG | |
1090 | if (transfer_len) | |
1091 | urb_priv.actual_length = transfer_len; | |
7770ce47 | 1092 | pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); |
c157d8e2 SR |
1093 | #endif |
1094 | ||
1095 | return stat; | |
1096 | } | |
1097 | ||
1098 | /*-------------------------------------------------------------------------*/ | |
1099 | ||
1100 | /* common code for handling submit messages - used for all but root hub */ | |
1101 | /* accesses. */ | |
1102 | int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 1103 | int transfer_len, struct devrequest *setup, int interval) |
c157d8e2 SR |
1104 | { |
1105 | int stat = 0; | |
1106 | int maxsize = usb_maxpacket(dev, pipe); | |
1107 | int timeout; | |
1108 | ||
1109 | /* device pulled? Shortcut the action. */ | |
1110 | if (devgone == dev) { | |
1111 | dev->status = USB_ST_CRC_ERR; | |
1112 | return 0; | |
1113 | } | |
7770ce47 | 1114 | |
c157d8e2 SR |
1115 | #ifdef DEBUG |
1116 | urb_priv.actual_length = 0; | |
7770ce47 | 1117 | pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); |
c157d8e2 SR |
1118 | #endif |
1119 | if (!maxsize) { | |
1120 | err("submit_common_message: pipesize for pipe %lx is zero", | |
7770ce47 | 1121 | pipe); |
c157d8e2 SR |
1122 | return -1; |
1123 | } | |
1124 | ||
7770ce47 | 1125 | if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { |
c157d8e2 SR |
1126 | err("sohci_submit_job failed"); |
1127 | return -1; | |
1128 | } | |
1129 | ||
1130 | /* allow more time for a BULK device to react - some are slow */ | |
7770ce47 | 1131 | #define BULK_TO 5000 /* timeout in milliseconds */ |
9dbc3667 | 1132 | if (usb_pipebulk(pipe)) |
c157d8e2 SR |
1133 | timeout = BULK_TO; |
1134 | else | |
1135 | timeout = 100; | |
1136 | ||
1137 | /* wait for it to complete */ | |
1138 | for (;;) { | |
1139 | /* check whether the controller is done */ | |
1140 | stat = hc_interrupt(); | |
1141 | if (stat < 0) { | |
1142 | stat = USB_ST_CRC_ERR; | |
1143 | break; | |
1144 | } | |
7770ce47 SR |
1145 | |
1146 | /* NOTE: since we are not interrupt driven in U-Boot and always | |
1147 | * handle only one URB at a time, we cannot assume the | |
1148 | * transaction finished on the first successful return from | |
1149 | * hc_interrupt().. unless the flag for current URB is set, | |
1150 | * meaning that all TD's to/from device got actually | |
1151 | * transferred and processed. If the current URB is not | |
1152 | * finished we need to re-iterate this loop so as | |
1153 | * hc_interrupt() gets called again as there needs to be some | |
1154 | * more TD's to process still */ | |
1155 | if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { | |
c157d8e2 SR |
1156 | /* 0xff is returned for an SF-interrupt */ |
1157 | break; | |
1158 | } | |
7770ce47 | 1159 | |
c157d8e2 | 1160 | if (--timeout) { |
5b84dd67 | 1161 | mdelay(1); |
7770ce47 SR |
1162 | if (!urb_finished) |
1163 | dbg("\%"); | |
1164 | ||
c157d8e2 SR |
1165 | } else { |
1166 | err("CTL:TIMEOUT "); | |
7770ce47 | 1167 | dbg("submit_common_msg: TO status %x\n", stat); |
c157d8e2 | 1168 | stat = USB_ST_CRC_ERR; |
7770ce47 | 1169 | urb_finished = 1; |
c157d8e2 SR |
1170 | break; |
1171 | } | |
1172 | } | |
7770ce47 | 1173 | #if 0 |
c157d8e2 SR |
1174 | /* we got an Root Hub Status Change interrupt */ |
1175 | if (got_rhsc) { | |
1176 | #ifdef DEBUG | |
7770ce47 | 1177 | ohci_dump_roothub (&gohci, 1); |
c157d8e2 SR |
1178 | #endif |
1179 | got_rhsc = 0; | |
1180 | /* abuse timeout */ | |
1181 | timeout = rh_check_port_status(&gohci); | |
1182 | if (timeout >= 0) { | |
7770ce47 | 1183 | #if 0 /* this does nothing useful, but leave it here in case that changes */ |
c157d8e2 SR |
1184 | /* the called routine adds 1 to the passed value */ |
1185 | usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); | |
1186 | #endif | |
1187 | /* | |
1188 | * XXX | |
1189 | * This is potentially dangerous because it assumes | |
1190 | * that only one device is ever plugged in! | |
1191 | */ | |
1192 | devgone = dev; | |
1193 | } | |
1194 | } | |
7770ce47 | 1195 | #endif |
c157d8e2 SR |
1196 | |
1197 | dev->status = stat; | |
1198 | dev->act_len = transfer_len; | |
1199 | ||
1200 | #ifdef DEBUG | |
7770ce47 | 1201 | pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); |
c157d8e2 SR |
1202 | #endif |
1203 | ||
1204 | /* free TDs in urb_priv */ | |
7770ce47 | 1205 | urb_free_priv (&urb_priv); |
c157d8e2 SR |
1206 | return 0; |
1207 | } | |
1208 | ||
1209 | /* submit routines called from usb.c */ | |
1210 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 1211 | int transfer_len) |
c157d8e2 SR |
1212 | { |
1213 | info("submit_bulk_msg"); | |
1214 | return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); | |
1215 | } | |
1216 | ||
1217 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 1218 | int transfer_len, struct devrequest *setup) |
c157d8e2 SR |
1219 | { |
1220 | int maxsize = usb_maxpacket(dev, pipe); | |
1221 | ||
1222 | info("submit_control_msg"); | |
1223 | #ifdef DEBUG | |
1224 | urb_priv.actual_length = 0; | |
7770ce47 | 1225 | pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); |
c157d8e2 SR |
1226 | #endif |
1227 | if (!maxsize) { | |
1228 | err("submit_control_message: pipesize for pipe %lx is zero", | |
7770ce47 | 1229 | pipe); |
c157d8e2 SR |
1230 | return -1; |
1231 | } | |
1232 | if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { | |
1233 | gohci.rh.dev = dev; | |
1234 | /* root hub - redirect */ | |
1235 | return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, | |
7770ce47 | 1236 | setup); |
c157d8e2 SR |
1237 | } |
1238 | ||
1239 | return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); | |
1240 | } | |
1241 | ||
1242 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
7770ce47 | 1243 | int transfer_len, int interval) |
c157d8e2 SR |
1244 | { |
1245 | info("submit_int_msg"); | |
1246 | return -1; | |
1247 | } | |
1248 | ||
1249 | /*-------------------------------------------------------------------------* | |
1250 | * HC functions | |
1251 | *-------------------------------------------------------------------------*/ | |
1252 | ||
1253 | /* reset the HC and BUS */ | |
1254 | ||
7770ce47 | 1255 | static int hc_reset (ohci_t *ohci) |
c157d8e2 SR |
1256 | { |
1257 | int timeout = 30; | |
7770ce47 | 1258 | int smm_timeout = 50; /* 0,5 sec */ |
c157d8e2 | 1259 | |
7770ce47 SR |
1260 | if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ |
1261 | writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ | |
c157d8e2 | 1262 | info("USB HC TakeOver from SMM"); |
7770ce47 | 1263 | while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { |
5b84dd67 | 1264 | mdelay (10); |
c157d8e2 SR |
1265 | if (--smm_timeout == 0) { |
1266 | err("USB HC TakeOver failed!"); | |
1267 | return -1; | |
1268 | } | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | /* Disable HC interrupts */ | |
7770ce47 | 1273 | writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); |
c157d8e2 SR |
1274 | |
1275 | dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", | |
7770ce47 SR |
1276 | ohci->slot_name, |
1277 | readl (&ohci->regs->control)); | |
c157d8e2 SR |
1278 | |
1279 | /* Reset USB (needed by some controllers) */ | |
1280 | ohci->hc_control = 0; | |
7770ce47 | 1281 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 SR |
1282 | |
1283 | /* HC Reset requires max 10 us delay */ | |
7770ce47 SR |
1284 | writel (OHCI_HCR, &ohci->regs->cmdstatus); |
1285 | while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
c157d8e2 SR |
1286 | if (--timeout == 0) { |
1287 | err("USB HC reset timed out!"); | |
1288 | return -1; | |
1289 | } | |
7770ce47 | 1290 | udelay (1); |
c157d8e2 SR |
1291 | } |
1292 | return 0; | |
1293 | } | |
1294 | ||
1295 | /*-------------------------------------------------------------------------*/ | |
1296 | ||
1297 | /* Start an OHCI controller, set the BUS operational | |
1298 | * enable interrupts | |
1299 | * connect the virtual root hub */ | |
1300 | ||
7770ce47 | 1301 | static int hc_start (ohci_t * ohci) |
c157d8e2 SR |
1302 | { |
1303 | __u32 mask; | |
1304 | unsigned int fminterval; | |
1305 | ||
1306 | ohci->disabled = 1; | |
1307 | ||
1308 | /* Tell the controller where the control and bulk lists are | |
1309 | * The lists are empty now. */ | |
1310 | ||
7770ce47 SR |
1311 | writel (0, &ohci->regs->ed_controlhead); |
1312 | writel (0, &ohci->regs->ed_bulkhead); | |
c157d8e2 | 1313 | |
7770ce47 | 1314 | writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ |
c157d8e2 SR |
1315 | |
1316 | fminterval = 0x2edf; | |
7770ce47 | 1317 | writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); |
c157d8e2 | 1318 | fminterval |= ((((fminterval - 210) * 6) / 7) << 16); |
7770ce47 SR |
1319 | writel (fminterval, &ohci->regs->fminterval); |
1320 | writel (0x628, &ohci->regs->lsthresh); | |
c157d8e2 SR |
1321 | |
1322 | /* start controller operations */ | |
1323 | ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; | |
1324 | ohci->disabled = 0; | |
7770ce47 | 1325 | writel (ohci->hc_control, &ohci->regs->control); |
c157d8e2 SR |
1326 | |
1327 | /* disable all interrupts */ | |
1328 | mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | | |
7770ce47 SR |
1329 | OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | |
1330 | OHCI_INTR_OC | OHCI_INTR_MIE); | |
1331 | writel (mask, &ohci->regs->intrdisable); | |
c157d8e2 SR |
1332 | /* clear all interrupts */ |
1333 | mask &= ~OHCI_INTR_MIE; | |
7770ce47 | 1334 | writel (mask, &ohci->regs->intrstatus); |
c157d8e2 SR |
1335 | /* Choose the interrupts we care about now - but w/o MIE */ |
1336 | mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; | |
7770ce47 | 1337 | writel (mask, &ohci->regs->intrenable); |
c157d8e2 SR |
1338 | |
1339 | #ifdef OHCI_USE_NPS | |
1340 | /* required for AMD-756 and some Mac platforms */ | |
7770ce47 SR |
1341 | writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, |
1342 | &ohci->regs->roothub.a); | |
1343 | writel (RH_HS_LPSC, &ohci->regs->roothub.status); | |
1344 | #endif /* OHCI_USE_NPS */ | |
c157d8e2 | 1345 | |
c157d8e2 | 1346 | /* POTPGT delay is bits 24-31, in 2 ms units. */ |
7770ce47 | 1347 | mdelay ((roothub_a (ohci) >> 23) & 0x1fe); |
c157d8e2 SR |
1348 | |
1349 | /* connect the virtual root hub */ | |
1350 | ohci->rh.devnum = 0; | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | /*-------------------------------------------------------------------------*/ | |
1356 | ||
1357 | /* an interrupt happens */ | |
1358 | ||
7770ce47 SR |
1359 | static int |
1360 | hc_interrupt (void) | |
c157d8e2 SR |
1361 | { |
1362 | ohci_t *ohci = &gohci; | |
1363 | struct ohci_regs *regs = ohci->regs; | |
1364 | int ints; | |
1365 | int stat = -1; | |
1366 | ||
7770ce47 SR |
1367 | if ((ohci->hcca->done_head != 0) && |
1368 | !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { | |
1369 | ||
1370 | ints = OHCI_INTR_WDH; | |
1371 | ||
1372 | } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { | |
1373 | ohci->disabled++; | |
1374 | err ("%s device removed!", ohci->slot_name); | |
1375 | return -1; | |
1376 | ||
1377 | } else if ((ints &= readl (®s->intrenable)) == 0) { | |
1378 | dbg("hc_interrupt: returning..\n"); | |
1379 | return 0xff; | |
c157d8e2 SR |
1380 | } |
1381 | ||
1382 | /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ | |
1383 | ||
1384 | if (ints & OHCI_INTR_RHSC) { | |
1385 | got_rhsc = 1; | |
7770ce47 | 1386 | stat = 0xff; |
c157d8e2 SR |
1387 | } |
1388 | ||
1389 | if (ints & OHCI_INTR_UE) { | |
1390 | ohci->disabled++; | |
7770ce47 SR |
1391 | err ("OHCI Unrecoverable Error, controller usb-%s disabled", |
1392 | ohci->slot_name); | |
c157d8e2 SR |
1393 | /* e.g. due to PCI Master/Target Abort */ |
1394 | ||
1395 | #ifdef DEBUG | |
7770ce47 | 1396 | ohci_dump (ohci, 1); |
c157d8e2 SR |
1397 | #endif |
1398 | /* FIXME: be optimistic, hope that bug won't repeat often. */ | |
1399 | /* Make some non-interrupt context restart the controller. */ | |
1400 | /* Count and limit the retries though; either hardware or */ | |
1401 | /* software errors can go forever... */ | |
7770ce47 | 1402 | hc_reset (ohci); |
c157d8e2 SR |
1403 | return -1; |
1404 | } | |
1405 | ||
1406 | if (ints & OHCI_INTR_WDH) { | |
7770ce47 SR |
1407 | writel (OHCI_INTR_WDH, ®s->intrdisable); |
1408 | stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); | |
1409 | writel (OHCI_INTR_WDH, ®s->intrenable); | |
c157d8e2 SR |
1410 | } |
1411 | ||
1412 | if (ints & OHCI_INTR_SO) { | |
1413 | dbg("USB Schedule overrun\n"); | |
7770ce47 | 1414 | writel (OHCI_INTR_SO, ®s->intrenable); |
c157d8e2 SR |
1415 | stat = -1; |
1416 | } | |
1417 | ||
1418 | /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ | |
1419 | if (ints & OHCI_INTR_SF) { | |
7770ce47 | 1420 | unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; |
5b84dd67 | 1421 | mdelay(1); |
7770ce47 | 1422 | writel (OHCI_INTR_SF, ®s->intrdisable); |
c157d8e2 | 1423 | if (ohci->ed_rm_list[frame] != NULL) |
7770ce47 | 1424 | writel (OHCI_INTR_SF, ®s->intrenable); |
c157d8e2 SR |
1425 | stat = 0xff; |
1426 | } | |
1427 | ||
7770ce47 | 1428 | writel (ints, ®s->intrstatus); |
c157d8e2 SR |
1429 | return stat; |
1430 | } | |
1431 | ||
1432 | /*-------------------------------------------------------------------------*/ | |
1433 | ||
1434 | /*-------------------------------------------------------------------------*/ | |
1435 | ||
1436 | /* De-allocate all resources.. */ | |
1437 | ||
7770ce47 | 1438 | static void hc_release_ohci (ohci_t *ohci) |
c157d8e2 | 1439 | { |
7770ce47 | 1440 | dbg ("USB HC release ohci usb-%s", ohci->slot_name); |
c157d8e2 SR |
1441 | |
1442 | if (!ohci->disabled) | |
7770ce47 | 1443 | hc_reset (ohci); |
c157d8e2 SR |
1444 | } |
1445 | ||
1446 | /*-------------------------------------------------------------------------*/ | |
1447 | ||
1448 | /* | |
1449 | * low level initalisation routine, called from usb.c | |
1450 | */ | |
1451 | static char ohci_inited = 0; | |
1452 | ||
06d513ec | 1453 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) |
c157d8e2 | 1454 | { |
7770ce47 SR |
1455 | memset (&gohci, 0, sizeof (ohci_t)); |
1456 | memset (&urb_priv, 0, sizeof (urb_priv_t)); | |
c157d8e2 SR |
1457 | |
1458 | /* align the storage */ | |
7770ce47 | 1459 | if ((__u32)&ghcca[0] & 0xff) { |
c157d8e2 SR |
1460 | err("HCCA not aligned!!"); |
1461 | return -1; | |
1462 | } | |
1463 | phcca = &ghcca[0]; | |
1464 | info("aligned ghcca %p", phcca); | |
1465 | memset(&ohci_dev, 0, sizeof(struct ohci_device)); | |
7770ce47 | 1466 | if ((__u32)&ohci_dev.ed[0] & 0x7) { |
c157d8e2 SR |
1467 | err("EDs not aligned!!"); |
1468 | return -1; | |
1469 | } | |
1470 | memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); | |
7770ce47 | 1471 | if ((__u32)gtd & 0x7) { |
c157d8e2 SR |
1472 | err("TDs not aligned!!"); |
1473 | return -1; | |
1474 | } | |
1475 | ptd = gtd; | |
1476 | gohci.hcca = phcca; | |
7770ce47 | 1477 | memset (phcca, 0, sizeof (struct ohci_hcca)); |
c157d8e2 SR |
1478 | |
1479 | gohci.disabled = 1; | |
1480 | gohci.sleeping = 0; | |
1481 | gohci.irq = -1; | |
887e2ec9 | 1482 | #if defined(CONFIG_440EP) |
6d0f6bcf JCPV |
1483 | gohci.regs = (struct ohci_regs *)(CONFIG_SYS_PERIPHERAL_BASE | 0x1000); |
1484 | #elif defined(CONFIG_440EPX) || defined(CONFIG_SYS_USB_HOST) | |
1485 | gohci.regs = (struct ohci_regs *)(CONFIG_SYS_USB_HOST); | |
887e2ec9 | 1486 | #endif |
c157d8e2 SR |
1487 | |
1488 | gohci.flags = 0; | |
1489 | gohci.slot_name = "ppc440"; | |
1490 | ||
7770ce47 SR |
1491 | if (hc_reset (&gohci) < 0) { |
1492 | hc_release_ohci (&gohci); | |
c157d8e2 SR |
1493 | return -1; |
1494 | } | |
1495 | ||
7770ce47 SR |
1496 | if (hc_start (&gohci) < 0) { |
1497 | err ("can't start usb-%s", gohci.slot_name); | |
1498 | hc_release_ohci (&gohci); | |
c157d8e2 SR |
1499 | return -1; |
1500 | } | |
7770ce47 | 1501 | |
c157d8e2 | 1502 | #ifdef DEBUG |
7770ce47 | 1503 | ohci_dump (&gohci, 1); |
c157d8e2 SR |
1504 | #endif |
1505 | ohci_inited = 1; | |
7770ce47 | 1506 | urb_finished = 1; |
c157d8e2 | 1507 | |
c157d8e2 SR |
1508 | return 0; |
1509 | } | |
1510 | ||
c7e3b2b5 | 1511 | int usb_lowlevel_stop(int index) |
c157d8e2 SR |
1512 | { |
1513 | /* this gets called really early - before the controller has */ | |
1514 | /* even been initialized! */ | |
1515 | if (!ohci_inited) | |
1516 | return 0; | |
1517 | /* TODO release any interrupts, etc. */ | |
1518 | /* call hc_release_ohci() here ? */ | |
7770ce47 | 1519 | hc_reset (&gohci); |
c157d8e2 SR |
1520 | return 0; |
1521 | } | |
1522 | ||
7770ce47 | 1523 | #endif /* CONFIG_USB_OHCI */ |