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47d41cc3 | 1 | /* |
21608275 | 2 | * Copyright 2009-2010 Freescale Semiconductor, Inc. |
47d41cc3 KG |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef _ASM_CONFIG_H_ | |
22 | #define _ASM_CONFIG_H_ | |
23 | ||
a16028da MF |
24 | #define CONFIG_LMB |
25 | ||
87c90639 | 26 | #ifndef CONFIG_MAX_MEM_MAPPED |
bd76729b | 27 | #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
87c90639 KG |
28 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) |
29 | #else | |
2ede879f | 30 | #define CONFIG_MAX_MEM_MAPPED (256 << 20) |
87c90639 KG |
31 | #endif |
32 | #endif | |
33 | ||
f732a759 PT |
34 | /* Check if boards need to enable FSL DMA engine for SDRAM init */ |
35 | #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) | |
36 | #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ | |
37 | ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ | |
38 | !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) | |
017f11f6 | 39 | #define CONFIG_FSL_DMA |
47d41cc3 | 40 | #endif |
017f11f6 PT |
41 | #endif |
42 | ||
3b1f243b | 43 | #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ |
21608275 | 44 | defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ |
3b1f243b | 45 | defined(CONFIG_P2020) || defined(CONFIG_MPC8641) |
7e4259bb KG |
46 | #define CONFIG_MAX_CPUS 2 |
47 | #elif defined(CONFIG_PPC_P4080) | |
48 | #define CONFIG_MAX_CPUS 8 | |
19dbcc96 KG |
49 | #elif defined(CONFIG_PPC_P5020) |
50 | #define CONFIG_MAX_CPUS 2 | |
0e870980 | 51 | #else |
7e4259bb | 52 | #define CONFIG_MAX_CPUS 1 |
0e870980 PA |
53 | #endif |
54 | ||
5ccd29c3 PT |
55 | /* |
56 | * Provide a default boot page translation virtual address that lines up with | |
57 | * Freescale's default e500 reset page. | |
58 | */ | |
59 | #if (defined(CONFIG_E500) && defined(CONFIG_MP)) | |
60 | #ifndef CONFIG_BPTR_VIRT_ADDR | |
61 | #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 | |
62 | #endif | |
63 | #endif | |
64 | ||
3ad89c4e KG |
65 | /* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ |
66 | #if defined(CONFIG_TSEC_ENET) && \ | |
67 | (defined(CONFIG_P1020) || defined(CONFIG_P1011)) | |
68 | #define CONFIG_TSECV2 | |
69 | #endif | |
70 | ||
929a2138 KP |
71 | /* |
72 | * SEC (crypto unit) major compatible version determination | |
73 | */ | |
22f292c7 KP |
74 | #if defined(CONFIG_FSL_CORENET) |
75 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
76 | #elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) | |
929a2138 KP |
77 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
78 | #endif | |
79 | ||
94e9411b KG |
80 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
81 | #if defined(CONFIG_E500MC) | |
82 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
83 | #elif defined(CONFIG_E500) | |
84 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
85 | #endif | |
86 | ||
85829017 PT |
87 | /* Relocation to SDRAM works on all PPC boards */ |
88 | #define CONFIG_RELOC_FIXUP_WORKS | |
89 | ||
f51cdaf1 BB |
90 | /* Since so many PPC SOCs have a semi-common LBC, define this here */ |
91 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ | |
92 | defined(CONFIG_MPC83xx) | |
93 | #define CONFIG_FSL_LBC | |
94 | #endif | |
95 | ||
017f11f6 | 96 | #endif /* _ASM_CONFIG_H_ */ |