projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 47d41cc3 | 1 | /* |
| b8cdd014 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
| 47d41cc3 | 3 | * |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 47d41cc3 KG |
5 | */ |
| 6 | ||
| 7 | #ifndef _ASM_CONFIG_H_ | |
| 8 | #define _ASM_CONFIG_H_ | |
| 9 | ||
| 243be8e2 KG |
10 | #ifdef CONFIG_MPC85xx |
| 11 | #include <asm/config_mpc85xx.h> | |
| 5614e71b | 12 | #define CONFIG_SYS_FSL_DDR |
| 243be8e2 KG |
13 | #endif |
| 14 | ||
| 15 | #ifdef CONFIG_MPC86xx | |
| 16 | #include <asm/config_mpc86xx.h> | |
| 5614e71b YS |
17 | #define CONFIG_SYS_FSL_DDR |
| 18 | #endif | |
| 19 | ||
| 20 | #ifdef CONFIG_MPC83xx | |
| 21 | #define CONFIG_SYS_FSL_DDR | |
| 243be8e2 KG |
22 | #endif |
| 23 | ||
| 7ac3cc20 YS |
24 | #ifndef HWCONFIG_BUFFER_SIZE |
| 25 | #define HWCONFIG_BUFFER_SIZE 256 | |
| 26 | #endif | |
| 27 | ||
| 273feafe MH |
28 | /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ |
| 29 | #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) | |
| 30 | # ifndef CONFIG_HARD_SPI | |
| 31 | # define CONFIG_HARD_SPI | |
| 32 | # endif | |
| 33 | #endif | |
| 34 | ||
| a16028da | 35 | #define CONFIG_LMB |
| fca43cc8 JR |
36 | #define CONFIG_SYS_BOOT_RAMDISK_HIGH |
| 37 | #define CONFIG_SYS_BOOT_GET_CMDLINE | |
| 38 | #define CONFIG_SYS_BOOT_GET_KBD | |
| a16028da | 39 | |
| 87c90639 | 40 | #ifndef CONFIG_MAX_MEM_MAPPED |
| d29d17d7 YS |
41 | #if defined(CONFIG_4xx) || \ |
| 42 | defined(CONFIG_E500) || \ | |
| 43 | defined(CONFIG_MPC86xx) || \ | |
| 44 | defined(CONFIG_E300) | |
| 87c90639 KG |
45 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) |
| 46 | #else | |
| 2ede879f | 47 | #define CONFIG_MAX_MEM_MAPPED (256 << 20) |
| 87c90639 KG |
48 | #endif |
| 49 | #endif | |
| 50 | ||
| f732a759 PT |
51 | /* Check if boards need to enable FSL DMA engine for SDRAM init */ |
| 52 | #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) | |
| 53 | #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ | |
| 54 | ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ | |
| 55 | !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) | |
| 017f11f6 | 56 | #define CONFIG_FSL_DMA |
| 47d41cc3 | 57 | #endif |
| 017f11f6 PT |
58 | #endif |
| 59 | ||
| 243be8e2 | 60 | #ifndef CONFIG_MAX_CPUS |
| 7e4259bb | 61 | #define CONFIG_MAX_CPUS 1 |
| 0e870980 PA |
62 | #endif |
| 63 | ||
| 5ccd29c3 PT |
64 | /* |
| 65 | * Provide a default boot page translation virtual address that lines up with | |
| 66 | * Freescale's default e500 reset page. | |
| 67 | */ | |
| 68 | #if (defined(CONFIG_E500) && defined(CONFIG_MP)) | |
| 69 | #ifndef CONFIG_BPTR_VIRT_ADDR | |
| 70 | #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 | |
| 71 | #endif | |
| 72 | #endif | |
| 73 | ||
| 929a2138 KP |
74 | /* |
| 75 | * SEC (crypto unit) major compatible version determination | |
| 76 | */ | |
| 243be8e2 | 77 | #if defined(CONFIG_MPC83xx) |
| 0181937f | 78 | #define CONFIG_SYS_FSL_SEC_BE |
| 929a2138 KP |
79 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| 80 | #endif | |
| 81 | ||
| f51cdaf1 BB |
82 | /* Since so many PPC SOCs have a semi-common LBC, define this here */ |
| 83 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ | |
| 84 | defined(CONFIG_MPC83xx) | |
| d789b5f5 | 85 | #if !defined(CONFIG_FSL_IFC) |
| f51cdaf1 BB |
86 | #define CONFIG_FSL_LBC |
| 87 | #endif | |
| d789b5f5 | 88 | #endif |
| f51cdaf1 | 89 | |
| 063c1263 AF |
90 | /* The TSEC driver uses the PHYLIB infrastructure */ |
| 91 | #ifndef CONFIG_PHYLIB | |
| 92 | #if defined(CONFIG_TSEC_ENET) | |
| 93 | #define CONFIG_PHYLIB | |
| 94 | ||
| 95 | #include <config_phylib_all_drivers.h> | |
| 96 | #endif /* TSEC_ENET */ | |
| 97 | #endif /* !CONFIG_PHYLIB */ | |
| 98 | ||
| c916d7c9 KG |
99 | /* The FMAN driver uses the PHYLIB infrastructure */ |
| 100 | #if defined(CONFIG_FMAN_ENET) | |
| 101 | #define CONFIG_PHYLIB | |
| 102 | #endif | |
| 103 | ||
| f2a37fcd AA |
104 | /* All PPC boards must swap IDE bytes */ |
| 105 | #define CONFIG_IDE_SWAP_IO | |
| 106 | ||
| f27445cb TC |
107 | #if defined(CONFIG_DM_SERIAL) |
| 108 | /* | |
| 109 | * TODO: Convert this to a clock driver exists that can give us the UART | |
| 110 | * clock here. | |
| 111 | */ | |
| 112 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
| 113 | #endif | |
| 114 | ||
| 017f11f6 | 115 | #endif /* _ASM_CONFIG_H_ */ |