]>
Commit | Line | Data |
---|---|---|
243be8e2 | 1 | /* |
19a8dbdc | 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
243be8e2 KG |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
22 | #define _ASM_MPC85xx_CONFIG_H_ | |
23 | ||
24 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
25 | ||
e46fedfe TT |
26 | #ifdef CONFIG_SYS_CCSRBAR_DEFAULT |
27 | #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." | |
28 | #endif | |
29 | ||
243be8e2 KG |
30 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
31 | #if defined(CONFIG_E500MC) | |
32 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
33 | #elif defined(CONFIG_E500) | |
34 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
35 | #endif | |
36 | ||
37 | #if defined(CONFIG_MPC8536) | |
38 | #define CONFIG_MAX_CPUS 1 | |
39 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 40 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 |
243be8e2 | 41 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 42 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 43 | |
d1a24f06 | 44 | #elif defined(CONFIG_MPC8540) |
243be8e2 KG |
45 | #define CONFIG_MAX_CPUS 1 |
46 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
e46fedfe | 47 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 48 | |
d1a24f06 | 49 | #elif defined(CONFIG_MPC8541) |
243be8e2 KG |
50 | #define CONFIG_MAX_CPUS 1 |
51 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
52 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 53 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
54 | |
55 | #elif defined(CONFIG_MPC8544) | |
56 | #define CONFIG_MAX_CPUS 1 | |
57 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
e4879afb | 58 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 59 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 60 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
61 | |
62 | #elif defined(CONFIG_MPC8548) | |
63 | #define CONFIG_MAX_CPUS 1 | |
64 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
e4879afb | 65 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 66 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 67 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
5ace2992 | 68 | #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 |
2b3a1cdd | 69 | #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
aada81de | 70 | #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
7d67ed58 LG |
71 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
72 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
73 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
74 | #define CONFIG_SYS_FSL_RMU | |
75 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 KG |
76 | |
77 | #elif defined(CONFIG_MPC8555) | |
78 | #define CONFIG_MAX_CPUS 1 | |
79 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
80 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 81 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
82 | |
83 | #elif defined(CONFIG_MPC8560) | |
84 | #define CONFIG_MAX_CPUS 1 | |
85 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
e46fedfe | 86 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
87 | |
88 | #elif defined(CONFIG_MPC8568) | |
89 | #define CONFIG_MAX_CPUS 1 | |
90 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
91 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
fdb4dad3 KG |
92 | #define QE_MURAM_SIZE 0x10000UL |
93 | #define MAX_QE_RISC 2 | |
94 | #define QE_NUM_OF_SNUM 28 | |
e46fedfe | 95 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
96 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
97 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
98 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
99 | #define CONFIG_SYS_FSL_RMU | |
100 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 KG |
101 | |
102 | #elif defined(CONFIG_MPC8569) | |
103 | #define CONFIG_MAX_CPUS 1 | |
104 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
105 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
fdb4dad3 KG |
106 | #define QE_MURAM_SIZE 0x20000UL |
107 | #define MAX_QE_RISC 4 | |
108 | #define QE_NUM_OF_SNUM 46 | |
e46fedfe | 109 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
110 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
111 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
112 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
113 | #define CONFIG_SYS_FSL_RMU | |
114 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 KG |
115 | |
116 | #elif defined(CONFIG_MPC8572) | |
117 | #define CONFIG_MAX_CPUS 2 | |
118 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 119 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 120 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 121 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
eb0aff77 | 122 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
91671913 | 123 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
243be8e2 KG |
124 | |
125 | #elif defined(CONFIG_P1010) | |
126 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 127 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 128 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 129 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
130 | #define CONFIG_TSECV2 |
131 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
132 | #define CONFIG_FSL_SATA_V2 |
133 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
134 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
135 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
8f29084a | 136 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
1b719e66 | 137 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 138 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 139 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
bc6bbd6b | 140 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
243be8e2 | 141 | |
093cffbe | 142 | /* P1011 is single core version of P1020 */ |
243be8e2 KG |
143 | #elif defined(CONFIG_P1011) |
144 | #define CONFIG_MAX_CPUS 1 | |
145 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 146 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 147 | #define CONFIG_TSECV2 |
b03a466d | 148 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 149 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 150 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
151 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
152 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
243be8e2 | 153 | |
093cffbe | 154 | /* P1012 is single core version of P1021 */ |
243be8e2 KG |
155 | #elif defined(CONFIG_P1012) |
156 | #define CONFIG_MAX_CPUS 1 | |
157 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 158 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 159 | #define CONFIG_TSECV2 |
b03a466d | 160 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 161 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 162 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
163 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
164 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
165 | #define QE_MURAM_SIZE 0x6000UL |
166 | #define MAX_QE_RISC 1 | |
167 | #define QE_NUM_OF_SNUM 28 | |
243be8e2 | 168 | |
093cffbe | 169 | /* P1013 is single core version of P1022 */ |
243be8e2 KG |
170 | #elif defined(CONFIG_P1013) |
171 | #define CONFIG_MAX_CPUS 1 | |
172 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 173 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
174 | #define CONFIG_TSECV2 |
175 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
3e0529f7 | 176 | #define CONFIG_FSL_SATA_V2 |
e46fedfe | 177 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
178 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
179 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
180 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
243be8e2 KG |
181 | |
182 | #elif defined(CONFIG_P1014) | |
183 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 184 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 185 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 186 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
187 | #define CONFIG_TSECV2 |
188 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
189 | #define CONFIG_FSL_SATA_V2 |
190 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
191 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
192 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
1b719e66 | 193 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 194 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 195 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
bc6bbd6b | 196 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
243be8e2 | 197 | |
093cffbe | 198 | /* P1017 is single core version of P1023 */ |
67a719da RZ |
199 | #elif defined(CONFIG_P1017) |
200 | #define CONFIG_MAX_CPUS 1 | |
201 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
202 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
203 | #define CONFIG_SYS_NUM_FMAN 1 | |
204 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
205 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
206 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 | |
207 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 208 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 209 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 210 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
67a719da | 211 | |
243be8e2 KG |
212 | #elif defined(CONFIG_P1020) |
213 | #define CONFIG_MAX_CPUS 2 | |
214 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 215 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 216 | #define CONFIG_TSECV2 |
b03a466d | 217 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 218 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 219 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
220 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
221 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
243be8e2 KG |
222 | |
223 | #elif defined(CONFIG_P1021) | |
224 | #define CONFIG_MAX_CPUS 2 | |
225 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 226 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 227 | #define CONFIG_TSECV2 |
b03a466d | 228 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 229 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 230 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
231 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
232 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
233 | #define QE_MURAM_SIZE 0x6000UL |
234 | #define MAX_QE_RISC 1 | |
235 | #define QE_NUM_OF_SNUM 28 | |
243be8e2 KG |
236 | |
237 | #elif defined(CONFIG_P1022) | |
238 | #define CONFIG_MAX_CPUS 2 | |
239 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 240 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
241 | #define CONFIG_TSECV2 |
242 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
3e0529f7 | 243 | #define CONFIG_FSL_SATA_V2 |
e46fedfe | 244 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
245 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
246 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
247 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
243be8e2 | 248 | |
67a719da RZ |
249 | #elif defined(CONFIG_P1023) |
250 | #define CONFIG_MAX_CPUS 2 | |
251 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
252 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
253 | #define CONFIG_SYS_NUM_FMAN 1 | |
254 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
255 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
256 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 | |
257 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 258 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 259 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 260 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
67a719da | 261 | |
093cffbe KG |
262 | /* P1024 is lower end variant of P1020 */ |
263 | #elif defined(CONFIG_P1024) | |
264 | #define CONFIG_MAX_CPUS 2 | |
265 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 266 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
267 | #define CONFIG_TSECV2 |
268 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
269 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 270 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
271 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
272 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
273 | ||
274 | /* P1025 is lower end variant of P1021 */ | |
275 | #elif defined(CONFIG_P1025) | |
276 | #define CONFIG_MAX_CPUS 2 | |
277 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 278 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
279 | #define CONFIG_TSECV2 |
280 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
281 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 282 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
283 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
284 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
285 | #define QE_MURAM_SIZE 0x6000UL |
286 | #define MAX_QE_RISC 1 | |
287 | #define QE_NUM_OF_SNUM 28 | |
093cffbe KG |
288 | |
289 | /* P2010 is single core version of P2020 */ | |
243be8e2 KG |
290 | #elif defined(CONFIG_P2010) |
291 | #define CONFIG_MAX_CPUS 1 | |
292 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 293 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 294 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 295 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 296 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 297 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
243be8e2 KG |
298 | |
299 | #elif defined(CONFIG_P2020) | |
300 | #define CONFIG_MAX_CPUS 2 | |
301 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 302 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 303 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 304 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 305 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 306 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
7d67ed58 LG |
307 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
308 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
309 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
310 | #define CONFIG_SYS_FSL_RMU | |
311 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 | 312 | |
3e978f5d | 313 | #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ |
d1001e3f | 314 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
1f97987a KG |
315 | #define CONFIG_MAX_CPUS 4 |
316 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
317 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
318 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
3e0529f7 | 319 | #define CONFIG_FSL_SATA_V2 |
1f97987a KG |
320 | #define CONFIG_SYS_NUM_FMAN 1 |
321 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
322 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
323 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
324 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
325 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 | |
326 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
e46fedfe | 327 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
1f97987a KG |
328 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
329 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 330 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
1f97987a | 331 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5e23ab0a | 332 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
43f082bb | 333 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
4108508a | 334 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
335 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
336 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
337 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
338 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
339 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
340 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
341 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 342 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
1f97987a | 343 | |
243be8e2 | 344 | #elif defined(CONFIG_PPC_P3041) |
d1001e3f | 345 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
243be8e2 | 346 | #define CONFIG_MAX_CPUS 4 |
b5c8753f | 347 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
348 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
349 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
3e0529f7 | 350 | #define CONFIG_FSL_SATA_V2 |
fbee0f7f KG |
351 | #define CONFIG_SYS_NUM_FMAN 1 |
352 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
353 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
354 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
c657d898 | 355 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 356 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 357 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 358 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
359 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
360 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 361 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 362 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
57125f22 | 363 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
43f082bb | 364 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
4108508a | 365 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
366 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
367 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
368 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
369 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
370 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
371 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
372 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 373 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
243be8e2 | 374 | |
3e978f5d | 375 | #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ |
d1001e3f | 376 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
243be8e2 | 377 | #define CONFIG_MAX_CPUS 8 |
b5c8753f | 378 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
243be8e2 KG |
379 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
380 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
381 | #define CONFIG_SYS_NUM_FMAN 2 | |
382 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
383 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
384 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
385 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
386 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
c657d898 | 387 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 388 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
8f29084a | 389 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
e46fedfe | 390 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
243be8e2 KG |
391 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
392 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
fa8d23c0 | 393 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
243be8e2 KG |
394 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
395 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
396 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
4e0be34a | 397 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 |
243be8e2 | 398 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 |
5e23ab0a | 399 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
243be8e2 | 400 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 |
df8af0b4 | 401 | #define CONFIG_SYS_P4080_ERRATUM_SERDES9 |
d90fdba6 | 402 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
da30b9fd | 403 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
43f082bb | 404 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
4108508a | 405 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
406 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
407 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
408 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
409 | #define CONFIG_SYS_FSL_RMU | |
410 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
33eee330 SW |
411 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
412 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 | |
413 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 | |
d59c5570 | 414 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
243be8e2 | 415 | |
3e978f5d | 416 | #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ |
d1001e3f | 417 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
243be8e2 | 418 | #define CONFIG_MAX_CPUS 2 |
b5c8753f | 419 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
420 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
421 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
3e0529f7 | 422 | #define CONFIG_FSL_SATA_V2 |
fbee0f7f KG |
423 | #define CONFIG_SYS_NUM_FMAN 1 |
424 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
425 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
426 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
c657d898 | 427 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 428 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 429 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 430 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
431 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
432 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 433 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 434 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
4108508a | 435 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
436 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
437 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
438 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
439 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
440 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
441 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 | |
d59c5570 | 442 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
243be8e2 | 443 | |
4905443f TT |
444 | #elif defined(CONFIG_PPC_P5040) |
445 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 | |
446 | #define CONFIG_MAX_CPUS 4 | |
447 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 | |
448 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
449 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
450 | #define CONFIG_SYS_NUM_FMAN 2 | |
451 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
452 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
453 | #define CONFIG_SYS_NUM_FM2_DTSEC 5 | |
454 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
455 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
456 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
457 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
458 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
459 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
460 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
461 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
462 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
463 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
464 | #define CONFIG_SYS_FSL_ERRATUM_USB138 | |
465 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 | |
466 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 | |
467 | #define CONFIG_SYS_FSL_ERRATUM_A004699 | |
468 | #define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC | |
469 | #define CONFIG_SYS_FSL_ERRATUM_A004510 | |
470 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
471 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
472 | ||
19a8dbdc PK |
473 | #elif defined(CONFIG_BSC9131) |
474 | #define CONFIG_MAX_CPUS 1 | |
475 | #define CONFIG_FSL_SDHC_V2_3 | |
476 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
477 | #define CONFIG_TSECV2 | |
478 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
479 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
480 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
481 | #define CONFIG_NAND_FSL_IFC | |
482 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 | |
483 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
484 | ||
9e758758 YS |
485 | #elif defined(CONFIG_PPC_T4240) |
486 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
487 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
488 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
489 | #define CONFIG_MAX_CPUS 12 | |
490 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 | |
491 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
492 | #define CONFIG_SYS_FSL_SRDS_3 | |
493 | #define CONFIG_SYS_FSL_SRDS_4 | |
494 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
495 | #define CONFIG_SYS_NUM_FMAN 2 | |
496 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 | |
497 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
498 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 | |
499 | #define CONFIG_SYS_NUM_FM2_10GEC 2 | |
500 | #define CONFIG_NUM_DDR_CONTROLLERS 3 | |
501 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 | |
111fd19e | 502 | #define CONFIG_SYS_FMAN_V3 |
9e758758 YS |
503 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
504 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
505 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
506 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
507 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
508 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
509 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
510 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
511 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
512 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
513 | ||
d2404141 YS |
514 | #elif defined(CONFIG_PPC_B4860) |
515 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
516 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
517 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
518 | #define CONFIG_MAX_CPUS 4 | |
519 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 | |
520 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
521 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
522 | #define CONFIG_SYS_NUM_FMAN 1 | |
523 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 | |
524 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
525 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
526 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 | |
111fd19e | 527 | #define CONFIG_SYS_FMAN_V3 |
d2404141 YS |
528 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
529 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
530 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
531 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
532 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
533 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
534 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
535 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
536 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
537 | ||
243be8e2 KG |
538 | #else |
539 | #error Processor type not defined for this platform | |
540 | #endif | |
541 | ||
e46fedfe TT |
542 | #ifndef CONFIG_SYS_CCSRBAR_DEFAULT |
543 | #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." | |
544 | #endif | |
545 | ||
243be8e2 | 546 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |