projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 243be8e2 KG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License as | |
| 6 | * published by the Free Software Foundation; either version 2 of | |
| 7 | * the License, or (at your option) any later version. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program; if not, write to the Free Software | |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 17 | * MA 02111-1307 USA | |
| 18 | * | |
| 19 | */ | |
| 20 | ||
| 21 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
| 22 | #define _ASM_MPC85xx_CONFIG_H_ | |
| 23 | ||
| 24 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
| 25 | ||
| 26 | /* Number of TLB CAM entries we have on FSL Book-E chips */ | |
| 27 | #if defined(CONFIG_E500MC) | |
| 28 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
| 29 | #elif defined(CONFIG_E500) | |
| 30 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
| 31 | #endif | |
| 32 | ||
| 33 | #if defined(CONFIG_MPC8536) | |
| 34 | #define CONFIG_MAX_CPUS 1 | |
| 35 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 36 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 37 | ||
| d1a24f06 | 38 | #elif defined(CONFIG_MPC8540) |
| 243be8e2 KG |
39 | #define CONFIG_MAX_CPUS 1 |
| 40 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
| 41 | ||
| d1a24f06 | 42 | #elif defined(CONFIG_MPC8541) |
| 243be8e2 KG |
43 | #define CONFIG_MAX_CPUS 1 |
| 44 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
| 45 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 46 | ||
| 47 | #elif defined(CONFIG_MPC8544) | |
| 48 | #define CONFIG_MAX_CPUS 1 | |
| 49 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
| 50 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 51 | ||
| 52 | #elif defined(CONFIG_MPC8548) | |
| 53 | #define CONFIG_MAX_CPUS 1 | |
| 54 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
| 55 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 56 | ||
| 57 | #elif defined(CONFIG_MPC8555) | |
| 58 | #define CONFIG_MAX_CPUS 1 | |
| 59 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
| 60 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 61 | ||
| 62 | #elif defined(CONFIG_MPC8560) | |
| 63 | #define CONFIG_MAX_CPUS 1 | |
| 64 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
| 65 | ||
| 66 | #elif defined(CONFIG_MPC8568) | |
| 67 | #define CONFIG_MAX_CPUS 1 | |
| 68 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
| 69 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 70 | ||
| 71 | #elif defined(CONFIG_MPC8569) | |
| 72 | #define CONFIG_MAX_CPUS 1 | |
| 73 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
| 74 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 75 | ||
| 76 | #elif defined(CONFIG_MPC8572) | |
| 77 | #define CONFIG_MAX_CPUS 2 | |
| 78 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 79 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| eb0aff77 | 80 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
| 91671913 | 81 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
| 243be8e2 KG |
82 | |
| 83 | #elif defined(CONFIG_P1010) | |
| 84 | #define CONFIG_MAX_CPUS 1 | |
| 85 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 86 | #define CONFIG_TSECV2 | |
| 87 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 88 | ||
| 89 | #elif defined(CONFIG_P1011) | |
| 90 | #define CONFIG_MAX_CPUS 1 | |
| 91 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 92 | #define CONFIG_TSECV2 | |
| 93 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 94 | ||
| 95 | #elif defined(CONFIG_P1012) | |
| 96 | #define CONFIG_MAX_CPUS 1 | |
| 97 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 98 | #define CONFIG_TSECV2 | |
| 99 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 100 | ||
| 101 | #elif defined(CONFIG_P1013) | |
| 102 | #define CONFIG_MAX_CPUS 1 | |
| 103 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 104 | #define CONFIG_TSECV2 | |
| 105 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 2d7534a3 JY |
106 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 107 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 108 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
| 243be8e2 KG |
109 | |
| 110 | #elif defined(CONFIG_P1014) | |
| 111 | #define CONFIG_MAX_CPUS 1 | |
| 112 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 113 | #define CONFIG_TSECV2 | |
| 114 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 115 | ||
| 116 | #elif defined(CONFIG_P1020) | |
| 117 | #define CONFIG_MAX_CPUS 2 | |
| 118 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 119 | #define CONFIG_TSECV2 | |
| 120 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 121 | ||
| 122 | #elif defined(CONFIG_P1021) | |
| 123 | #define CONFIG_MAX_CPUS 2 | |
| 124 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 125 | #define CONFIG_TSECV2 | |
| 126 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 127 | ||
| 128 | #elif defined(CONFIG_P1022) | |
| 129 | #define CONFIG_MAX_CPUS 2 | |
| 130 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 131 | #define CONFIG_TSECV2 | |
| 132 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 2d7534a3 JY |
133 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 134 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 135 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
| 243be8e2 KG |
136 | |
| 137 | #elif defined(CONFIG_P2010) | |
| 138 | #define CONFIG_MAX_CPUS 1 | |
| 139 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 140 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 6e7f0bc0 | 141 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 5103a03a | 142 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 243be8e2 KG |
143 | |
| 144 | #elif defined(CONFIG_P2020) | |
| 145 | #define CONFIG_MAX_CPUS 2 | |
| 146 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 147 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 6e7f0bc0 | 148 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 5103a03a | 149 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 243be8e2 KG |
150 | |
| 151 | #elif defined(CONFIG_PPC_P2040) | |
| 152 | #define CONFIG_MAX_CPUS 4 | |
| 153 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
| 154 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 155 | ||
| 156 | #elif defined(CONFIG_PPC_P3041) | |
| 157 | #define CONFIG_MAX_CPUS 4 | |
| 158 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
| 159 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 160 | ||
| 161 | #elif defined(CONFIG_PPC_P4040) | |
| 162 | #define CONFIG_MAX_CPUS 4 | |
| 163 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
| 164 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 165 | ||
| 166 | #elif defined(CONFIG_PPC_P4080) | |
| 167 | #define CONFIG_MAX_CPUS 8 | |
| 168 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
| 169 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 170 | #define CONFIG_SYS_NUM_FMAN 2 | |
| 171 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
| 172 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
| 173 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
| 174 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
| 175 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 176 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 | |
| 177 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
| fa8d23c0 | 178 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
| 243be8e2 KG |
179 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 180 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 181 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
| 182 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 | |
| 183 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 | |
| 184 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 | |
| 185 | ||
| 186 | #elif defined(CONFIG_PPC_P5010) | |
| 187 | #define CONFIG_MAX_CPUS 1 | |
| 188 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
| 189 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 190 | ||
| 191 | #elif defined(CONFIG_PPC_P5020) | |
| 192 | #define CONFIG_MAX_CPUS 2 | |
| 193 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
| 194 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 195 | ||
| 196 | #else | |
| 197 | #error Processor type not defined for this platform | |
| 198 | #endif | |
| 199 | ||
| 200 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |