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243be8e2 KG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
22 | #define _ASM_MPC85xx_CONFIG_H_ | |
23 | ||
24 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
25 | ||
e46fedfe TT |
26 | #ifdef CONFIG_SYS_CCSRBAR_DEFAULT |
27 | #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." | |
28 | #endif | |
29 | ||
243be8e2 KG |
30 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
31 | #if defined(CONFIG_E500MC) | |
32 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
33 | #elif defined(CONFIG_E500) | |
34 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
35 | #endif | |
36 | ||
37 | #if defined(CONFIG_MPC8536) | |
38 | #define CONFIG_MAX_CPUS 1 | |
39 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
40 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 41 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 42 | |
d1a24f06 | 43 | #elif defined(CONFIG_MPC8540) |
243be8e2 KG |
44 | #define CONFIG_MAX_CPUS 1 |
45 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
e46fedfe | 46 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 47 | |
d1a24f06 | 48 | #elif defined(CONFIG_MPC8541) |
243be8e2 KG |
49 | #define CONFIG_MAX_CPUS 1 |
50 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
51 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 52 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
53 | |
54 | #elif defined(CONFIG_MPC8544) | |
55 | #define CONFIG_MAX_CPUS 1 | |
56 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
57 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 58 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
59 | |
60 | #elif defined(CONFIG_MPC8548) | |
61 | #define CONFIG_MAX_CPUS 1 | |
62 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
63 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 64 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
5ace2992 | 65 | #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 |
2b3a1cdd | 66 | #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
aada81de | 67 | #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
243be8e2 KG |
68 | |
69 | #elif defined(CONFIG_MPC8555) | |
70 | #define CONFIG_MAX_CPUS 1 | |
71 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
72 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 73 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
74 | |
75 | #elif defined(CONFIG_MPC8560) | |
76 | #define CONFIG_MAX_CPUS 1 | |
77 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
e46fedfe | 78 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
79 | |
80 | #elif defined(CONFIG_MPC8568) | |
81 | #define CONFIG_MAX_CPUS 1 | |
82 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
83 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
fdb4dad3 KG |
84 | #define QE_MURAM_SIZE 0x10000UL |
85 | #define MAX_QE_RISC 2 | |
86 | #define QE_NUM_OF_SNUM 28 | |
e46fedfe | 87 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
88 | |
89 | #elif defined(CONFIG_MPC8569) | |
90 | #define CONFIG_MAX_CPUS 1 | |
91 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
92 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
fdb4dad3 KG |
93 | #define QE_MURAM_SIZE 0x20000UL |
94 | #define MAX_QE_RISC 4 | |
95 | #define QE_NUM_OF_SNUM 46 | |
e46fedfe | 96 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
97 | |
98 | #elif defined(CONFIG_MPC8572) | |
99 | #define CONFIG_MAX_CPUS 2 | |
100 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
101 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 102 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
eb0aff77 | 103 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
91671913 | 104 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
243be8e2 KG |
105 | |
106 | #elif defined(CONFIG_P1010) | |
107 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 108 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 KG |
109 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
110 | #define CONFIG_TSECV2 | |
111 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
112 | #define CONFIG_FSL_SATA_V2 |
113 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
114 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
115 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
8f29084a | 116 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
1b719e66 | 117 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 118 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 119 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
bc6bbd6b | 120 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
243be8e2 | 121 | |
093cffbe | 122 | /* P1011 is single core version of P1020 */ |
243be8e2 KG |
123 | #elif defined(CONFIG_P1011) |
124 | #define CONFIG_MAX_CPUS 1 | |
125 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
126 | #define CONFIG_TSECV2 | |
b03a466d | 127 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 128 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 129 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
130 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
131 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
243be8e2 | 132 | |
093cffbe | 133 | /* P1012 is single core version of P1021 */ |
243be8e2 KG |
134 | #elif defined(CONFIG_P1012) |
135 | #define CONFIG_MAX_CPUS 1 | |
136 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
137 | #define CONFIG_TSECV2 | |
b03a466d | 138 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 139 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 140 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
141 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
142 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
143 | #define QE_MURAM_SIZE 0x6000UL |
144 | #define MAX_QE_RISC 1 | |
145 | #define QE_NUM_OF_SNUM 28 | |
243be8e2 | 146 | |
093cffbe | 147 | /* P1013 is single core version of P1022 */ |
243be8e2 KG |
148 | #elif defined(CONFIG_P1013) |
149 | #define CONFIG_MAX_CPUS 1 | |
150 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
151 | #define CONFIG_TSECV2 | |
152 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 153 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
154 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
155 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
156 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
243be8e2 KG |
157 | |
158 | #elif defined(CONFIG_P1014) | |
159 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 160 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 KG |
161 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
162 | #define CONFIG_TSECV2 | |
163 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
164 | #define CONFIG_FSL_SATA_V2 |
165 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
166 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
167 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
1b719e66 | 168 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 169 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 170 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
bc6bbd6b | 171 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
243be8e2 | 172 | |
093cffbe KG |
173 | /* P1015 is single core version of P1024 */ |
174 | #elif defined(CONFIG_P1015) | |
175 | #define CONFIG_MAX_CPUS 1 | |
176 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
177 | #define CONFIG_TSECV2 | |
178 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
179 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 180 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
181 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
182 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
183 | ||
184 | /* P1016 is single core version of P1025 */ | |
185 | #elif defined(CONFIG_P1016) | |
186 | #define CONFIG_MAX_CPUS 1 | |
187 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
188 | #define CONFIG_TSECV2 | |
189 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
190 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
191 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 | |
192 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
193 | #define QE_MURAM_SIZE 0x6000UL |
194 | #define MAX_QE_RISC 1 | |
195 | #define QE_NUM_OF_SNUM 28 | |
e46fedfe | 196 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
197 | |
198 | /* P1017 is single core version of P1023 */ | |
67a719da RZ |
199 | #elif defined(CONFIG_P1017) |
200 | #define CONFIG_MAX_CPUS 1 | |
201 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
202 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
203 | #define CONFIG_SYS_NUM_FMAN 1 | |
204 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
205 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
206 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 | |
207 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 208 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 209 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 210 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
67a719da | 211 | |
243be8e2 KG |
212 | #elif defined(CONFIG_P1020) |
213 | #define CONFIG_MAX_CPUS 2 | |
214 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
215 | #define CONFIG_TSECV2 | |
b03a466d | 216 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 217 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 218 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
219 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
220 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
243be8e2 KG |
221 | |
222 | #elif defined(CONFIG_P1021) | |
223 | #define CONFIG_MAX_CPUS 2 | |
224 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
225 | #define CONFIG_TSECV2 | |
b03a466d | 226 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 227 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 228 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
229 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
230 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
231 | #define QE_MURAM_SIZE 0x6000UL |
232 | #define MAX_QE_RISC 1 | |
233 | #define QE_NUM_OF_SNUM 28 | |
243be8e2 KG |
234 | |
235 | #elif defined(CONFIG_P1022) | |
236 | #define CONFIG_MAX_CPUS 2 | |
237 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
238 | #define CONFIG_TSECV2 | |
239 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 240 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
241 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
242 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
243 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
243be8e2 | 244 | |
67a719da RZ |
245 | #elif defined(CONFIG_P1023) |
246 | #define CONFIG_MAX_CPUS 2 | |
247 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
248 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
249 | #define CONFIG_SYS_NUM_FMAN 1 | |
250 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
251 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
252 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 | |
253 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 254 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 255 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 256 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
67a719da | 257 | |
093cffbe KG |
258 | /* P1024 is lower end variant of P1020 */ |
259 | #elif defined(CONFIG_P1024) | |
260 | #define CONFIG_MAX_CPUS 2 | |
261 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
262 | #define CONFIG_TSECV2 | |
263 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
264 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 265 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
266 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
267 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
268 | ||
269 | /* P1025 is lower end variant of P1021 */ | |
270 | #elif defined(CONFIG_P1025) | |
271 | #define CONFIG_MAX_CPUS 2 | |
272 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
273 | #define CONFIG_TSECV2 | |
274 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
275 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 276 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
277 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
278 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
279 | #define QE_MURAM_SIZE 0x6000UL |
280 | #define MAX_QE_RISC 1 | |
281 | #define QE_NUM_OF_SNUM 28 | |
093cffbe KG |
282 | |
283 | /* P2010 is single core version of P2020 */ | |
243be8e2 KG |
284 | #elif defined(CONFIG_P2010) |
285 | #define CONFIG_MAX_CPUS 1 | |
286 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
287 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 288 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 289 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 290 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
243be8e2 KG |
291 | |
292 | #elif defined(CONFIG_P2020) | |
293 | #define CONFIG_MAX_CPUS 2 | |
294 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
295 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 296 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 297 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 298 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
243be8e2 KG |
299 | |
300 | #elif defined(CONFIG_PPC_P2040) | |
301 | #define CONFIG_MAX_CPUS 4 | |
b5c8753f | 302 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
303 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
304 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
305 | #define CONFIG_SYS_NUM_FMAN 1 |
306 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
307 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
c657d898 | 308 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 309 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 310 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 311 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
312 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
313 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 314 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 315 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
43f082bb | 316 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
243be8e2 | 317 | |
1f97987a KG |
318 | #elif defined(CONFIG_PPC_P2041) |
319 | #define CONFIG_MAX_CPUS 4 | |
320 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
321 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
322 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
323 | #define CONFIG_SYS_NUM_FMAN 1 | |
324 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
325 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
326 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
327 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
328 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 | |
329 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
e46fedfe | 330 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
1f97987a KG |
331 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
332 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 333 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
1f97987a | 334 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
43f082bb | 335 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
1f97987a | 336 | |
243be8e2 KG |
337 | #elif defined(CONFIG_PPC_P3041) |
338 | #define CONFIG_MAX_CPUS 4 | |
b5c8753f | 339 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
340 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
341 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
342 | #define CONFIG_SYS_NUM_FMAN 1 |
343 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
344 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
345 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
c657d898 | 346 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 347 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 348 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 349 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
350 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
351 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 352 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 353 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
43f082bb | 354 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
243be8e2 | 355 | |
6d7b061a SL |
356 | #elif defined(CONFIG_PPC_P3060) |
357 | #define CONFIG_MAX_CPUS 8 | |
358 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 | |
359 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
360 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
361 | #define CONFIG_SYS_NUM_FMAN 2 | |
362 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
363 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
364 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
365 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
366 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
367 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
368 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
369 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 | |
43f082bb | 370 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
6d7b061a | 371 | |
243be8e2 KG |
372 | #elif defined(CONFIG_PPC_P4040) |
373 | #define CONFIG_MAX_CPUS 4 | |
b5c8753f | 374 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
243be8e2 KG |
375 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
376 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
c657d898 | 377 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 378 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
8f29084a | 379 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
e46fedfe | 380 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
43f082bb | 381 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
243be8e2 KG |
382 | |
383 | #elif defined(CONFIG_PPC_P4080) | |
384 | #define CONFIG_MAX_CPUS 8 | |
b5c8753f | 385 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
243be8e2 KG |
386 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
387 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
388 | #define CONFIG_SYS_NUM_FMAN 2 | |
389 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
390 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
391 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
392 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
393 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
c657d898 | 394 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 395 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
8f29084a | 396 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
e46fedfe | 397 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
243be8e2 KG |
398 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
399 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
fa8d23c0 | 400 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
243be8e2 KG |
401 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
402 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
403 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
404 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 | |
405 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 | |
406 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 | |
df8af0b4 | 407 | #define CONFIG_SYS_P4080_ERRATUM_SERDES9 |
d90fdba6 | 408 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
da30b9fd | 409 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
43f082bb | 410 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
243be8e2 | 411 | |
093cffbe | 412 | /* P5010 is single core version of P5020 */ |
243be8e2 KG |
413 | #elif defined(CONFIG_PPC_P5010) |
414 | #define CONFIG_MAX_CPUS 1 | |
b5c8753f | 415 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
416 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
417 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
418 | #define CONFIG_SYS_NUM_FMAN 1 |
419 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
420 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
421 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
c657d898 | 422 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 423 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 424 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 425 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
426 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
427 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 428 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 429 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
243be8e2 KG |
430 | |
431 | #elif defined(CONFIG_PPC_P5020) | |
432 | #define CONFIG_MAX_CPUS 2 | |
b5c8753f | 433 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
434 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
435 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
436 | #define CONFIG_SYS_NUM_FMAN 1 |
437 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
438 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
439 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
c657d898 | 440 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 441 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 442 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 443 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
444 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
445 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 446 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 447 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
243be8e2 KG |
448 | |
449 | #else | |
450 | #error Processor type not defined for this platform | |
451 | #endif | |
452 | ||
e46fedfe TT |
453 | #ifndef CONFIG_SYS_CCSRBAR_DEFAULT |
454 | #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." | |
455 | #endif | |
456 | ||
243be8e2 | 457 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |