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243be8e2 | 1 | /* |
19a8dbdc | 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
243be8e2 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
243be8e2 KG |
5 | */ |
6 | ||
7 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
8 | #define _ASM_MPC85xx_CONFIG_H_ | |
9 | ||
10 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
11 | ||
e46fedfe TT |
12 | #ifdef CONFIG_SYS_CCSRBAR_DEFAULT |
13 | #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." | |
14 | #endif | |
15 | ||
2a5fcb83 YS |
16 | /* |
17 | * This macro should be removed when we no longer care about backwards | |
18 | * compatibility with older operating systems. | |
19 | */ | |
20 | #define CONFIG_PPC_SPINTABLE_COMPATIBLE | |
21 | ||
57495e4e | 22 | #define FSL_DDR_VER_4_7 47 |
1d384eca | 23 | #define FSL_DDR_VER_5_0 50 |
57495e4e | 24 | |
243be8e2 KG |
25 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
26 | #if defined(CONFIG_E500MC) | |
27 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
28 | #elif defined(CONFIG_E500) | |
29 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
30 | #endif | |
31 | ||
32 | #if defined(CONFIG_MPC8536) | |
33 | #define CONFIG_MAX_CPUS 1 | |
34 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 35 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 |
243be8e2 | 36 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 37 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
954a1a47 | 38 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 39 | |
d1a24f06 | 40 | #elif defined(CONFIG_MPC8540) |
243be8e2 KG |
41 | #define CONFIG_MAX_CPUS 1 |
42 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 43 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
e46fedfe | 44 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 45 | |
d1a24f06 | 46 | #elif defined(CONFIG_MPC8541) |
243be8e2 KG |
47 | #define CONFIG_MAX_CPUS 1 |
48 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 49 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
243be8e2 | 50 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 51 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
52 | |
53 | #elif defined(CONFIG_MPC8544) | |
54 | #define CONFIG_MAX_CPUS 1 | |
55 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 56 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
e4879afb | 57 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 58 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 59 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
954a1a47 | 60 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
61 | |
62 | #elif defined(CONFIG_MPC8548) | |
63 | #define CONFIG_MAX_CPUS 1 | |
64 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 65 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
e4879afb | 66 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 67 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 68 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
5ace2992 | 69 | #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 |
2b3a1cdd | 70 | #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
aada81de | 71 | #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
7d67ed58 LG |
72 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
73 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
74 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
75 | #define CONFIG_SYS_FSL_RMU | |
76 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 77 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
78 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
79 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 | |
243be8e2 KG |
80 | |
81 | #elif defined(CONFIG_MPC8555) | |
82 | #define CONFIG_MAX_CPUS 1 | |
83 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 84 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
243be8e2 | 85 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 86 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
87 | |
88 | #elif defined(CONFIG_MPC8560) | |
89 | #define CONFIG_MAX_CPUS 1 | |
90 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 91 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
e46fedfe | 92 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
93 | |
94 | #elif defined(CONFIG_MPC8568) | |
95 | #define CONFIG_MAX_CPUS 1 | |
96 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 97 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
243be8e2 | 98 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
fdb4dad3 KG |
99 | #define QE_MURAM_SIZE 0x10000UL |
100 | #define MAX_QE_RISC 2 | |
101 | #define QE_NUM_OF_SNUM 28 | |
e46fedfe | 102 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
103 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
104 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
105 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
106 | #define CONFIG_SYS_FSL_RMU | |
107 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 KG |
108 | |
109 | #elif defined(CONFIG_MPC8569) | |
110 | #define CONFIG_MAX_CPUS 1 | |
111 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
112 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
fdb4dad3 KG |
113 | #define QE_MURAM_SIZE 0x20000UL |
114 | #define MAX_QE_RISC 4 | |
115 | #define QE_NUM_OF_SNUM 46 | |
e46fedfe | 116 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
117 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
118 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
119 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
120 | #define CONFIG_SYS_FSL_RMU | |
121 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 122 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
123 | |
124 | #elif defined(CONFIG_MPC8572) | |
125 | #define CONFIG_MAX_CPUS 2 | |
126 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 127 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 128 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 129 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
eb0aff77 | 130 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
91671913 | 131 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
954a1a47 | 132 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
133 | |
134 | #elif defined(CONFIG_P1010) | |
135 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 136 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 137 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 138 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
139 | #define CONFIG_TSECV2 |
140 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
141 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
142 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 143 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
362ee04b | 144 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
1fbf3483 | 145 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
8f29084a | 146 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
1b719e66 | 147 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 148 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 149 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
424bf942 | 150 | #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 |
bc6bbd6b | 151 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
954a1a47 | 152 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
153 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
154 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 | |
243be8e2 | 155 | |
093cffbe | 156 | /* P1011 is single core version of P1020 */ |
243be8e2 KG |
157 | #elif defined(CONFIG_P1011) |
158 | #define CONFIG_MAX_CPUS 1 | |
159 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 160 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 161 | #define CONFIG_TSECV2 |
b03a466d | 162 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 163 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
f1810d85 | 164 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 165 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
166 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
167 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
954a1a47 | 168 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 169 | |
093cffbe | 170 | /* P1012 is single core version of P1021 */ |
243be8e2 KG |
171 | #elif defined(CONFIG_P1012) |
172 | #define CONFIG_MAX_CPUS 1 | |
173 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 174 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 175 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 176 | #define CONFIG_TSECV2 |
b03a466d | 177 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 178 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 179 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
180 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
181 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
182 | #define QE_MURAM_SIZE 0x6000UL |
183 | #define MAX_QE_RISC 1 | |
184 | #define QE_NUM_OF_SNUM 28 | |
954a1a47 | 185 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 186 | |
093cffbe | 187 | /* P1013 is single core version of P1022 */ |
243be8e2 KG |
188 | #elif defined(CONFIG_P1013) |
189 | #define CONFIG_MAX_CPUS 1 | |
190 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 191 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 192 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
193 | #define CONFIG_TSECV2 |
194 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 195 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
196 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
197 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
198 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
954a1a47 | 199 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
200 | |
201 | #elif defined(CONFIG_P1014) | |
202 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 203 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 204 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 205 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
206 | #define CONFIG_TSECV2 |
207 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
208 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
209 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 210 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
1fbf3483 | 211 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
1b719e66 | 212 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 213 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 214 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
bc6bbd6b | 215 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
243be8e2 | 216 | |
093cffbe | 217 | /* P1017 is single core version of P1023 */ |
67a719da RZ |
218 | #elif defined(CONFIG_P1017) |
219 | #define CONFIG_MAX_CPUS 1 | |
220 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
221 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
222 | #define CONFIG_SYS_NUM_FMAN 1 | |
223 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
224 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 225 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
226 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
227 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 228 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 229 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 230 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
954a1a47 | 231 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
67a719da | 232 | |
243be8e2 KG |
233 | #elif defined(CONFIG_P1020) |
234 | #define CONFIG_MAX_CPUS 2 | |
235 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 236 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 237 | #define CONFIG_TSECV2 |
b03a466d | 238 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 239 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 240 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
241 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
242 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
954a1a47 | 243 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 244 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
243be8e2 KG |
245 | |
246 | #elif defined(CONFIG_P1021) | |
247 | #define CONFIG_MAX_CPUS 2 | |
248 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 249 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 250 | #define CONFIG_TSECV2 |
b03a466d | 251 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 252 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 253 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
254 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
255 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
256 | #define QE_MURAM_SIZE 0x6000UL |
257 | #define MAX_QE_RISC 1 | |
258 | #define QE_NUM_OF_SNUM 28 | |
954a1a47 | 259 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 260 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
243be8e2 KG |
261 | |
262 | #elif defined(CONFIG_P1022) | |
263 | #define CONFIG_MAX_CPUS 2 | |
264 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 265 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
266 | #define CONFIG_TSECV2 |
267 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
f1810d85 | 268 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 269 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
270 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
271 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
272 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
954a1a47 | 273 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 274 | |
67a719da RZ |
275 | #elif defined(CONFIG_P1023) |
276 | #define CONFIG_MAX_CPUS 2 | |
277 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
278 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
279 | #define CONFIG_SYS_NUM_FMAN 1 | |
280 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
281 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 282 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
283 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
284 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 285 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 286 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 287 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
954a1a47 | 288 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
289 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
290 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
67a719da | 291 | |
093cffbe KG |
292 | /* P1024 is lower end variant of P1020 */ |
293 | #elif defined(CONFIG_P1024) | |
294 | #define CONFIG_MAX_CPUS 2 | |
295 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 296 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
297 | #define CONFIG_TSECV2 |
298 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
299 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
f1810d85 | 300 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 301 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
302 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
303 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
954a1a47 | 304 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
305 | |
306 | /* P1025 is lower end variant of P1021 */ | |
307 | #elif defined(CONFIG_P1025) | |
308 | #define CONFIG_MAX_CPUS 2 | |
309 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 310 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 311 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
312 | #define CONFIG_TSECV2 |
313 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
314 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 315 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
316 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
317 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
318 | #define QE_MURAM_SIZE 0x6000UL |
319 | #define MAX_QE_RISC 1 | |
320 | #define QE_NUM_OF_SNUM 28 | |
954a1a47 | 321 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
322 | |
323 | /* P2010 is single core version of P2020 */ | |
243be8e2 KG |
324 | #elif defined(CONFIG_P2010) |
325 | #define CONFIG_MAX_CPUS 1 | |
326 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 327 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 328 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
f1810d85 | 329 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
e46fedfe | 330 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 331 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 332 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
954a1a47 | 333 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
334 | |
335 | #elif defined(CONFIG_P2020) | |
336 | #define CONFIG_MAX_CPUS 2 | |
337 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 338 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 339 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 340 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 341 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 342 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
7d67ed58 LG |
343 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
344 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
345 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
346 | #define CONFIG_SYS_FSL_RMU | |
347 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 348 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 349 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
3e978f5d | 350 | #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ |
d1001e3f | 351 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 352 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
1f97987a KG |
353 | #define CONFIG_MAX_CPUS 4 |
354 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
355 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
356 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
357 | #define CONFIG_SYS_NUM_FMAN 1 | |
358 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
359 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
360 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 361 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
1f97987a KG |
362 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
363 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 | |
364 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
e46fedfe | 365 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
1f97987a KG |
366 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
367 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 368 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
1f97987a | 369 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5e23ab0a | 370 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 371 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 372 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 373 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 374 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
375 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
376 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
377 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
378 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
379 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
380 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
381 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 382 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 383 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
9c3f77eb CL |
384 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
385 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
1f97987a | 386 | |
243be8e2 | 387 | #elif defined(CONFIG_PPC_P3041) |
d1001e3f | 388 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 389 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 390 | #define CONFIG_MAX_CPUS 4 |
b5c8753f | 391 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
392 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
393 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
394 | #define CONFIG_SYS_NUM_FMAN 1 |
395 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
396 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
397 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
c657d898 | 398 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 399 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 400 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 401 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
402 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
403 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 404 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
f1810d85 | 405 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
30009766 | 406 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
57125f22 | 407 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 408 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 409 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 410 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 411 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
412 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
413 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
414 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
415 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
416 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
417 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
418 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 419 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 420 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d217a9ad | 421 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb CL |
422 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
423 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 | |
243be8e2 | 424 | |
3e978f5d | 425 | #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ |
d1001e3f | 426 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 427 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 428 | #define CONFIG_MAX_CPUS 8 |
b5c8753f | 429 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
243be8e2 KG |
430 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
431 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
432 | #define CONFIG_SYS_NUM_FMAN 2 | |
433 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
434 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
435 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
436 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
437 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
f1810d85 | 438 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 439 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 440 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
8f29084a | 441 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
e46fedfe | 442 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
243be8e2 KG |
443 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
444 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
fa8d23c0 | 445 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
243be8e2 KG |
446 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
447 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
448 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
4e0be34a | 449 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 |
243be8e2 | 450 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 |
5e23ab0a | 451 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
243be8e2 | 452 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 |
df8af0b4 | 453 | #define CONFIG_SYS_P4080_ERRATUM_SERDES9 |
d90fdba6 | 454 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
da30b9fd | 455 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
43f082bb | 456 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
4108508a | 457 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
458 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
459 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
460 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
461 | #define CONFIG_SYS_FSL_RMU | |
462 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
33eee330 SW |
463 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
464 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 | |
465 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 | |
d59c5570 | 466 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 467 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d607b968 | 468 | #define CONFIG_SYS_FSL_ERRATUM_A004580 |
c0a4e6b8 | 469 | #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 |
d217a9ad | 470 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb CL |
471 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
472 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 | |
243be8e2 | 473 | |
3e978f5d | 474 | #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ |
ffd06e02 | 475 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
d1001e3f | 476 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 477 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 478 | #define CONFIG_MAX_CPUS 2 |
b5c8753f | 479 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
480 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
481 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
482 | #define CONFIG_SYS_NUM_FMAN 1 |
483 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
484 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
485 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
f1810d85 | 486 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 487 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 488 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 489 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 490 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
491 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
492 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 493 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 494 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
99d7b0a4 | 495 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
e22be77a | 496 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 497 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
498 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
499 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
500 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
501 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
502 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
503 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 | |
d59c5570 | 504 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
9c3f77eb CL |
505 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
506 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 | |
243be8e2 | 507 | |
4905443f | 508 | #elif defined(CONFIG_PPC_P5040) |
1956e431 | 509 | #define CONFIG_SYS_PPC64 |
4905443f | 510 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 511 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
4905443f TT |
512 | #define CONFIG_MAX_CPUS 4 |
513 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 | |
514 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
515 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
516 | #define CONFIG_SYS_NUM_FMAN 2 | |
517 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
518 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
519 | #define CONFIG_SYS_NUM_FM2_DTSEC 5 | |
520 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
521 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
f1810d85 | 522 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
4905443f TT |
523 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
524 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
525 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
526 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
527 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
528 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
529 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
530 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
99d7b0a4 | 531 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
4905443f TT |
532 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
533 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 | |
534 | #define CONFIG_SYS_FSL_ERRATUM_A004699 | |
4905443f TT |
535 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
536 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
537 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d217a9ad | 538 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
4905443f | 539 | |
19a8dbdc PK |
540 | #elif defined(CONFIG_BSC9131) |
541 | #define CONFIG_MAX_CPUS 1 | |
542 | #define CONFIG_FSL_SDHC_V2_3 | |
543 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
544 | #define CONFIG_TSECV2 | |
545 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
546 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 547 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
765b0bdb PJ |
548 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 |
549 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
362ee04b | 550 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
19a8dbdc PK |
551 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
552 | #define CONFIG_NAND_FSL_IFC | |
19a8dbdc | 553 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
954a1a47 | 554 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
19a8dbdc | 555 | |
35fe948e PK |
556 | #elif defined(CONFIG_BSC9132) |
557 | #define CONFIG_MAX_CPUS 2 | |
558 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 | |
559 | #define CONFIG_FSL_SDHC_V2_3 | |
560 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
561 | #define CONFIG_TSECV2 | |
562 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
563 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
f1810d85 | 564 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
64501c66 PJ |
565 | #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 |
566 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 | |
567 | #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 | |
568 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
061ffeda | 569 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
35fe948e PK |
570 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
571 | #define CONFIG_NAND_FSL_IFC | |
35fe948e PK |
572 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
573 | #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK | |
574 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
954a1a47 | 575 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
576 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
577 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
35fe948e | 578 | |
3d2972fe YS |
579 | #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) |
580 | #define CONFIG_E6500 | |
ffd06e02 | 581 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
9e758758 YS |
582 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
583 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 584 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
9e758758 | 585 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
3d2972fe | 586 | #ifdef CONFIG_PPC_T4240 |
9e758758 | 587 | #define CONFIG_MAX_CPUS 12 |
ce746fe0 | 588 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } |
9e758758 YS |
589 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 |
590 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
591 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 | |
592 | #define CONFIG_SYS_NUM_FM2_10GEC 2 | |
593 | #define CONFIG_NUM_DDR_CONTROLLERS 3 | |
3d2972fe | 594 | #else |
b6240846 | 595 | #define CONFIG_MAX_CPUS 8 |
ce746fe0 | 596 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } |
3d2972fe YS |
597 | #define CONFIG_SYS_NUM_FM1_DTSEC 7 |
598 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
599 | #define CONFIG_SYS_NUM_FM2_DTSEC 7 | |
600 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
601 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
602 | #endif | |
b6240846 YS |
603 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 |
604 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
a4c955bc PK |
605 | #define CONFIG_SYS_FSL_SRDS_1 |
606 | #define CONFIG_SYS_FSL_SRDS_2 | |
b6240846 YS |
607 | #define CONFIG_SYS_FSL_SRDS_3 |
608 | #define CONFIG_SYS_FSL_SRDS_4 | |
609 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
610 | #define CONFIG_SYS_NUM_FMAN 2 | |
f1810d85 | 611 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 | 612 | #define CONFIG_SYS_PME_CLK 0 |
b6240846 | 613 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 614 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
b6240846 | 615 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
616 | #define CONFIG_SYS_FM1_CLK 3 |
617 | #define CONFIG_SYS_FM2_CLK 3 | |
b6240846 YS |
618 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
619 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
620 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
621 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
622 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
623 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
08047937 | 624 | #define CONFIG_SYS_FSL_SRIO_LIODN |
b6240846 YS |
625 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
626 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
627 | #define CONFIG_SYS_FSL_ERRATUM_A004468 | |
628 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
629 | #define CONFIG_SYS_FSL_ERRATUM_A005871 | |
133fbfa9 | 630 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
82125192 | 631 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
b6240846 YS |
632 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
633 | #define CONFIG_SYS_FSL_PCI_VER_3_X | |
634 | ||
8fa0102b PA |
635 | #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) |
636 | #define CONFIG_E6500 | |
e1dbdd81 PA |
637 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
638 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
639 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
640 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
e1dbdd81 | 641 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
a4c955bc PK |
642 | #define CONFIG_SYS_FSL_SRDS_1 |
643 | #define CONFIG_SYS_FSL_SRDS_2 | |
e1dbdd81 PA |
644 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
645 | #define CONFIG_SYS_NUM_FMAN 1 | |
f1810d85 | 646 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
ce746fe0 | 647 | #define CONFIG_SYS_FM1_CLK 0 |
e1dbdd81 | 648 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 649 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
e1dbdd81 PA |
650 | #define CONFIG_SYS_FMAN_V3 |
651 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 | |
652 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
653 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
654 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
655 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
04feb57f | 656 | #define CONFIG_SYS_FSL_ERRATUM_A005871 |
133fbfa9 | 657 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
82125192 | 658 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
e1dbdd81 PA |
659 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
660 | ||
8fa0102b | 661 | #ifdef CONFIG_PPC_B4860 |
f6981439 | 662 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
d2404141 YS |
663 | #define CONFIG_MAX_CPUS 4 |
664 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 | |
ce746fe0 | 665 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } |
d2404141 YS |
666 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
667 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
e394ceb1 | 668 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
f1810d85 | 669 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
d2404141 YS |
670 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
671 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
672 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
32f38ee3 | 673 | #define CONFIG_SYS_FSL_SRIO_LIODN |
8fa0102b PA |
674 | #else |
675 | #define CONFIG_MAX_CPUS 2 | |
676 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 | |
677 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 | |
ce746fe0 | 678 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } |
8fa0102b PA |
679 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 |
680 | #define CONFIG_SYS_NUM_FM1_10GEC 0 | |
681 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
682 | #endif | |
d2404141 | 683 | |
2967af68 PJ |
684 | #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ |
685 | defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) | |
5f208d11 YS |
686 | #define CONFIG_E5500 |
687 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
688 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 689 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 |
5f208d11 | 690 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
1d384eca | 691 | #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) |
5f208d11 | 692 | #define CONFIG_MAX_CPUS 4 |
1d384eca PK |
693 | #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) |
694 | #define CONFIG_MAX_CPUS 2 | |
695 | #endif | |
696 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
ce746fe0 PK |
697 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } |
698 | #define CONFIG_SYS_SDHC_CLOCK 0 | |
5f208d11 | 699 | #define CONFIG_SYS_FSL_NUM_LAWS 16 |
1d384eca PK |
700 | #define CONFIG_SYS_FSL_SRDS_1 |
701 | #define CONFIG_SYS_FSL_SEC_COMPAT 5 | |
5f208d11 YS |
702 | #define CONFIG_SYS_NUM_FMAN 1 |
703 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
704 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 705 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 PK |
706 | #define CONFIG_PME_PLAT_CLK_DIV 2 |
707 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
1d384eca PK |
708 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
709 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
5f208d11 | 710 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
711 | #define CONFIG_FM_PLAT_CLK_DIV 1 |
712 | #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV | |
1d384eca | 713 | #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 |
e03c76c3 | 714 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
5f208d11 | 715 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" |
5f208d11 YS |
716 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
717 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
718 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
719 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
720 | ||
629d6b32 SL |
721 | #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) |
722 | #define CONFIG_E6500 | |
723 | #define CONFIG_SYS_PPC64 /* 64-bit core */ | |
724 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
725 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
726 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 | |
727 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
728 | #define CONFIG_SYS_FSL_QMAN_V3 | |
729 | #define CONFIG_MAX_CPUS 4 | |
730 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
731 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
732 | #define CONFIG_SYS_NUM_FMAN 1 | |
733 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } | |
734 | #define CONFIG_SYS_FSL_SRDS_1 | |
735 | #define CONFIG_SYS_FSL_PCI_VER_3_X | |
736 | #if defined(CONFIG_PPC_T2080) | |
737 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 | |
738 | #define CONFIG_SYS_NUM_FM1_10GEC 4 | |
739 | #define CONFIG_SYS_FSL_SRDS_2 | |
740 | #define CONFIG_SYS_FSL_SRIO_LIODN | |
741 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
742 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
743 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
744 | #elif defined(CONFIG_PPC_T2081) | |
745 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 | |
746 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
747 | #endif | |
748 | #define CONFIG_SYS_FSL_NUM_USB_CTRLS 2 | |
749 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
750 | #define CONFIG_PME_PLAT_CLK_DIV 1 | |
751 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
752 | #define CONFIG_SYS_FM1_CLK 0 | |
753 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 | |
754 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
755 | #define CONFIG_SYS_FMAN_V3 | |
756 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
757 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
758 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
759 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE | |
760 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
761 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
762 | #define CONFIG_SYS_FSL_SFP_VER_3_0 | |
763 | #define CONFIG_SYS_FSL_ISBC_VER 2 | |
764 | ||
3b75e982 MH |
765 | #elif defined(CONFIG_PPC_C29X) |
766 | #define CONFIG_MAX_CPUS 1 | |
767 | #define CONFIG_FSL_SDHC_V2_3 | |
768 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
769 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 | |
770 | #define CONFIG_TSECV2_1 | |
771 | #define CONFIG_SYS_FSL_SEC_COMPAT 6 | |
772 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
773 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
774 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
775 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
954a1a47 | 776 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
3b75e982 | 777 | |
243be8e2 KG |
778 | #else |
779 | #error Processor type not defined for this platform | |
780 | #endif | |
781 | ||
e46fedfe TT |
782 | #ifndef CONFIG_SYS_CCSRBAR_DEFAULT |
783 | #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." | |
784 | #endif | |
785 | ||
f6981439 YS |
786 | #ifdef CONFIG_E6500 |
787 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 | |
788 | #else | |
789 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 | |
790 | #endif | |
791 | ||
5614e71b YS |
792 | #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ |
793 | !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ | |
794 | !defined(CONFIG_SYS_FSL_DDRC_GEN3) | |
795 | #define CONFIG_SYS_FSL_DDRC_GEN3 | |
796 | #endif | |
797 | ||
243be8e2 | 798 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |