projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 243be8e2 KG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License as | |
| 6 | * published by the Free Software Foundation; either version 2 of | |
| 7 | * the License, or (at your option) any later version. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program; if not, write to the Free Software | |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 17 | * MA 02111-1307 USA | |
| 18 | * | |
| 19 | */ | |
| 20 | ||
| 21 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
| 22 | #define _ASM_MPC85xx_CONFIG_H_ | |
| 23 | ||
| 24 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
| 25 | ||
| e46fedfe TT |
26 | #ifdef CONFIG_SYS_CCSRBAR_DEFAULT |
| 27 | #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." | |
| 28 | #endif | |
| 29 | ||
| 243be8e2 KG |
30 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
| 31 | #if defined(CONFIG_E500MC) | |
| 32 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
| 33 | #elif defined(CONFIG_E500) | |
| 34 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
| 35 | #endif | |
| 36 | ||
| 37 | #if defined(CONFIG_MPC8536) | |
| 38 | #define CONFIG_MAX_CPUS 1 | |
| 39 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 40 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 41 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 243be8e2 | 42 | |
| d1a24f06 | 43 | #elif defined(CONFIG_MPC8540) |
| 243be8e2 KG |
44 | #define CONFIG_MAX_CPUS 1 |
| 45 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
| e46fedfe | 46 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 243be8e2 | 47 | |
| d1a24f06 | 48 | #elif defined(CONFIG_MPC8541) |
| 243be8e2 KG |
49 | #define CONFIG_MAX_CPUS 1 |
| 50 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
| 51 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 52 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 243be8e2 KG |
53 | |
| 54 | #elif defined(CONFIG_MPC8544) | |
| 55 | #define CONFIG_MAX_CPUS 1 | |
| 56 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
| 57 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 58 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 243be8e2 KG |
59 | |
| 60 | #elif defined(CONFIG_MPC8548) | |
| 61 | #define CONFIG_MAX_CPUS 1 | |
| 62 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
| 63 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 64 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 5ace2992 | 65 | #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 |
| 243be8e2 KG |
66 | |
| 67 | #elif defined(CONFIG_MPC8555) | |
| 68 | #define CONFIG_MAX_CPUS 1 | |
| 69 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
| 70 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 71 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 243be8e2 KG |
72 | |
| 73 | #elif defined(CONFIG_MPC8560) | |
| 74 | #define CONFIG_MAX_CPUS 1 | |
| 75 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
| e46fedfe | 76 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 243be8e2 KG |
77 | |
| 78 | #elif defined(CONFIG_MPC8568) | |
| 79 | #define CONFIG_MAX_CPUS 1 | |
| 80 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
| 81 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| fdb4dad3 KG |
82 | #define QE_MURAM_SIZE 0x10000UL |
| 83 | #define MAX_QE_RISC 2 | |
| 84 | #define QE_NUM_OF_SNUM 28 | |
| e46fedfe | 85 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 243be8e2 KG |
86 | |
| 87 | #elif defined(CONFIG_MPC8569) | |
| 88 | #define CONFIG_MAX_CPUS 1 | |
| 89 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
| 90 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| fdb4dad3 KG |
91 | #define QE_MURAM_SIZE 0x20000UL |
| 92 | #define MAX_QE_RISC 4 | |
| 93 | #define QE_NUM_OF_SNUM 46 | |
| e46fedfe | 94 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 243be8e2 KG |
95 | |
| 96 | #elif defined(CONFIG_MPC8572) | |
| 97 | #define CONFIG_MAX_CPUS 2 | |
| 98 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 99 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 100 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| eb0aff77 | 101 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
| 91671913 | 102 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
| 243be8e2 KG |
103 | |
| 104 | #elif defined(CONFIG_P1010) | |
| 105 | #define CONFIG_MAX_CPUS 1 | |
| 32c8cfb2 | 106 | #define CONFIG_FSL_SDHC_V2_3 |
| 243be8e2 KG |
107 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 108 | #define CONFIG_TSECV2 | |
| 109 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 1fbf3483 PA |
110 | #define CONFIG_FSL_SATA_V2 |
| 111 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 112 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 113 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
| 8f29084a | 114 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
| 1b719e66 | 115 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 42aee64b | 116 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
| fb855f43 | 117 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
| bc6bbd6b | 118 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
| 243be8e2 | 119 | |
| 093cffbe | 120 | /* P1011 is single core version of P1020 */ |
| 243be8e2 KG |
121 | #elif defined(CONFIG_P1011) |
| 122 | #define CONFIG_MAX_CPUS 1 | |
| 123 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 124 | #define CONFIG_TSECV2 | |
| b03a466d | 125 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
| 243be8e2 | 126 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| e46fedfe | 127 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 093cffbe KG |
128 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 129 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 243be8e2 | 130 | |
| 093cffbe | 131 | /* P1012 is single core version of P1021 */ |
| 243be8e2 KG |
132 | #elif defined(CONFIG_P1012) |
| 133 | #define CONFIG_MAX_CPUS 1 | |
| 134 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 135 | #define CONFIG_TSECV2 | |
| b03a466d | 136 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
| 243be8e2 | 137 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| e46fedfe | 138 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 093cffbe KG |
139 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 140 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| a52d2f81 HW |
141 | #define QE_MURAM_SIZE 0x6000UL |
| 142 | #define MAX_QE_RISC 1 | |
| 143 | #define QE_NUM_OF_SNUM 28 | |
| 243be8e2 | 144 | |
| 093cffbe | 145 | /* P1013 is single core version of P1022 */ |
| 243be8e2 KG |
146 | #elif defined(CONFIG_P1013) |
| 147 | #define CONFIG_MAX_CPUS 1 | |
| 148 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 149 | #define CONFIG_TSECV2 | |
| 150 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 151 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 2d7534a3 JY |
152 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 153 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 154 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
| 243be8e2 KG |
155 | |
| 156 | #elif defined(CONFIG_P1014) | |
| 157 | #define CONFIG_MAX_CPUS 1 | |
| 32c8cfb2 | 158 | #define CONFIG_FSL_SDHC_V2_3 |
| 243be8e2 KG |
159 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
| 160 | #define CONFIG_TSECV2 | |
| 161 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 1fbf3483 PA |
162 | #define CONFIG_FSL_SATA_V2 |
| 163 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 164 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 165 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
| 1b719e66 | 166 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 42aee64b | 167 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
| fb855f43 | 168 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
| bc6bbd6b | 169 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
| 243be8e2 | 170 | |
| 093cffbe KG |
171 | /* P1015 is single core version of P1024 */ |
| 172 | #elif defined(CONFIG_P1015) | |
| 173 | #define CONFIG_MAX_CPUS 1 | |
| 174 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 175 | #define CONFIG_TSECV2 | |
| 176 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
| 177 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 178 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 093cffbe KG |
179 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 180 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 181 | ||
| 182 | /* P1016 is single core version of P1025 */ | |
| 183 | #elif defined(CONFIG_P1016) | |
| 184 | #define CONFIG_MAX_CPUS 1 | |
| 185 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 186 | #define CONFIG_TSECV2 | |
| 187 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
| 188 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| 189 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 | |
| 190 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| a52d2f81 HW |
191 | #define QE_MURAM_SIZE 0x6000UL |
| 192 | #define MAX_QE_RISC 1 | |
| 193 | #define QE_NUM_OF_SNUM 28 | |
| e46fedfe | 194 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 093cffbe KG |
195 | |
| 196 | /* P1017 is single core version of P1023 */ | |
| 67a719da RZ |
197 | #elif defined(CONFIG_P1017) |
| 198 | #define CONFIG_MAX_CPUS 1 | |
| 199 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 200 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 201 | #define CONFIG_SYS_NUM_FMAN 1 | |
| 202 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
| 203 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 204 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 | |
| 205 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
| c657d898 | 206 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
| 8f29084a | 207 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
| e46fedfe | 208 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
| 67a719da | 209 | |
| 243be8e2 KG |
210 | #elif defined(CONFIG_P1020) |
| 211 | #define CONFIG_MAX_CPUS 2 | |
| 212 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 213 | #define CONFIG_TSECV2 | |
| b03a466d | 214 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
| 243be8e2 | 215 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| e46fedfe | 216 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 093cffbe KG |
217 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 218 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 243be8e2 KG |
219 | |
| 220 | #elif defined(CONFIG_P1021) | |
| 221 | #define CONFIG_MAX_CPUS 2 | |
| 222 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 223 | #define CONFIG_TSECV2 | |
| b03a466d | 224 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
| 243be8e2 | 225 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
| e46fedfe | 226 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 093cffbe KG |
227 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 228 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| a52d2f81 HW |
229 | #define QE_MURAM_SIZE 0x6000UL |
| 230 | #define MAX_QE_RISC 1 | |
| 231 | #define QE_NUM_OF_SNUM 28 | |
| 243be8e2 KG |
232 | |
| 233 | #elif defined(CONFIG_P1022) | |
| 234 | #define CONFIG_MAX_CPUS 2 | |
| 235 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 236 | #define CONFIG_TSECV2 | |
| 237 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 238 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 2d7534a3 JY |
239 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 240 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 241 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
| 243be8e2 | 242 | |
| 67a719da RZ |
243 | #elif defined(CONFIG_P1023) |
| 244 | #define CONFIG_MAX_CPUS 2 | |
| 245 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 246 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 247 | #define CONFIG_SYS_NUM_FMAN 1 | |
| 248 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
| 249 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 250 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 | |
| 251 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
| c657d898 | 252 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
| 8f29084a | 253 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
| e46fedfe | 254 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
| 67a719da | 255 | |
| 093cffbe KG |
256 | /* P1024 is lower end variant of P1020 */ |
| 257 | #elif defined(CONFIG_P1024) | |
| 258 | #define CONFIG_MAX_CPUS 2 | |
| 259 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 260 | #define CONFIG_TSECV2 | |
| 261 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
| 262 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 263 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 093cffbe KG |
264 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 265 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 266 | ||
| 267 | /* P1025 is lower end variant of P1021 */ | |
| 268 | #elif defined(CONFIG_P1025) | |
| 269 | #define CONFIG_MAX_CPUS 2 | |
| 270 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 271 | #define CONFIG_TSECV2 | |
| 272 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
| 273 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 274 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 093cffbe KG |
275 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 276 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| a52d2f81 HW |
277 | #define QE_MURAM_SIZE 0x6000UL |
| 278 | #define MAX_QE_RISC 1 | |
| 279 | #define QE_NUM_OF_SNUM 28 | |
| 093cffbe KG |
280 | |
| 281 | /* P2010 is single core version of P2020 */ | |
| 243be8e2 KG |
282 | #elif defined(CONFIG_P2010) |
| 283 | #define CONFIG_MAX_CPUS 1 | |
| 284 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 285 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 286 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 6e7f0bc0 | 287 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 5103a03a | 288 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 243be8e2 KG |
289 | |
| 290 | #elif defined(CONFIG_P2020) | |
| 291 | #define CONFIG_MAX_CPUS 2 | |
| 292 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
| 293 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
| e46fedfe | 294 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
| 6e7f0bc0 | 295 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 5103a03a | 296 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 243be8e2 KG |
297 | |
| 298 | #elif defined(CONFIG_PPC_P2040) | |
| 299 | #define CONFIG_MAX_CPUS 4 | |
| b5c8753f | 300 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
| 243be8e2 KG |
301 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 302 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| fbee0f7f KG |
303 | #define CONFIG_SYS_NUM_FMAN 1 |
| 304 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
| 305 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| c657d898 | 306 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
| 66412c63 | 307 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
| 8f29084a | 308 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
| e46fedfe | 309 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
| 86221f09 RZ |
310 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
| 311 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
| b6c3722d | 312 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 30009766 | 313 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 243be8e2 | 314 | |
| 1f97987a KG |
315 | #elif defined(CONFIG_PPC_P2041) |
| 316 | #define CONFIG_MAX_CPUS 4 | |
| 317 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
| 318 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
| 319 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 320 | #define CONFIG_SYS_NUM_FMAN 1 | |
| 321 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
| 322 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
| 323 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 324 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
| 325 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 | |
| 326 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
| e46fedfe | 327 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
| 1f97987a KG |
328 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
| 329 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
| b6c3722d | 330 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 1f97987a KG |
331 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 332 | ||
| 243be8e2 KG |
333 | #elif defined(CONFIG_PPC_P3041) |
| 334 | #define CONFIG_MAX_CPUS 4 | |
| b5c8753f | 335 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
| 243be8e2 KG |
336 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 337 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| fbee0f7f KG |
338 | #define CONFIG_SYS_NUM_FMAN 1 |
| 339 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
| 340 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
| 341 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| c657d898 | 342 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
| 66412c63 | 343 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
| 8f29084a | 344 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
| e46fedfe | 345 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
| 86221f09 RZ |
346 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
| 347 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
| b6c3722d | 348 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 30009766 | 349 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 243be8e2 KG |
350 | |
| 351 | #elif defined(CONFIG_PPC_P4040) | |
| 352 | #define CONFIG_MAX_CPUS 4 | |
| b5c8753f | 353 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
| 243be8e2 KG |
354 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 355 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| c657d898 | 356 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
| 66412c63 | 357 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
| 8f29084a | 358 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
| e46fedfe | 359 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
| 243be8e2 KG |
360 | |
| 361 | #elif defined(CONFIG_PPC_P4080) | |
| 362 | #define CONFIG_MAX_CPUS 8 | |
| b5c8753f | 363 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
| 243be8e2 KG |
364 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 365 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| 366 | #define CONFIG_SYS_NUM_FMAN 2 | |
| 367 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
| 368 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
| 369 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
| 370 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
| 371 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| c657d898 | 372 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
| 66412c63 | 373 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
| 8f29084a | 374 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
| e46fedfe | 375 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
| 243be8e2 KG |
376 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
| 377 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
| fa8d23c0 | 378 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
| 243be8e2 KG |
379 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
| 380 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
| 381 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
| 382 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 | |
| 383 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 | |
| 384 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 | |
| df8af0b4 | 385 | #define CONFIG_SYS_P4080_ERRATUM_SERDES9 |
| d90fdba6 | 386 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
| da30b9fd | 387 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
| 243be8e2 | 388 | |
| 093cffbe | 389 | /* P5010 is single core version of P5020 */ |
| 243be8e2 KG |
390 | #elif defined(CONFIG_PPC_P5010) |
| 391 | #define CONFIG_MAX_CPUS 1 | |
| b5c8753f | 392 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
| 243be8e2 KG |
393 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 394 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| fbee0f7f KG |
395 | #define CONFIG_SYS_NUM_FMAN 1 |
| 396 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
| 397 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
| 398 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| c657d898 | 399 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
| 66412c63 | 400 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
| 8f29084a | 401 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
| e46fedfe | 402 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
| 86221f09 RZ |
403 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
| 404 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
| b6c3722d | 405 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 30009766 | 406 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 243be8e2 KG |
407 | |
| 408 | #elif defined(CONFIG_PPC_P5020) | |
| 409 | #define CONFIG_MAX_CPUS 2 | |
| b5c8753f | 410 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
| 243be8e2 KG |
411 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
| 412 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
| fbee0f7f KG |
413 | #define CONFIG_SYS_NUM_FMAN 1 |
| 414 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
| 415 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
| 416 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| c657d898 | 417 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
| 66412c63 | 418 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
| 8f29084a | 419 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
| e46fedfe | 420 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
| 86221f09 RZ |
421 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
| 422 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
| b6c3722d | 423 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
| 30009766 | 424 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 243be8e2 KG |
425 | |
| 426 | #else | |
| 427 | #error Processor type not defined for this platform | |
| 428 | #endif | |
| 429 | ||
| e46fedfe TT |
430 | #ifndef CONFIG_SYS_CCSRBAR_DEFAULT |
| 431 | #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." | |
| 432 | #endif | |
| 433 | ||
| 243be8e2 | 434 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |