[people/ms/u-boot.git] / arch / powerpc / include / asm / config_mpc85xx.h

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#ifndef _ASM_MPC85xx_CONFIG_H_
#define _ASM_MPC85xx_CONFIG_H_

/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */

/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#define CONFIG_SYS_NUM_TLBCAMS		64
#elif defined(CONFIG_E500)
#define CONFIG_SYS_NUM_TLBCAMS		16
#endif

#if defined(CONFIG_MPC8536)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_MPC8540)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		8

#elif defined(CONFIG_MPC8541)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		8
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_MPC8544)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		10
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_MPC8548)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		10
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		8
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_MPC8560)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		8

#elif defined(CONFIG_MPC8568)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		10
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_MPC8569)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		10
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_MPC8572)
#define CONFIG_MAX_CPUS			2
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_P1010)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT	4

#elif defined(CONFIG_P1011)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_P1012)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_P1014)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT	4

#elif defined(CONFIG_P1020)
#define CONFIG_MAX_CPUS			2
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS			2
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS			2
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT	2

#elif defined(CONFIG_P2010)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_SYS_FSL_SEC_COMPAT	2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001

#elif defined(CONFIG_P2020)
#define CONFIG_MAX_CPUS			2
#define CONFIG_SYS_FSL_NUM_LAWS		12
#define CONFIG_SYS_FSL_SEC_COMPAT	2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001

#elif defined(CONFIG_PPC_P2040)
#define CONFIG_MAX_CPUS			4
#define CONFIG_SYS_FSL_NUM_LAWS		32
#define CONFIG_SYS_FSL_SEC_COMPAT	4

#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS			4
#define CONFIG_SYS_FSL_NUM_LAWS		32
#define CONFIG_SYS_FSL_SEC_COMPAT	4

#elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS			4
#define CONFIG_SYS_FSL_NUM_LAWS		32
#define CONFIG_SYS_FSL_SEC_COMPAT	4

#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS			8
#define CONFIG_SYS_FSL_NUM_LAWS		32
#define CONFIG_SYS_FSL_SEC_COMPAT	4
#define CONFIG_SYS_NUM_FMAN		2
#define CONFIG_SYS_NUM_FM1_DTSEC	4
#define CONFIG_SYS_NUM_FM2_DTSEC	4
#define CONFIG_SYS_NUM_FM1_10GEC	1
#define CONFIG_SYS_NUM_FM2_10GEC	1
#define CONFIG_NUM_DDR_CONTROLLERS	2
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_P4080_ERRATUM_SERDES8

#elif defined(CONFIG_PPC_P5010)
#define CONFIG_MAX_CPUS			1
#define CONFIG_SYS_FSL_NUM_LAWS		32
#define CONFIG_SYS_FSL_SEC_COMPAT	4

#elif defined(CONFIG_PPC_P5020)
#define CONFIG_MAX_CPUS			2
#define CONFIG_SYS_FSL_NUM_LAWS		32
#define CONFIG_SYS_FSL_SEC_COMPAT	4

#else
#error Processor type not defined for this platform
#endif

#endif /* _ASM_MPC85xx_CONFIG_H_ */
Commit	Line	Data
243be8e2 KG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*
	19	*/
	20
	21	#ifndef _ASM_MPC85xx_CONFIG_H_
	22	#define _ASM_MPC85xx_CONFIG_H_
	23
	24	/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
	25
	26	/* Number of TLB CAM entries we have on FSL Book-E chips */
	27	#if defined(CONFIG_E500MC)
	28	#define CONFIG_SYS_NUM_TLBCAMS 64
	29	#elif defined(CONFIG_E500)
	30	#define CONFIG_SYS_NUM_TLBCAMS 16
	31	#endif
	32
	33	#if defined(CONFIG_MPC8536)
	34	#define CONFIG_MAX_CPUS 1
	35	#define CONFIG_SYS_FSL_NUM_LAWS 12
	36	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	37
d1a24f06	38	#elif defined(CONFIG_MPC8540)
243be8e2 KG	39	#define CONFIG_MAX_CPUS 1
	40	#define CONFIG_SYS_FSL_NUM_LAWS 8
	41
d1a24f06	42	#elif defined(CONFIG_MPC8541)
243be8e2 KG	43	#define CONFIG_MAX_CPUS 1
	44	#define CONFIG_SYS_FSL_NUM_LAWS 8
	45	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	46
	47	#elif defined(CONFIG_MPC8544)
	48	#define CONFIG_MAX_CPUS 1
	49	#define CONFIG_SYS_FSL_NUM_LAWS 10
	50	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	51
	52	#elif defined(CONFIG_MPC8548)
	53	#define CONFIG_MAX_CPUS 1
	54	#define CONFIG_SYS_FSL_NUM_LAWS 10
	55	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	56
	57	#elif defined(CONFIG_MPC8555)
	58	#define CONFIG_MAX_CPUS 1
	59	#define CONFIG_SYS_FSL_NUM_LAWS 8
	60	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	61
	62	#elif defined(CONFIG_MPC8560)
	63	#define CONFIG_MAX_CPUS 1
	64	#define CONFIG_SYS_FSL_NUM_LAWS 8
	65
	66	#elif defined(CONFIG_MPC8568)
	67	#define CONFIG_MAX_CPUS 1
	68	#define CONFIG_SYS_FSL_NUM_LAWS 10
	69	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	70
	71	#elif defined(CONFIG_MPC8569)
	72	#define CONFIG_MAX_CPUS 1
	73	#define CONFIG_SYS_FSL_NUM_LAWS 10
	74	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	75
	76	#elif defined(CONFIG_MPC8572)
	77	#define CONFIG_MAX_CPUS 2
	78	#define CONFIG_SYS_FSL_NUM_LAWS 12
	79	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	80
	81	#elif defined(CONFIG_P1010)
	82	#define CONFIG_MAX_CPUS 1
	83	#define CONFIG_SYS_FSL_NUM_LAWS 12
	84	#define CONFIG_TSECV2
	85	#define CONFIG_SYS_FSL_SEC_COMPAT 4
	86
	87	#elif defined(CONFIG_P1011)
	88	#define CONFIG_MAX_CPUS 1
	89	#define CONFIG_SYS_FSL_NUM_LAWS 12
	90	#define CONFIG_TSECV2
	91	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	92
	93	#elif defined(CONFIG_P1012)
	94	#define CONFIG_MAX_CPUS 1
	95	#define CONFIG_SYS_FSL_NUM_LAWS 12
	96	#define CONFIG_TSECV2
	97	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	98
	99	#elif defined(CONFIG_P1013)
	100	#define CONFIG_MAX_CPUS 1
	101	#define CONFIG_SYS_FSL_NUM_LAWS 12
	102	#define CONFIG_TSECV2
	103	#define CONFIG_SYS_FSL_SEC_COMPAT 2
	104
	105	#elif defined(CONFIG_P1014)
	106	#define CONFIG_MAX_CPUS 1
107	#define CONFIG_SYS_FSL_NUM_LAWS 12
108	#define CONFIG_TSECV2
109	#define CONFIG_SYS_FSL_SEC_COMPAT 4
110
111	#elif defined(CONFIG_P1020)
112	#define CONFIG_MAX_CPUS 2
113	#define CONFIG_SYS_FSL_NUM_LAWS 12
114	#define CONFIG_TSECV2
115	#define CONFIG_SYS_FSL_SEC_COMPAT 2
116
117	#elif defined(CONFIG_P1021)
118	#define CONFIG_MAX_CPUS 2
119	#define CONFIG_SYS_FSL_NUM_LAWS 12
120	#define CONFIG_TSECV2
121	#define CONFIG_SYS_FSL_SEC_COMPAT 2
122
123	#elif defined(CONFIG_P1022)
124	#define CONFIG_MAX_CPUS 2
125	#define CONFIG_SYS_FSL_NUM_LAWS 12
126	#define CONFIG_TSECV2
127	#define CONFIG_SYS_FSL_SEC_COMPAT 2
128
129	#elif defined(CONFIG_P2010)
130	#define CONFIG_MAX_CPUS 1
131	#define CONFIG_SYS_FSL_NUM_LAWS 12
132	#define CONFIG_SYS_FSL_SEC_COMPAT 2
6e7f0bc0	133	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
5103a03a	134	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
243be8e2 KG	135
	136	#elif defined(CONFIG_P2020)
	137	#define CONFIG_MAX_CPUS 2
	138	#define CONFIG_SYS_FSL_NUM_LAWS 12
	139	#define CONFIG_SYS_FSL_SEC_COMPAT 2
6e7f0bc0	140	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
5103a03a	141	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
243be8e2 KG	142
	143	#elif defined(CONFIG_PPC_P2040)
	144	#define CONFIG_MAX_CPUS 4
	145	#define CONFIG_SYS_FSL_NUM_LAWS 32
	146	#define CONFIG_SYS_FSL_SEC_COMPAT 4
	147
	148	#elif defined(CONFIG_PPC_P3041)
	149	#define CONFIG_MAX_CPUS 4
	150	#define CONFIG_SYS_FSL_NUM_LAWS 32
	151	#define CONFIG_SYS_FSL_SEC_COMPAT 4
	152
	153	#elif defined(CONFIG_PPC_P4040)
	154	#define CONFIG_MAX_CPUS 4
	155	#define CONFIG_SYS_FSL_NUM_LAWS 32
	156	#define CONFIG_SYS_FSL_SEC_COMPAT 4
	157
	158	#elif defined(CONFIG_PPC_P4080)
	159	#define CONFIG_MAX_CPUS 8
	160	#define CONFIG_SYS_FSL_NUM_LAWS 32
	161	#define CONFIG_SYS_FSL_SEC_COMPAT 4
	162	#define CONFIG_SYS_NUM_FMAN 2
	163	#define CONFIG_SYS_NUM_FM1_DTSEC 4
	164	#define CONFIG_SYS_NUM_FM2_DTSEC 4
	165	#define CONFIG_SYS_NUM_FM1_10GEC 1
	166	#define CONFIG_SYS_NUM_FM2_10GEC 1
	167	#define CONFIG_NUM_DDR_CONTROLLERS 2
	168	#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
	169	#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
fa8d23c0	170	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
243be8e2 KG	171	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
	172	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
	173	#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
	174	#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
	175	#define CONFIG_SYS_P4080_ERRATUM_CPU22
	176	#define CONFIG_SYS_P4080_ERRATUM_SERDES8
	177
	178	#elif defined(CONFIG_PPC_P5010)
	179	#define CONFIG_MAX_CPUS 1
	180	#define CONFIG_SYS_FSL_NUM_LAWS 32
	181	#define CONFIG_SYS_FSL_SEC_COMPAT 4
	182
	183	#elif defined(CONFIG_PPC_P5020)
	184	#define CONFIG_MAX_CPUS 2
	185	#define CONFIG_SYS_FSL_NUM_LAWS 32
	186	#define CONFIG_SYS_FSL_SEC_COMPAT 4
	187
	188	#else
	189	#error Processor type not defined for this platform
	190	#endif
	191
	192	#endif /* _ASM_MPC85xx_CONFIG_H_ */