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243be8e2 | 1 | /* |
19a8dbdc | 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
243be8e2 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
243be8e2 KG |
5 | */ |
6 | ||
7 | #ifndef _ASM_MPC85xx_CONFIG_H_ | |
8 | #define _ASM_MPC85xx_CONFIG_H_ | |
9 | ||
10 | /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ | |
11 | ||
e46fedfe TT |
12 | #ifdef CONFIG_SYS_CCSRBAR_DEFAULT |
13 | #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." | |
14 | #endif | |
15 | ||
2a5fcb83 YS |
16 | /* |
17 | * This macro should be removed when we no longer care about backwards | |
18 | * compatibility with older operating systems. | |
19 | */ | |
20 | #define CONFIG_PPC_SPINTABLE_COMPATIBLE | |
21 | ||
57495e4e | 22 | #define FSL_DDR_VER_4_7 47 |
1d384eca | 23 | #define FSL_DDR_VER_5_0 50 |
57495e4e | 24 | |
1b4175d6 PK |
25 | /* IP endianness */ |
26 | #define CONFIG_SYS_FSL_IFC_BE | |
27 | ||
243be8e2 KG |
28 | /* Number of TLB CAM entries we have on FSL Book-E chips */ |
29 | #if defined(CONFIG_E500MC) | |
30 | #define CONFIG_SYS_NUM_TLBCAMS 64 | |
31 | #elif defined(CONFIG_E500) | |
32 | #define CONFIG_SYS_NUM_TLBCAMS 16 | |
33 | #endif | |
34 | ||
35 | #if defined(CONFIG_MPC8536) | |
36 | #define CONFIG_MAX_CPUS 1 | |
37 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 38 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 |
243be8e2 | 39 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 40 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
954a1a47 | 41 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 42 | |
d1a24f06 | 43 | #elif defined(CONFIG_MPC8540) |
243be8e2 KG |
44 | #define CONFIG_MAX_CPUS 1 |
45 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 46 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
e46fedfe | 47 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 | 48 | |
d1a24f06 | 49 | #elif defined(CONFIG_MPC8541) |
243be8e2 KG |
50 | #define CONFIG_MAX_CPUS 1 |
51 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 52 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
243be8e2 | 53 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 54 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
55 | |
56 | #elif defined(CONFIG_MPC8544) | |
57 | #define CONFIG_MAX_CPUS 1 | |
58 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 59 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
e4879afb | 60 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 61 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 62 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
954a1a47 | 63 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
64 | |
65 | #elif defined(CONFIG_MPC8548) | |
66 | #define CONFIG_MAX_CPUS 1 | |
67 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 68 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
e4879afb | 69 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 |
243be8e2 | 70 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 71 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
5ace2992 | 72 | #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 |
2b3a1cdd | 73 | #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
aada81de | 74 | #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
7d67ed58 LG |
75 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
76 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
77 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
78 | #define CONFIG_SYS_FSL_RMU | |
79 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 80 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
81 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
82 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 | |
243be8e2 KG |
83 | |
84 | #elif defined(CONFIG_MPC8555) | |
85 | #define CONFIG_MAX_CPUS 1 | |
86 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 87 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
243be8e2 | 88 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 89 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
90 | |
91 | #elif defined(CONFIG_MPC8560) | |
92 | #define CONFIG_MAX_CPUS 1 | |
93 | #define CONFIG_SYS_FSL_NUM_LAWS 8 | |
5614e71b | 94 | #define CONFIG_SYS_FSL_DDRC_GEN1 |
e46fedfe | 95 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
243be8e2 KG |
96 | |
97 | #elif defined(CONFIG_MPC8568) | |
98 | #define CONFIG_MAX_CPUS 1 | |
99 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
5614e71b | 100 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
243be8e2 | 101 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
fdb4dad3 KG |
102 | #define QE_MURAM_SIZE 0x10000UL |
103 | #define MAX_QE_RISC 2 | |
104 | #define QE_NUM_OF_SNUM 28 | |
e46fedfe | 105 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
106 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
107 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
108 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
109 | #define CONFIG_SYS_FSL_RMU | |
110 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
243be8e2 KG |
111 | |
112 | #elif defined(CONFIG_MPC8569) | |
113 | #define CONFIG_MAX_CPUS 1 | |
114 | #define CONFIG_SYS_FSL_NUM_LAWS 10 | |
115 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
fdb4dad3 KG |
116 | #define QE_MURAM_SIZE 0x20000UL |
117 | #define MAX_QE_RISC 4 | |
118 | #define QE_NUM_OF_SNUM 46 | |
e46fedfe | 119 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
7d67ed58 LG |
120 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 |
121 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
122 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
123 | #define CONFIG_SYS_FSL_RMU | |
124 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 125 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
126 | |
127 | #elif defined(CONFIG_MPC8572) | |
128 | #define CONFIG_MAX_CPUS 2 | |
129 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
e4879afb | 130 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 131 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 132 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
eb0aff77 | 133 | #define CONFIG_SYS_FSL_ERRATUM_DDR_115 |
91671913 | 134 | #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 |
954a1a47 | 135 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
136 | |
137 | #elif defined(CONFIG_P1010) | |
138 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 139 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 140 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 141 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
142 | #define CONFIG_TSECV2 |
143 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
144 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
145 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 146 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
362ee04b | 147 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
1fbf3483 | 148 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
8f29084a | 149 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
1b719e66 | 150 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 151 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 152 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
424bf942 | 153 | #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 |
bc6bbd6b | 154 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
954a1a47 | 155 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb | 156 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 157 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 158 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 |
f28bea00 | 159 | #define CONFIG_ESDHC_HC_BLK_ADDR |
243be8e2 | 160 | |
093cffbe | 161 | /* P1011 is single core version of P1020 */ |
243be8e2 KG |
162 | #elif defined(CONFIG_P1011) |
163 | #define CONFIG_MAX_CPUS 1 | |
164 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 165 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 166 | #define CONFIG_TSECV2 |
b03a466d | 167 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 168 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
f1810d85 | 169 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 170 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
171 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
172 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
954a1a47 | 173 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 174 | |
093cffbe | 175 | /* P1012 is single core version of P1021 */ |
243be8e2 KG |
176 | #elif defined(CONFIG_P1012) |
177 | #define CONFIG_MAX_CPUS 1 | |
178 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 179 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 180 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 181 | #define CONFIG_TSECV2 |
b03a466d | 182 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 183 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 184 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
185 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
186 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
187 | #define QE_MURAM_SIZE 0x6000UL |
188 | #define MAX_QE_RISC 1 | |
189 | #define QE_NUM_OF_SNUM 28 | |
954a1a47 | 190 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 191 | |
093cffbe | 192 | /* P1013 is single core version of P1022 */ |
243be8e2 KG |
193 | #elif defined(CONFIG_P1013) |
194 | #define CONFIG_MAX_CPUS 1 | |
195 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 196 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 197 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
198 | #define CONFIG_TSECV2 |
199 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 200 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
201 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
202 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
203 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
954a1a47 | 204 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
205 | |
206 | #elif defined(CONFIG_P1014) | |
207 | #define CONFIG_MAX_CPUS 1 | |
32c8cfb2 | 208 | #define CONFIG_FSL_SDHC_V2_3 |
243be8e2 | 209 | #define CONFIG_SYS_FSL_NUM_LAWS 12 |
ad75d442 | 210 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 |
243be8e2 KG |
211 | #define CONFIG_TSECV2 |
212 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
1fbf3483 PA |
213 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
214 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 215 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
1fbf3483 | 216 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
1b719e66 | 217 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
42aee64b | 218 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
fb855f43 | 219 | #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 |
bc6bbd6b | 220 | #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
243be8e2 | 221 | |
093cffbe | 222 | /* P1017 is single core version of P1023 */ |
67a719da RZ |
223 | #elif defined(CONFIG_P1017) |
224 | #define CONFIG_MAX_CPUS 1 | |
225 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
226 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
227 | #define CONFIG_SYS_NUM_FMAN 1 | |
228 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
229 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 230 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
231 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
232 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 233 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 234 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 235 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
954a1a47 | 236 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
67a719da | 237 | |
243be8e2 KG |
238 | #elif defined(CONFIG_P1020) |
239 | #define CONFIG_MAX_CPUS 2 | |
240 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 241 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 242 | #define CONFIG_TSECV2 |
b03a466d | 243 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 244 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 245 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
246 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
247 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
954a1a47 | 248 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 249 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
243be8e2 KG |
250 | |
251 | #elif defined(CONFIG_P1021) | |
252 | #define CONFIG_MAX_CPUS 2 | |
253 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 254 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 255 | #define CONFIG_TSECV2 |
b03a466d | 256 | #define CONFIG_FSL_PCIE_DISABLE_ASPM |
243be8e2 | 257 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 258 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
259 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
260 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
261 | #define QE_MURAM_SIZE 0x6000UL |
262 | #define MAX_QE_RISC 1 | |
263 | #define QE_NUM_OF_SNUM 28 | |
954a1a47 | 264 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 265 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
243be8e2 KG |
266 | |
267 | #elif defined(CONFIG_P1022) | |
268 | #define CONFIG_MAX_CPUS 2 | |
269 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 270 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 KG |
271 | #define CONFIG_TSECV2 |
272 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
f1810d85 | 273 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 274 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
2d7534a3 JY |
275 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
276 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
277 | #define CONFIG_FSL_SATA_ERRATUM_A001 | |
954a1a47 | 278 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 | 279 | |
67a719da RZ |
280 | #elif defined(CONFIG_P1023) |
281 | #define CONFIG_MAX_CPUS 2 | |
282 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
283 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
284 | #define CONFIG_SYS_NUM_FMAN 1 | |
285 | #define CONFIG_SYS_NUM_FM1_DTSEC 2 | |
286 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 287 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
67a719da RZ |
288 | #define CONFIG_SYS_QMAN_NUM_PORTALS 3 |
289 | #define CONFIG_SYS_BMAN_NUM_PORTALS 3 | |
c657d898 | 290 | #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 |
8f29084a | 291 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 292 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 |
954a1a47 | 293 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
294 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
295 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
67a719da | 296 | |
093cffbe KG |
297 | /* P1024 is lower end variant of P1020 */ |
298 | #elif defined(CONFIG_P1024) | |
299 | #define CONFIG_MAX_CPUS 2 | |
300 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 301 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
302 | #define CONFIG_TSECV2 |
303 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
304 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
f1810d85 | 305 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
e46fedfe | 306 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
307 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
308 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
954a1a47 | 309 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
310 | |
311 | /* P1025 is lower end variant of P1021 */ | |
312 | #elif defined(CONFIG_P1025) | |
313 | #define CONFIG_MAX_CPUS 2 | |
314 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
f1810d85 | 315 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ad75d442 | 316 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
093cffbe KG |
317 | #define CONFIG_TSECV2 |
318 | #define CONFIG_FSL_PCIE_DISABLE_ASPM | |
319 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 | |
e46fedfe | 320 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
093cffbe KG |
321 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
322 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
a52d2f81 HW |
323 | #define QE_MURAM_SIZE 0x6000UL |
324 | #define MAX_QE_RISC 1 | |
325 | #define QE_NUM_OF_SNUM 28 | |
954a1a47 | 326 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
093cffbe KG |
327 | |
328 | /* P2010 is single core version of P2020 */ | |
243be8e2 KG |
329 | #elif defined(CONFIG_P2010) |
330 | #define CONFIG_MAX_CPUS 1 | |
331 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 332 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 333 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
f1810d85 | 334 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
e46fedfe | 335 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 336 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 337 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
954a1a47 | 338 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
243be8e2 KG |
339 | |
340 | #elif defined(CONFIG_P2020) | |
341 | #define CONFIG_MAX_CPUS 2 | |
342 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
ad75d442 | 343 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 |
243be8e2 | 344 | #define CONFIG_SYS_FSL_SEC_COMPAT 2 |
e46fedfe | 345 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
6e7f0bc0 | 346 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5103a03a | 347 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
7d67ed58 LG |
348 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
349 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
350 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
351 | #define CONFIG_SYS_FSL_RMU | |
352 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
954a1a47 | 353 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f1810d85 | 354 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
3e978f5d | 355 | #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ |
d1001e3f | 356 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 357 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
1f97987a KG |
358 | #define CONFIG_MAX_CPUS 4 |
359 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
360 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
361 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
362 | #define CONFIG_SYS_NUM_FMAN 1 | |
363 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
364 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
365 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 366 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
1f97987a KG |
367 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
368 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 | |
369 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
e46fedfe | 370 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
1f97987a KG |
371 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
372 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 373 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
1f97987a | 374 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
5e23ab0a | 375 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 376 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 377 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 378 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 379 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
380 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
381 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
382 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
383 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
384 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
385 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
386 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 387 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 388 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
9c3f77eb | 389 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 390 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 391 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 |
1f97987a | 392 | |
243be8e2 | 393 | #elif defined(CONFIG_PPC_P3041) |
d1001e3f | 394 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 395 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 396 | #define CONFIG_MAX_CPUS 4 |
b5c8753f | 397 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
398 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
399 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
400 | #define CONFIG_SYS_NUM_FMAN 1 |
401 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
402 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
403 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
c657d898 | 404 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 405 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 406 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 407 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
408 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
409 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 410 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
f1810d85 | 411 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
30009766 | 412 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
57125f22 | 413 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
99d7b0a4 | 414 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
43f082bb | 415 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
e22be77a | 416 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 417 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
418 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
419 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
420 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
421 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
422 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
423 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 | |
424 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 | |
d59c5570 | 425 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 426 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d217a9ad | 427 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb | 428 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 429 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 430 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 431 | |
3e978f5d | 432 | #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ |
d1001e3f | 433 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 434 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 435 | #define CONFIG_MAX_CPUS 8 |
b5c8753f | 436 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
243be8e2 KG |
437 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
438 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
439 | #define CONFIG_SYS_NUM_FMAN 2 | |
440 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 | |
441 | #define CONFIG_SYS_NUM_FM2_DTSEC 4 | |
442 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
443 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
444 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
f1810d85 | 445 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 446 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 447 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
8f29084a | 448 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" |
e46fedfe | 449 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
243be8e2 KG |
450 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
451 | #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 | |
fa8d23c0 | 452 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
243be8e2 KG |
453 | #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 |
454 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
455 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 | |
4e0be34a | 456 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 |
243be8e2 | 457 | #define CONFIG_SYS_P4080_ERRATUM_CPU22 |
5e23ab0a | 458 | #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 |
243be8e2 | 459 | #define CONFIG_SYS_P4080_ERRATUM_SERDES8 |
df8af0b4 | 460 | #define CONFIG_SYS_P4080_ERRATUM_SERDES9 |
d90fdba6 | 461 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 |
da30b9fd | 462 | #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 |
43f082bb | 463 | #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 |
4108508a | 464 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
465 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
466 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
467 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
468 | #define CONFIG_SYS_FSL_RMU | |
469 | #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 | |
33eee330 SW |
470 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
471 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 | |
472 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 | |
d59c5570 | 473 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
0118033b | 474 | #define CONFIG_SYS_FSL_ERRATUM_A004849 |
d607b968 | 475 | #define CONFIG_SYS_FSL_ERRATUM_A004580 |
c0a4e6b8 | 476 | #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 |
d217a9ad | 477 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
9c3f77eb CL |
478 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
479 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 | |
243be8e2 | 480 | |
3e978f5d | 481 | #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ |
ffd06e02 | 482 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
d1001e3f | 483 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 484 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
243be8e2 | 485 | #define CONFIG_MAX_CPUS 2 |
b5c8753f | 486 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 |
243be8e2 KG |
487 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
488 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
fbee0f7f KG |
489 | #define CONFIG_SYS_NUM_FMAN 1 |
490 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
491 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
492 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
f1810d85 | 493 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
c657d898 | 494 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
66412c63 | 495 | #define CONFIG_SYS_FSL_TBCLK_DIV 32 |
8f29084a | 496 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" |
e46fedfe | 497 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
86221f09 RZ |
498 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE |
499 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
b6c3722d | 500 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
30009766 | 501 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
99d7b0a4 | 502 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
e22be77a | 503 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
4108508a | 504 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 |
7d67ed58 LG |
505 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
506 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
507 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
33eee330 SW |
508 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
509 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
510 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 | |
d59c5570 | 511 | #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 |
9c3f77eb | 512 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
9c641a87 | 513 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
9c3f77eb | 514 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 |
243be8e2 | 515 | |
4905443f | 516 | #elif defined(CONFIG_PPC_P5040) |
1956e431 | 517 | #define CONFIG_SYS_PPC64 |
4905443f | 518 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 |
d2ab4bbc | 519 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
4905443f TT |
520 | #define CONFIG_MAX_CPUS 4 |
521 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 | |
522 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
523 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
524 | #define CONFIG_SYS_NUM_FMAN 2 | |
525 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
526 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
527 | #define CONFIG_SYS_NUM_FM2_DTSEC 5 | |
528 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
529 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
f1810d85 | 530 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
4905443f TT |
531 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 |
532 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
533 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
534 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
535 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
536 | #define CONFIG_SYS_FSL_USB2_PHY_ENABLE | |
537 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
538 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
99d7b0a4 | 539 | #define CONFIG_SYS_FSL_ERRATUM_USB14 |
4905443f TT |
540 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 |
541 | #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 | |
542 | #define CONFIG_SYS_FSL_ERRATUM_A004699 | |
4905443f TT |
543 | #define CONFIG_SYS_FSL_ERRATUM_A004510 |
544 | #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 | |
9c641a87 | 545 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
4905443f | 546 | #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 |
d217a9ad | 547 | #define CONFIG_SYS_FSL_ERRATUM_A005812 |
4905443f | 548 | |
19a8dbdc PK |
549 | #elif defined(CONFIG_BSC9131) |
550 | #define CONFIG_MAX_CPUS 1 | |
551 | #define CONFIG_FSL_SDHC_V2_3 | |
552 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
553 | #define CONFIG_TSECV2 | |
554 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
555 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 556 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
765b0bdb PJ |
557 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 |
558 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
362ee04b | 559 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
19a8dbdc PK |
560 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
561 | #define CONFIG_NAND_FSL_IFC | |
19a8dbdc | 562 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
954a1a47 | 563 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
f28bea00 | 564 | #define CONFIG_ESDHC_HC_BLK_ADDR |
19a8dbdc | 565 | |
35fe948e PK |
566 | #elif defined(CONFIG_BSC9132) |
567 | #define CONFIG_MAX_CPUS 2 | |
568 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 | |
569 | #define CONFIG_FSL_SDHC_V2_3 | |
570 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
571 | #define CONFIG_TSECV2 | |
572 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
573 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
f1810d85 | 574 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
64501c66 PJ |
575 | #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 |
576 | #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 | |
577 | #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 | |
578 | #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 | |
061ffeda | 579 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 |
35fe948e PK |
580 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 |
581 | #define CONFIG_NAND_FSL_IFC | |
35fe948e PK |
582 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
583 | #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK | |
584 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" | |
954a1a47 | 585 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
9c3f77eb CL |
586 | #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
587 | #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 | |
f28bea00 | 588 | #define CONFIG_ESDHC_HC_BLK_ADDR |
35fe948e | 589 | |
3d2972fe YS |
590 | #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) |
591 | #define CONFIG_E6500 | |
ffd06e02 | 592 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
9e758758 YS |
593 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
594 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 595 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
9e758758 | 596 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
3d2972fe | 597 | #ifdef CONFIG_PPC_T4240 |
9e758758 | 598 | #define CONFIG_MAX_CPUS 12 |
ce746fe0 | 599 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } |
9e758758 YS |
600 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 |
601 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
602 | #define CONFIG_SYS_NUM_FM2_DTSEC 8 | |
603 | #define CONFIG_SYS_NUM_FM2_10GEC 2 | |
604 | #define CONFIG_NUM_DDR_CONTROLLERS 3 | |
3d2972fe | 605 | #else |
b6240846 | 606 | #define CONFIG_MAX_CPUS 8 |
ce746fe0 | 607 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } |
3d2972fe YS |
608 | #define CONFIG_SYS_NUM_FM1_DTSEC 7 |
609 | #define CONFIG_SYS_NUM_FM1_10GEC 1 | |
610 | #define CONFIG_SYS_NUM_FM2_DTSEC 7 | |
611 | #define CONFIG_SYS_NUM_FM2_10GEC 1 | |
612 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
613 | #endif | |
b6240846 YS |
614 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 |
615 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
a4c955bc PK |
616 | #define CONFIG_SYS_FSL_SRDS_1 |
617 | #define CONFIG_SYS_FSL_SRDS_2 | |
b6240846 YS |
618 | #define CONFIG_SYS_FSL_SRDS_3 |
619 | #define CONFIG_SYS_FSL_SRDS_4 | |
620 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
621 | #define CONFIG_SYS_NUM_FMAN 2 | |
f1810d85 | 622 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 | 623 | #define CONFIG_SYS_PME_CLK 0 |
b6240846 | 624 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 625 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 |
b6240846 | 626 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
627 | #define CONFIG_SYS_FM1_CLK 3 |
628 | #define CONFIG_SYS_FM2_CLK 3 | |
b6240846 YS |
629 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 |
630 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
631 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
632 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
633 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
634 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
08047937 | 635 | #define CONFIG_SYS_FSL_SRIO_LIODN |
b6240846 YS |
636 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
637 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
638 | #define CONFIG_SYS_FSL_ERRATUM_A004468 | |
639 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
640 | #define CONFIG_SYS_FSL_ERRATUM_A005871 | |
9c641a87 | 641 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
133fbfa9 | 642 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
82125192 | 643 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
b6240846 YS |
644 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
645 | #define CONFIG_SYS_FSL_PCI_VER_3_X | |
646 | ||
8fa0102b PA |
647 | #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) |
648 | #define CONFIG_E6500 | |
e1dbdd81 PA |
649 | #define CONFIG_SYS_PPC64 /* 64-bit core */ |
650 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
651 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
652 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ | |
e1dbdd81 | 653 | #define CONFIG_SYS_FSL_NUM_LAWS 32 |
a4c955bc PK |
654 | #define CONFIG_SYS_FSL_SRDS_1 |
655 | #define CONFIG_SYS_FSL_SRDS_2 | |
e1dbdd81 PA |
656 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 |
657 | #define CONFIG_SYS_NUM_FMAN 1 | |
f1810d85 | 658 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
ce746fe0 | 659 | #define CONFIG_SYS_FM1_CLK 0 |
e1dbdd81 | 660 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 |
362ee04b | 661 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 |
e1dbdd81 PA |
662 | #define CONFIG_SYS_FMAN_V3 |
663 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 | |
664 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
665 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" | |
666 | #define CONFIG_SYS_FSL_USB1_PHY_ENABLE | |
667 | #define CONFIG_SYS_FSL_ERRATUM_A_004934 | |
04feb57f | 668 | #define CONFIG_SYS_FSL_ERRATUM_A005871 |
133fbfa9 | 669 | #define CONFIG_SYS_FSL_ERRATUM_A006379 |
82125192 | 670 | #define CONFIG_SYS_FSL_ERRATUM_A006593 |
7af9a074 SL |
671 | #define CONFIG_SYS_FSL_ERRATUM_A006475 |
672 | #define CONFIG_SYS_FSL_ERRATUM_A006384 | |
e1dbdd81 PA |
673 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
674 | ||
8fa0102b | 675 | #ifdef CONFIG_PPC_B4860 |
f6981439 | 676 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |
d2404141 | 677 | #define CONFIG_MAX_CPUS 4 |
6df82e3c | 678 | #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 |
d2404141 | 679 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 |
ce746fe0 | 680 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } |
d2404141 YS |
681 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 |
682 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
e394ceb1 | 683 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
f1810d85 | 684 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
d2404141 YS |
685 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
686 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
687 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
32f38ee3 | 688 | #define CONFIG_SYS_FSL_SRIO_LIODN |
8fa0102b PA |
689 | #else |
690 | #define CONFIG_MAX_CPUS 2 | |
6df82e3c | 691 | #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 |
8fa0102b PA |
692 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 |
693 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 | |
ce746fe0 | 694 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } |
8fa0102b PA |
695 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 |
696 | #define CONFIG_SYS_NUM_FM1_10GEC 0 | |
697 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
698 | #endif | |
d2404141 | 699 | |
2967af68 PJ |
700 | #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ |
701 | defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) | |
5f208d11 YS |
702 | #define CONFIG_E5500 |
703 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
704 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
f6981439 | 705 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 |
5f208d11 | 706 | #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ |
1d384eca | 707 | #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) |
5f208d11 | 708 | #define CONFIG_MAX_CPUS 4 |
1d384eca PK |
709 | #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) |
710 | #define CONFIG_MAX_CPUS 2 | |
711 | #endif | |
712 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
ce746fe0 PK |
713 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } |
714 | #define CONFIG_SYS_SDHC_CLOCK 0 | |
5f208d11 | 715 | #define CONFIG_SYS_FSL_NUM_LAWS 16 |
1d384eca PK |
716 | #define CONFIG_SYS_FSL_SRDS_1 |
717 | #define CONFIG_SYS_FSL_SEC_COMPAT 5 | |
5f208d11 YS |
718 | #define CONFIG_SYS_NUM_FMAN 1 |
719 | #define CONFIG_SYS_NUM_FM1_DTSEC 5 | |
720 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
f1810d85 | 721 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
ce746fe0 PK |
722 | #define CONFIG_PME_PLAT_CLK_DIV 2 |
723 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
1d384eca PK |
724 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
725 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
5f208d11 | 726 | #define CONFIG_SYS_FMAN_V3 |
ce746fe0 PK |
727 | #define CONFIG_FM_PLAT_CLK_DIV 1 |
728 | #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV | |
1d384eca | 729 | #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 |
b135991a | 730 | #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
e03c76c3 | 731 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 |
5f208d11 | 732 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" |
a4f7cba6 | 733 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
5f208d11 | 734 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY |
9c641a87 | 735 | #define CONFIG_SYS_FSL_ERRATUM_A006261 |
5f208d11 | 736 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 |
1336e2d3 HZ |
737 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
738 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE | |
5f208d11 | 739 | |
629d6b32 SL |
740 | #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) |
741 | #define CONFIG_E6500 | |
742 | #define CONFIG_SYS_PPC64 /* 64-bit core */ | |
743 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
744 | #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ | |
745 | #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 | |
746 | #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 | |
747 | #define CONFIG_SYS_FSL_QMAN_V3 | |
748 | #define CONFIG_MAX_CPUS 4 | |
749 | #define CONFIG_SYS_FSL_NUM_LAWS 32 | |
750 | #define CONFIG_SYS_FSL_SEC_COMPAT 4 | |
751 | #define CONFIG_SYS_NUM_FMAN 1 | |
752 | #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } | |
753 | #define CONFIG_SYS_FSL_SRDS_1 | |
754 | #define CONFIG_SYS_FSL_PCI_VER_3_X | |
755 | #if defined(CONFIG_PPC_T2080) | |
756 | #define CONFIG_SYS_NUM_FM1_DTSEC 8 | |
757 | #define CONFIG_SYS_NUM_FM1_10GEC 4 | |
758 | #define CONFIG_SYS_FSL_SRDS_2 | |
759 | #define CONFIG_SYS_FSL_SRIO_LIODN | |
760 | #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 | |
761 | #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 | |
762 | #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 | |
763 | #elif defined(CONFIG_PPC_T2081) | |
764 | #define CONFIG_SYS_NUM_FM1_DTSEC 6 | |
765 | #define CONFIG_SYS_NUM_FM1_10GEC 2 | |
766 | #endif | |
2ffa96d8 | 767 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
629d6b32 SL |
768 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
769 | #define CONFIG_PME_PLAT_CLK_DIV 1 | |
770 | #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV | |
771 | #define CONFIG_SYS_FM1_CLK 0 | |
772 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 | |
773 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
774 | #define CONFIG_SYS_FMAN_V3 | |
775 | #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 | |
776 | #define CONFIG_SYS_FSL_TBCLK_DIV 16 | |
777 | #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" | |
778 | #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE | |
779 | #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY | |
780 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 | |
781 | #define CONFIG_SYS_FSL_SFP_VER_3_0 | |
782 | #define CONFIG_SYS_FSL_ISBC_VER 2 | |
1336e2d3 HZ |
783 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
784 | #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE | |
785 | ||
629d6b32 | 786 | |
3b75e982 MH |
787 | #elif defined(CONFIG_PPC_C29X) |
788 | #define CONFIG_MAX_CPUS 1 | |
789 | #define CONFIG_FSL_SDHC_V2_3 | |
790 | #define CONFIG_SYS_FSL_NUM_LAWS 12 | |
791 | #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 | |
792 | #define CONFIG_TSECV2_1 | |
793 | #define CONFIG_SYS_FSL_SEC_COMPAT 6 | |
794 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
795 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
796 | #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 | |
797 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 | |
954a1a47 | 798 | #define CONFIG_SYS_FSL_ERRATUM_A005125 |
3b75e982 | 799 | |
243be8e2 KG |
800 | #else |
801 | #error Processor type not defined for this platform | |
802 | #endif | |
803 | ||
e46fedfe TT |
804 | #ifndef CONFIG_SYS_CCSRBAR_DEFAULT |
805 | #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." | |
806 | #endif | |
807 | ||
f6981439 YS |
808 | #ifdef CONFIG_E6500 |
809 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 | |
810 | #else | |
811 | #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 | |
812 | #endif | |
813 | ||
5614e71b YS |
814 | #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ |
815 | !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ | |
816 | !defined(CONFIG_SYS_FSL_DDRC_GEN3) | |
817 | #define CONFIG_SYS_FSL_DDRC_GEN3 | |
818 | #endif | |
819 | ||
243be8e2 | 820 | #endif /* _ASM_MPC85xx_CONFIG_H_ */ |