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42d1f039 WD |
1 | |
2 | /* | |
3 | * MPC85xx Communication Processor Module | |
4 | * Copyright (c) 2003,Motorola Inc. | |
5 | * Xianghua Xiao (X.Xiao@motorola.com) | |
6 | * | |
7 | * MPC8260 Communication Processor Module. | |
8 | * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) | |
9 | * | |
10 | * This file contains structures and information for the communication | |
11 | * processor channels found in the dual port RAM or parameter RAM. | |
12 | * All CPM control and status is available through the MPC8260 internal | |
13 | * memory map. See immap.h for details. | |
14 | */ | |
15 | #ifndef __CPM_85XX__ | |
16 | #define __CPM_85XX__ | |
17 | ||
18 | #include <asm/immap_85xx.h> | |
19 | ||
20 | /* CPM Command register. | |
21 | */ | |
22 | #define CPM_CR_RST ((uint)0x80000000) | |
23 | #define CPM_CR_PAGE ((uint)0x7c000000) | |
24 | #define CPM_CR_SBLOCK ((uint)0x03e00000) | |
25 | #define CPM_CR_FLG ((uint)0x00010000) | |
26 | #define CPM_CR_MCN ((uint)0x00003fc0) | |
27 | #define CPM_CR_OPCODE ((uint)0x0000000f) | |
28 | ||
29 | /* Device sub-block and page codes. | |
30 | */ | |
31 | #define CPM_CR_SCC1_SBLOCK (0x04) | |
32 | #define CPM_CR_SCC2_SBLOCK (0x05) | |
33 | #define CPM_CR_SCC3_SBLOCK (0x06) | |
34 | #define CPM_CR_SCC4_SBLOCK (0x07) | |
35 | #define CPM_CR_SMC1_SBLOCK (0x08) | |
36 | #define CPM_CR_SMC2_SBLOCK (0x09) | |
37 | #define CPM_CR_SPI_SBLOCK (0x0a) | |
38 | #define CPM_CR_I2C_SBLOCK (0x0b) | |
39 | #define CPM_CR_TIMER_SBLOCK (0x0f) | |
40 | #define CPM_CR_RAND_SBLOCK (0x0e) | |
41 | #define CPM_CR_FCC1_SBLOCK (0x10) | |
42 | #define CPM_CR_FCC2_SBLOCK (0x11) | |
43 | #define CPM_CR_FCC3_SBLOCK (0x12) | |
44 | #define CPM_CR_MCC1_SBLOCK (0x1c) | |
45 | ||
46 | #define CPM_CR_SCC1_PAGE (0x00) | |
47 | #define CPM_CR_SCC2_PAGE (0x01) | |
48 | #define CPM_CR_SCC3_PAGE (0x02) | |
49 | #define CPM_CR_SCC4_PAGE (0x03) | |
50 | #define CPM_CR_SPI_PAGE (0x09) | |
51 | #define CPM_CR_I2C_PAGE (0x0a) | |
52 | #define CPM_CR_TIMER_PAGE (0x0a) | |
53 | #define CPM_CR_RAND_PAGE (0x0a) | |
54 | #define CPM_CR_FCC1_PAGE (0x04) | |
55 | #define CPM_CR_FCC2_PAGE (0x05) | |
56 | #define CPM_CR_FCC3_PAGE (0x06) | |
57 | #define CPM_CR_MCC1_PAGE (0x07) | |
58 | #define CPM_CR_MCC2_PAGE (0x08) | |
59 | ||
60 | /* Some opcodes (there are more...later) | |
61 | */ | |
62 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | |
63 | #define CPM_CR_INIT_RX ((ushort)0x0001) | |
64 | #define CPM_CR_INIT_TX ((ushort)0x0002) | |
65 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | |
66 | #define CPM_CR_STOP_TX ((ushort)0x0004) | |
67 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | |
68 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | |
69 | ||
70 | #define mk_cr_cmd(PG, SBC, MCN, OP) \ | |
71 | ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) | |
72 | ||
73 | /* Dual Port RAM addresses. The first 16K is available for almost | |
74 | * any CPM use, so we put the BDs there. The first 128 bytes are | |
75 | * used for SMC1 and SMC2 parameter RAM, so we start allocating | |
76 | * BDs above that. All of this must change when we start | |
77 | * downloading RAM microcode. | |
78 | */ | |
79 | #define CPM_DATAONLY_BASE ((uint)128) | |
a889bd27 WD |
80 | #define CPM_DP_NOSPACE ((uint)0x7FFFFFFF) |
81 | #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) | |
82 | #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) | |
83 | #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) | |
84 | #else /* MPC8540, MPC8560 */ | |
85 | #define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000) | |
42d1f039 | 86 | #define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) |
a889bd27 | 87 | #endif |
42d1f039 WD |
88 | |
89 | /* The number of pages of host memory we allocate for CPM. This is | |
90 | * done early in kernel initialization to get physically contiguous | |
91 | * pages. | |
92 | */ | |
93 | #define NUM_CPM_HOST_PAGES 2 | |
94 | ||
95 | /* Export the base address of the communication processor registers | |
96 | * and dual port ram. | |
97 | */ | |
98 | /*extern cpm8560_t *cpmp; Pointer to comm processor */ | |
99 | uint m8560_cpm_dpalloc(uint size, uint align); | |
100 | uint m8560_cpm_hostalloc(uint size, uint align); | |
101 | void m8560_cpm_setbrg(uint brg, uint rate); | |
102 | void m8560_cpm_fastbrg(uint brg, uint rate, int div16); | |
103 | void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); | |
104 | ||
105 | /* Buffer descriptors used by many of the CPM protocols. | |
106 | */ | |
107 | typedef struct cpm_buf_desc { | |
108 | ushort cbd_sc; /* Status and Control */ | |
109 | ushort cbd_datlen; /* Data length in buffer */ | |
110 | uint cbd_bufaddr; /* Buffer address in host memory */ | |
111 | } cbd_t; | |
112 | ||
113 | #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ | |
114 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ | |
115 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | |
116 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | |
117 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ | |
118 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | |
119 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | |
120 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | |
121 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | |
122 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | |
123 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | |
124 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | |
125 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ | |
126 | ||
127 | /* Function code bits, usually generic to devices. | |
128 | */ | |
129 | #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ | |
130 | #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ | |
131 | #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ | |
132 | #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ | |
133 | #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ | |
134 | ||
135 | /* Parameter RAM offsets from the base. | |
136 | */ | |
137 | #define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ | |
138 | #define PROFF_SCC1 ((uint)0x8000) | |
139 | #define PROFF_SCC2 ((uint)0x8100) | |
140 | #define PROFF_SCC3 ((uint)0x8200) | |
141 | #define PROFF_SCC4 ((uint)0x8300) | |
142 | #define PROFF_FCC1 ((uint)0x8400) | |
143 | #define PROFF_FCC2 ((uint)0x8500) | |
144 | #define PROFF_FCC3 ((uint)0x8600) | |
145 | #define PROFF_MCC1 ((uint)0x8700) | |
146 | #define PROFF_MCC2 ((uint)0x8800) | |
147 | #define PROFF_SPI_BASE ((uint)0x89fc) | |
148 | #define PROFF_TIMERS ((uint)0x8ae0) | |
149 | #define PROFF_REVNUM ((uint)0x8af0) | |
150 | #define PROFF_RAND ((uint)0x8af8) | |
151 | #define PROFF_I2C_BASE ((uint)0x8afc) | |
152 | ||
153 | /* Baud rate generators. | |
154 | */ | |
155 | #define CPM_BRG_RST ((uint)0x00020000) | |
156 | #define CPM_BRG_EN ((uint)0x00010000) | |
157 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | |
158 | #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) | |
159 | #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) | |
160 | #define CPM_BRG_ATB ((uint)0x00002000) | |
161 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | |
162 | #define CPM_BRG_DIV16 ((uint)0x00000001) | |
163 | ||
164 | /* SCCs. | |
165 | */ | |
166 | #define SCC_GSMRH_IRP ((uint)0x00040000) | |
167 | #define SCC_GSMRH_GDE ((uint)0x00010000) | |
168 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | |
169 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | |
170 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | |
171 | #define SCC_GSMRH_REVD ((uint)0x00002000) | |
172 | #define SCC_GSMRH_TRX ((uint)0x00001000) | |
173 | #define SCC_GSMRH_TTX ((uint)0x00000800) | |
174 | #define SCC_GSMRH_CDP ((uint)0x00000400) | |
175 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | |
176 | #define SCC_GSMRH_CDS ((uint)0x00000100) | |
177 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | |
178 | #define SCC_GSMRH_TFL ((uint)0x00000040) | |
179 | #define SCC_GSMRH_RFW ((uint)0x00000020) | |
180 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | |
181 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | |
182 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | |
183 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | |
184 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | |
185 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | |
186 | ||
187 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | |
188 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | |
189 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | |
190 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | |
191 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | |
192 | #define SCC_GSMRL_TCI ((uint)0x10000000) | |
193 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | |
194 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | |
195 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | |
196 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | |
197 | #define SCC_GSMRL_RINV ((uint)0x02000000) | |
198 | #define SCC_GSMRL_TINV ((uint)0x01000000) | |
199 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | |
200 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | |
201 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | |
202 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | |
203 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | |
204 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | |
205 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | |
206 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | |
207 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | |
208 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | |
209 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | |
210 | #define SCC_GSMRL_TEND ((uint)0x00040000) | |
211 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | |
212 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | |
213 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | |
214 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | |
215 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | |
216 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | |
217 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | |
218 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | |
219 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | |
220 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | |
221 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | |
222 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | |
223 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | |
224 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | |
225 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | |
226 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | |
227 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | |
228 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | |
229 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | |
230 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | |
231 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | |
232 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | |
233 | #define SCC_GSMRL_ENR ((uint)0x00000020) | |
234 | #define SCC_GSMRL_ENT ((uint)0x00000010) | |
235 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | |
236 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | |
237 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | |
238 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | |
239 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | |
240 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | |
241 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | |
242 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | |
243 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | |
244 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | |
245 | ||
246 | #define SCC_TODR_TOD ((ushort)0x8000) | |
247 | ||
248 | /* SCC Event and Mask register. | |
249 | */ | |
250 | #define SCCM_TXE ((unsigned char)0x10) | |
251 | #define SCCM_BSY ((unsigned char)0x04) | |
252 | #define SCCM_TX ((unsigned char)0x02) | |
253 | #define SCCM_RX ((unsigned char)0x01) | |
254 | ||
255 | typedef struct scc_param { | |
256 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | |
257 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | |
258 | u_char scc_rfcr; /* Rx function code */ | |
259 | u_char scc_tfcr; /* Tx function code */ | |
260 | ushort scc_mrblr; /* Max receive buffer length */ | |
261 | uint scc_rstate; /* Internal */ | |
262 | uint scc_idp; /* Internal */ | |
263 | ushort scc_rbptr; /* Internal */ | |
264 | ushort scc_ibc; /* Internal */ | |
265 | uint scc_rxtmp; /* Internal */ | |
266 | uint scc_tstate; /* Internal */ | |
267 | uint scc_tdp; /* Internal */ | |
268 | ushort scc_tbptr; /* Internal */ | |
269 | ushort scc_tbc; /* Internal */ | |
270 | uint scc_txtmp; /* Internal */ | |
271 | uint scc_rcrc; /* Internal */ | |
272 | uint scc_tcrc; /* Internal */ | |
273 | } sccp_t; | |
274 | ||
275 | /* CPM Ethernet through SCC1. | |
276 | */ | |
277 | typedef struct scc_enet { | |
278 | sccp_t sen_genscc; | |
279 | uint sen_cpres; /* Preset CRC */ | |
280 | uint sen_cmask; /* Constant mask for CRC */ | |
281 | uint sen_crcec; /* CRC Error counter */ | |
282 | uint sen_alec; /* alignment error counter */ | |
283 | uint sen_disfc; /* discard frame counter */ | |
284 | ushort sen_pads; /* Tx short frame pad character */ | |
285 | ushort sen_retlim; /* Retry limit threshold */ | |
286 | ushort sen_retcnt; /* Retry limit counter */ | |
287 | ushort sen_maxflr; /* maximum frame length register */ | |
288 | ushort sen_minflr; /* minimum frame length register */ | |
289 | ushort sen_maxd1; /* maximum DMA1 length */ | |
290 | ushort sen_maxd2; /* maximum DMA2 length */ | |
291 | ushort sen_maxd; /* Rx max DMA */ | |
292 | ushort sen_dmacnt; /* Rx DMA counter */ | |
293 | ushort sen_maxb; /* Max BD byte count */ | |
294 | ushort sen_gaddr1; /* Group address filter */ | |
295 | ushort sen_gaddr2; | |
296 | ushort sen_gaddr3; | |
297 | ushort sen_gaddr4; | |
298 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | |
299 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | |
300 | uint sen_tbuf0rba; /* Internal */ | |
301 | uint sen_tbuf0crc; /* Internal */ | |
302 | ushort sen_tbuf0bcnt; /* Internal */ | |
303 | ushort sen_paddrh; /* physical address (MSB) */ | |
304 | ushort sen_paddrm; | |
305 | ushort sen_paddrl; /* physical address (LSB) */ | |
306 | ushort sen_pper; /* persistence */ | |
307 | ushort sen_rfbdptr; /* Rx first BD pointer */ | |
308 | ushort sen_tfbdptr; /* Tx first BD pointer */ | |
309 | ushort sen_tlbdptr; /* Tx last BD pointer */ | |
310 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | |
311 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | |
312 | uint sen_tbuf1rba; /* Internal */ | |
313 | uint sen_tbuf1crc; /* Internal */ | |
314 | ushort sen_tbuf1bcnt; /* Internal */ | |
315 | ushort sen_txlen; /* Tx Frame length counter */ | |
316 | ushort sen_iaddr1; /* Individual address filter */ | |
317 | ushort sen_iaddr2; | |
318 | ushort sen_iaddr3; | |
319 | ushort sen_iaddr4; | |
320 | ushort sen_boffcnt; /* Backoff counter */ | |
321 | ||
322 | /* NOTE: Some versions of the manual have the following items | |
323 | * incorrectly documented. Below is the proper order. | |
324 | */ | |
325 | ushort sen_taddrh; /* temp address (MSB) */ | |
326 | ushort sen_taddrm; | |
327 | ushort sen_taddrl; /* temp address (LSB) */ | |
328 | } scc_enet_t; | |
329 | ||
330 | ||
331 | /* SCC Event register as used by Ethernet. | |
332 | */ | |
333 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | |
334 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | |
335 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | |
336 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | |
337 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | |
338 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | |
339 | ||
340 | /* SCC Mode Register (PSMR) as used by Ethernet. | |
341 | */ | |
342 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | |
343 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | |
344 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | |
345 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | |
346 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | |
347 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | |
348 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | |
349 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | |
350 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | |
351 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | |
352 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | |
353 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | |
354 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | |
355 | ||
356 | /* Buffer descriptor control/status used by Ethernet receive. | |
357 | * Common to SCC and FCC. | |
358 | */ | |
359 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | |
360 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | |
361 | #define BD_ENET_RX_INTR ((ushort)0x1000) | |
362 | #define BD_ENET_RX_LAST ((ushort)0x0800) | |
363 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | |
364 | #define BD_ENET_RX_MISS ((ushort)0x0100) | |
365 | #define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ | |
366 | #define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ | |
367 | #define BD_ENET_RX_LG ((ushort)0x0020) | |
368 | #define BD_ENET_RX_NO ((ushort)0x0010) | |
369 | #define BD_ENET_RX_SH ((ushort)0x0008) | |
370 | #define BD_ENET_RX_CR ((ushort)0x0004) | |
371 | #define BD_ENET_RX_OV ((ushort)0x0002) | |
372 | #define BD_ENET_RX_CL ((ushort)0x0001) | |
373 | #define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ | |
374 | ||
375 | /* Buffer descriptor control/status used by Ethernet transmit. | |
376 | * Common to SCC and FCC. | |
377 | */ | |
378 | #define BD_ENET_TX_READY ((ushort)0x8000) | |
379 | #define BD_ENET_TX_PAD ((ushort)0x4000) | |
380 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | |
381 | #define BD_ENET_TX_INTR ((ushort)0x1000) | |
382 | #define BD_ENET_TX_LAST ((ushort)0x0800) | |
383 | #define BD_ENET_TX_TC ((ushort)0x0400) | |
384 | #define BD_ENET_TX_DEF ((ushort)0x0200) | |
385 | #define BD_ENET_TX_HB ((ushort)0x0100) | |
386 | #define BD_ENET_TX_LC ((ushort)0x0080) | |
387 | #define BD_ENET_TX_RL ((ushort)0x0040) | |
388 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | |
389 | #define BD_ENET_TX_UN ((ushort)0x0002) | |
390 | #define BD_ENET_TX_CSL ((ushort)0x0001) | |
391 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | |
392 | ||
393 | /* SCC as UART | |
394 | */ | |
395 | typedef struct scc_uart { | |
396 | sccp_t scc_genscc; | |
397 | uint scc_res1; /* Reserved */ | |
398 | uint scc_res2; /* Reserved */ | |
399 | ushort scc_maxidl; /* Maximum idle chars */ | |
400 | ushort scc_idlc; /* temp idle counter */ | |
401 | ushort scc_brkcr; /* Break count register */ | |
402 | ushort scc_parec; /* receive parity error counter */ | |
403 | ushort scc_frmec; /* receive framing error counter */ | |
404 | ushort scc_nosec; /* receive noise counter */ | |
405 | ushort scc_brkec; /* receive break condition counter */ | |
406 | ushort scc_brkln; /* last received break length */ | |
407 | ushort scc_uaddr1; /* UART address character 1 */ | |
408 | ushort scc_uaddr2; /* UART address character 2 */ | |
409 | ushort scc_rtemp; /* Temp storage */ | |
410 | ushort scc_toseq; /* Transmit out of sequence char */ | |
411 | ushort scc_char1; /* control character 1 */ | |
412 | ushort scc_char2; /* control character 2 */ | |
413 | ushort scc_char3; /* control character 3 */ | |
414 | ushort scc_char4; /* control character 4 */ | |
415 | ushort scc_char5; /* control character 5 */ | |
416 | ushort scc_char6; /* control character 6 */ | |
417 | ushort scc_char7; /* control character 7 */ | |
418 | ushort scc_char8; /* control character 8 */ | |
419 | ushort scc_rccm; /* receive control character mask */ | |
420 | ushort scc_rccr; /* receive control character register */ | |
421 | ushort scc_rlbc; /* receive last break character */ | |
422 | } scc_uart_t; | |
423 | ||
424 | /* SCC Event and Mask registers when it is used as a UART. | |
425 | */ | |
426 | #define UART_SCCM_GLR ((ushort)0x1000) | |
427 | #define UART_SCCM_GLT ((ushort)0x0800) | |
428 | #define UART_SCCM_AB ((ushort)0x0200) | |
429 | #define UART_SCCM_IDL ((ushort)0x0100) | |
430 | #define UART_SCCM_GRA ((ushort)0x0080) | |
431 | #define UART_SCCM_BRKE ((ushort)0x0040) | |
432 | #define UART_SCCM_BRKS ((ushort)0x0020) | |
433 | #define UART_SCCM_CCR ((ushort)0x0008) | |
434 | #define UART_SCCM_BSY ((ushort)0x0004) | |
435 | #define UART_SCCM_TX ((ushort)0x0002) | |
436 | #define UART_SCCM_RX ((ushort)0x0001) | |
437 | ||
438 | /* The SCC PSMR when used as a UART. | |
439 | */ | |
440 | #define SCU_PSMR_FLC ((ushort)0x8000) | |
441 | #define SCU_PSMR_SL ((ushort)0x4000) | |
442 | #define SCU_PSMR_CL ((ushort)0x3000) | |
443 | #define SCU_PSMR_UM ((ushort)0x0c00) | |
444 | #define SCU_PSMR_FRZ ((ushort)0x0200) | |
445 | #define SCU_PSMR_RZS ((ushort)0x0100) | |
446 | #define SCU_PSMR_SYN ((ushort)0x0080) | |
447 | #define SCU_PSMR_DRT ((ushort)0x0040) | |
448 | #define SCU_PSMR_PEN ((ushort)0x0010) | |
449 | #define SCU_PSMR_RPM ((ushort)0x000c) | |
450 | #define SCU_PSMR_REVP ((ushort)0x0008) | |
451 | #define SCU_PSMR_TPM ((ushort)0x0003) | |
452 | #define SCU_PSMR_TEVP ((ushort)0x0003) | |
453 | ||
454 | /* CPM Transparent mode SCC. | |
455 | */ | |
456 | typedef struct scc_trans { | |
457 | sccp_t st_genscc; | |
458 | uint st_cpres; /* Preset CRC */ | |
459 | uint st_cmask; /* Constant mask for CRC */ | |
460 | } scc_trans_t; | |
461 | ||
462 | #define BD_SCC_TX_LAST ((ushort)0x0800) | |
463 | ||
464 | /* How about some FCCs..... | |
465 | */ | |
466 | #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) | |
467 | #define FCC_GFMR_DIAG_LE ((uint)0x40000000) | |
468 | #define FCC_GFMR_DIAG_AE ((uint)0x80000000) | |
469 | #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) | |
470 | #define FCC_GFMR_TCI ((uint)0x20000000) | |
471 | #define FCC_GFMR_TRX ((uint)0x10000000) | |
472 | #define FCC_GFMR_TTX ((uint)0x08000000) | |
473 | #define FCC_GFMR_TTX ((uint)0x08000000) | |
474 | #define FCC_GFMR_CDP ((uint)0x04000000) | |
475 | #define FCC_GFMR_CTSP ((uint)0x02000000) | |
476 | #define FCC_GFMR_CDS ((uint)0x01000000) | |
477 | #define FCC_GFMR_CTSS ((uint)0x00800000) | |
478 | #define FCC_GFMR_SYNL_NONE ((uint)0x00000000) | |
479 | #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) | |
480 | #define FCC_GFMR_SYNL_8 ((uint)0x00008000) | |
481 | #define FCC_GFMR_SYNL_16 ((uint)0x0000c000) | |
482 | #define FCC_GFMR_RTSM ((uint)0x00002000) | |
483 | #define FCC_GFMR_RENC_NRZ ((uint)0x00000000) | |
484 | #define FCC_GFMR_RENC_NRZI ((uint)0x00000800) | |
485 | #define FCC_GFMR_REVD ((uint)0x00000400) | |
486 | #define FCC_GFMR_TENC_NRZ ((uint)0x00000000) | |
487 | #define FCC_GFMR_TENC_NRZI ((uint)0x00000100) | |
488 | #define FCC_GFMR_TCRC_16 ((uint)0x00000000) | |
489 | #define FCC_GFMR_TCRC_32 ((uint)0x00000080) | |
490 | #define FCC_GFMR_ENR ((uint)0x00000020) | |
491 | #define FCC_GFMR_ENT ((uint)0x00000010) | |
492 | #define FCC_GFMR_MODE_ENET ((uint)0x0000000c) | |
493 | #define FCC_GFMR_MODE_ATM ((uint)0x0000000a) | |
494 | #define FCC_GFMR_MODE_HDLC ((uint)0x00000000) | |
495 | ||
496 | /* Generic FCC parameter ram. | |
497 | */ | |
498 | typedef struct fcc_param { | |
499 | ushort fcc_riptr; /* Rx Internal temp pointer */ | |
500 | ushort fcc_tiptr; /* Tx Internal temp pointer */ | |
501 | ushort fcc_res1; | |
502 | ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ | |
503 | uint fcc_rstate; /* Upper byte is Func code, must be set */ | |
504 | uint fcc_rbase; /* Receive BD base */ | |
505 | ushort fcc_rbdstat; /* RxBD status */ | |
506 | ushort fcc_rbdlen; /* RxBD down counter */ | |
507 | uint fcc_rdptr; /* RxBD internal data pointer */ | |
508 | uint fcc_tstate; /* Upper byte is Func code, must be set */ | |
509 | uint fcc_tbase; /* Transmit BD base */ | |
510 | ushort fcc_tbdstat; /* TxBD status */ | |
511 | ushort fcc_tbdlen; /* TxBD down counter */ | |
512 | uint fcc_tdptr; /* TxBD internal data pointer */ | |
513 | uint fcc_rbptr; /* Rx BD Internal buf pointer */ | |
514 | uint fcc_tbptr; /* Tx BD Internal buf pointer */ | |
515 | uint fcc_rcrc; /* Rx temp CRC */ | |
516 | uint fcc_res2; | |
517 | uint fcc_tcrc; /* Tx temp CRC */ | |
518 | } fccp_t; | |
519 | ||
520 | ||
521 | /* Ethernet controller through FCC. | |
522 | */ | |
523 | typedef struct fcc_enet { | |
524 | fccp_t fen_genfcc; | |
525 | uint fen_statbuf; /* Internal status buffer */ | |
526 | uint fen_camptr; /* CAM address */ | |
527 | uint fen_cmask; /* Constant mask for CRC */ | |
528 | uint fen_cpres; /* Preset CRC */ | |
529 | uint fen_crcec; /* CRC Error counter */ | |
530 | uint fen_alec; /* alignment error counter */ | |
531 | uint fen_disfc; /* discard frame counter */ | |
532 | ushort fen_retlim; /* Retry limit */ | |
533 | ushort fen_retcnt; /* Retry counter */ | |
534 | ushort fen_pper; /* Persistence */ | |
535 | ushort fen_boffcnt; /* backoff counter */ | |
536 | uint fen_gaddrh; /* Group address filter, high 32-bits */ | |
537 | uint fen_gaddrl; /* Group address filter, low 32-bits */ | |
538 | ushort fen_tfcstat; /* out of sequence TxBD */ | |
539 | ushort fen_tfclen; | |
540 | uint fen_tfcptr; | |
541 | ushort fen_mflr; /* Maximum frame length (1518) */ | |
542 | ushort fen_paddrh; /* MAC address */ | |
543 | ushort fen_paddrm; | |
544 | ushort fen_paddrl; | |
545 | ushort fen_ibdcount; /* Internal BD counter */ | |
546 | ushort fen_ibdstart; /* Internal BD start pointer */ | |
547 | ushort fen_ibdend; /* Internal BD end pointer */ | |
548 | ushort fen_txlen; /* Internal Tx frame length counter */ | |
549 | uint fen_ibdbase[8]; /* Internal use */ | |
550 | uint fen_iaddrh; /* Individual address filter */ | |
551 | uint fen_iaddrl; | |
552 | ushort fen_minflr; /* Minimum frame length (64) */ | |
553 | ushort fen_taddrh; /* Filter transfer MAC address */ | |
554 | ushort fen_taddrm; | |
555 | ushort fen_taddrl; | |
556 | ushort fen_padptr; /* Pointer to pad byte buffer */ | |
557 | ushort fen_cftype; /* control frame type */ | |
558 | ushort fen_cfrange; /* control frame range */ | |
559 | ushort fen_maxb; /* maximum BD count */ | |
560 | ushort fen_maxd1; /* Max DMA1 length (1520) */ | |
561 | ushort fen_maxd2; /* Max DMA2 length (1520) */ | |
562 | ushort fen_maxd; /* internal max DMA count */ | |
563 | ushort fen_dmacnt; /* internal DMA counter */ | |
564 | uint fen_octc; /* Total octect counter */ | |
565 | uint fen_colc; /* Total collision counter */ | |
566 | uint fen_broc; /* Total broadcast packet counter */ | |
567 | uint fen_mulc; /* Total multicast packet count */ | |
568 | uint fen_uspc; /* Total packets < 64 bytes */ | |
569 | uint fen_frgc; /* Total packets < 64 bytes with errors */ | |
570 | uint fen_ospc; /* Total packets > 1518 */ | |
571 | uint fen_jbrc; /* Total packets > 1518 with errors */ | |
572 | uint fen_p64c; /* Total packets == 64 bytes */ | |
573 | uint fen_p65c; /* Total packets 64 < bytes <= 127 */ | |
574 | uint fen_p128c; /* Total packets 127 < bytes <= 255 */ | |
575 | uint fen_p256c; /* Total packets 256 < bytes <= 511 */ | |
576 | uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ | |
577 | uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ | |
578 | uint fen_cambuf; /* Internal CAM buffer poiner */ | |
579 | ushort fen_rfthr; /* Received frames threshold */ | |
580 | ushort fen_rfcnt; /* Received frames count */ | |
581 | } fcc_enet_t; | |
582 | ||
583 | /* FCC Event/Mask register as used by Ethernet. | |
584 | */ | |
585 | #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | |
586 | #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ | |
587 | #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ | |
588 | #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | |
589 | #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ | |
590 | #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ | |
591 | #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | |
592 | #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | |
593 | ||
594 | /* FCC Mode Register (FPSMR) as used by Ethernet. | |
595 | */ | |
596 | #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ | |
597 | #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ | |
598 | #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ | |
599 | #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ | |
600 | #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ | |
601 | #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ | |
602 | #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ | |
603 | #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ | |
604 | #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ | |
605 | #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ | |
606 | #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ | |
607 | #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ | |
608 | #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ | |
609 | ||
610 | /* IIC parameter RAM. | |
611 | */ | |
612 | typedef struct iic { | |
613 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | |
614 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | |
615 | u_char iic_rfcr; /* Rx function code */ | |
616 | u_char iic_tfcr; /* Tx function code */ | |
617 | ushort iic_mrblr; /* Max receive buffer length */ | |
618 | uint iic_rstate; /* Internal */ | |
619 | uint iic_rdp; /* Internal */ | |
620 | ushort iic_rbptr; /* Internal */ | |
621 | ushort iic_rbc; /* Internal */ | |
622 | uint iic_rxtmp; /* Internal */ | |
623 | uint iic_tstate; /* Internal */ | |
624 | uint iic_tdp; /* Internal */ | |
625 | ushort iic_tbptr; /* Internal */ | |
626 | ushort iic_tbc; /* Internal */ | |
627 | uint iic_txtmp; /* Internal */ | |
628 | } iic_t; | |
629 | ||
630 | /* SPI parameter RAM. | |
631 | */ | |
632 | typedef struct spi { | |
633 | ushort spi_rbase; /* Rx Buffer descriptor base address */ | |
634 | ushort spi_tbase; /* Tx Buffer descriptor base address */ | |
635 | u_char spi_rfcr; /* Rx function code */ | |
636 | u_char spi_tfcr; /* Tx function code */ | |
637 | ushort spi_mrblr; /* Max receive buffer length */ | |
638 | uint spi_rstate; /* Internal */ | |
639 | uint spi_rdp; /* Internal */ | |
640 | ushort spi_rbptr; /* Internal */ | |
641 | ushort spi_rbc; /* Internal */ | |
642 | uint spi_rxtmp; /* Internal */ | |
643 | uint spi_tstate; /* Internal */ | |
644 | uint spi_tdp; /* Internal */ | |
645 | ushort spi_tbptr; /* Internal */ | |
646 | ushort spi_tbc; /* Internal */ | |
647 | uint spi_txtmp; /* Internal */ | |
648 | uint spi_res; /* Tx temp. */ | |
649 | uint spi_res1[4]; /* SDMA temp. */ | |
650 | } spi_t; | |
651 | ||
652 | /* SPI Mode register. | |
653 | */ | |
654 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ | |
655 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ | |
656 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ | |
657 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ | |
658 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ | |
659 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ | |
660 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ | |
661 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ | |
662 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ | |
663 | ||
664 | #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) | |
665 | #define SPMODE_PM(x) ((x) &0xF) | |
666 | ||
667 | #define SPI_EB ((u_char)0x10) /* big endian byte order */ | |
668 | ||
669 | #define BD_IIC_START ((ushort)0x0400) | |
670 | ||
671 | /*----------------------------------------------------------------------- | |
672 | * CMXFCR - CMX FCC Clock Route Register 15-12 | |
673 | */ | |
674 | #define CMXFCR_FC1 0x40000000 /* FCC1 connection */ | |
675 | #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ | |
676 | #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ | |
677 | #define CMXFCR_FC2 0x00400000 /* FCC2 connection */ | |
678 | #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ | |
679 | #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ | |
680 | #define CMXFCR_FC3 0x00004000 /* FCC3 connection */ | |
681 | #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ | |
682 | #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ | |
683 | ||
684 | #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ | |
685 | #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ | |
686 | #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ | |
687 | #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ | |
688 | #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ | |
689 | #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ | |
690 | #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ | |
691 | #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ | |
692 | ||
693 | #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ | |
694 | #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ | |
695 | #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ | |
696 | #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ | |
697 | #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ | |
698 | #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ | |
699 | #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ | |
700 | #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ | |
701 | ||
702 | #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ | |
703 | #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ | |
704 | #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ | |
705 | #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ | |
706 | #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ | |
707 | #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ | |
708 | #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ | |
709 | #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ | |
710 | ||
711 | #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ | |
712 | #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ | |
713 | #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ | |
714 | #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ | |
715 | #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ | |
716 | #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ | |
717 | #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ | |
718 | #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ | |
719 | ||
720 | #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ | |
721 | #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ | |
722 | #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ | |
723 | #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ | |
724 | #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ | |
725 | #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ | |
726 | #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ | |
727 | #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ | |
728 | ||
729 | #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ | |
730 | #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ | |
731 | #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ | |
732 | #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ | |
733 | #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ | |
734 | #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ | |
735 | #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ | |
736 | #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ | |
737 | ||
738 | /*----------------------------------------------------------------------- | |
739 | * CMXSCR - CMX SCC Clock Route Register 15-14 | |
740 | */ | |
741 | #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ | |
742 | #define CMXSCR_SC1 0x40000000 /* SCC1 connection */ | |
743 | #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ | |
744 | #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ | |
745 | #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ | |
746 | #define CMXSCR_SC2 0x00400000 /* SCC2 connection */ | |
747 | #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ | |
748 | #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ | |
749 | #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ | |
750 | #define CMXSCR_SC3 0x00004000 /* SCC3 connection */ | |
751 | #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ | |
752 | #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ | |
753 | #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ | |
754 | #define CMXSCR_SC4 0x00000040 /* SCC4 connection */ | |
755 | #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ | |
756 | #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ | |
757 | ||
758 | #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ | |
759 | #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ | |
760 | #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ | |
761 | #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ | |
762 | #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ | |
763 | #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ | |
764 | #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ | |
765 | #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ | |
766 | ||
767 | #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ | |
768 | #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ | |
769 | #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ | |
770 | #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ | |
771 | #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ | |
772 | #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ | |
773 | #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ | |
774 | #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ | |
775 | ||
776 | #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ | |
777 | #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ | |
778 | #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ | |
779 | #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ | |
780 | #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ | |
781 | #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ | |
782 | #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ | |
783 | #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ | |
784 | ||
785 | #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ | |
786 | #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ | |
787 | #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ | |
788 | #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ | |
789 | #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ | |
790 | #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ | |
791 | #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ | |
792 | #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ | |
793 | ||
794 | #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ | |
795 | #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ | |
796 | #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ | |
797 | #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ | |
798 | #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ | |
799 | #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ | |
800 | #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ | |
801 | #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ | |
802 | ||
803 | #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ | |
804 | #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ | |
805 | #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ | |
806 | #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ | |
807 | #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ | |
808 | #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ | |
809 | #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ | |
810 | #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ | |
811 | ||
812 | #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ | |
813 | #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ | |
814 | #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ | |
815 | #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ | |
816 | #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ | |
817 | #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ | |
818 | #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ | |
819 | #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ | |
820 | ||
821 | #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ | |
822 | #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ | |
823 | #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ | |
824 | #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ | |
825 | #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ | |
826 | #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ | |
827 | #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ | |
828 | #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ | |
829 | ||
830 | #endif /* __CPM_85XX__ */ |