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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 2/*
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3 * Copyright (C) 2004 IBM
4 *
5 * Implements the generic device dma API for powerpc.
6 * the pci and vio busses
1da177e4 7 */
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8#ifndef _ASM_DMA_MAPPING_H
9#define _ASM_DMA_MAPPING_H
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10#ifdef __KERNEL__
11
12#include <linux/types.h>
13#include <linux/cache.h>
14/* need struct page definitions */
15#include <linux/mm.h>
16#include <linux/scatterlist.h>
46bab4e4 17#include <linux/dma-debug.h>
33ff910f 18#include <asm/io.h>
ec3cf2ec 19#include <asm/swiotlb.h>
33ff910f 20
ec3cf2ec 21/* Some dma direct funcs must be visible for use in other dma_ops */
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22extern void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
23 dma_addr_t *dma_handle, gfp_t flag,
00085f1e 24 unsigned long attrs);
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25extern void __dma_direct_free_coherent(struct device *dev, size_t size,
26 void *vaddr, dma_addr_t dma_handle,
00085f1e 27 unsigned long attrs);
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28extern int dma_direct_mmap_coherent(struct device *dev,
29 struct vm_area_struct *vma,
30 void *cpu_addr, dma_addr_t handle,
00085f1e 31 size_t size, unsigned long attrs);
ec3cf2ec 32
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33#ifdef CONFIG_NOT_COHERENT_CACHE
34/*
35 * DMA-consistent mapping functions for PowerPCs that don't support
36 * cache snooping. These allocate/free a region of uncached mapped
37 * memory space for use with DMA devices. Alternatively, you could
38 * allocate the space "normally" and use the cache management functions
39 * to ensure it is consistent.
40 */
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41struct device;
42extern void *__dma_alloc_coherent(struct device *dev, size_t size,
43 dma_addr_t *handle, gfp_t gfp);
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44extern void __dma_free_coherent(size_t size, void *vaddr);
45extern void __dma_sync(void *vaddr, size_t size, int direction);
46extern void __dma_sync_page(struct page *page, unsigned long offset,
47 size_t size, int direction);
6090912c 48extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr);
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49
50#else /* ! CONFIG_NOT_COHERENT_CACHE */
51/*
52 * Cache coherent cores.
53 */
54
8b31e49d 55#define __dma_alloc_coherent(dev, gfp, size, handle) NULL
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56#define __dma_free_coherent(size, addr) ((void)0)
57#define __dma_sync(addr, size, rw) ((void)0)
58#define __dma_sync_page(pg, off, sz, rw) ((void)0)
59
60#endif /* ! CONFIG_NOT_COHERENT_CACHE */
61
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62static inline unsigned long device_to_mask(struct device *dev)
63{
64 if (dev->dma_mask && *dev->dma_mask)
65 return *dev->dma_mask;
66 /* Assume devices without mask can take 32 bit addresses */
67 return 0xfffffffful;
68}
69
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70/*
71 * Available generic sets of operations
72 */
73#ifdef CONFIG_PPC64
45223c54 74extern struct dma_map_ops dma_iommu_ops;
4fc665b8 75#endif
5299709d 76extern const struct dma_map_ops dma_direct_ops;
4fc665b8 77
815dd187 78static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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79{
80 /* We don't handle the NULL dev case for ISA for now. We could
81 * do it via an out of line call but it is not needed for now. The
82 * only ISA DMA device we support is the floppy and we have a hack
83 * in the floppy driver directly to get a device for us.
84 */
815dd187 85 return NULL;
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86}
87
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88/*
89 * get_dma_offset()
90 *
91 * Get the dma offset on configurations where the dma address can be determined
92 * from the physical address by looking at a simple offset. Direct dma and
93 * swiotlb use this function, but it is typically not used by implementations
94 * with an iommu.
95 */
738ef42e 96static inline dma_addr_t get_dma_offset(struct device *dev)
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97{
98 if (dev)
2db4928b 99 return dev->archdata.dma_offset;
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100
101 return PCI_DRAM_OFFSET;
102}
103
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104static inline void set_dma_offset(struct device *dev, dma_addr_t off)
105{
106 if (dev)
2db4928b 107 dev->archdata.dma_offset = off;
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108}
109
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110/* this will be removed soon */
111#define flush_write_buffers()
112
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113#define HAVE_ARCH_DMA_SET_MASK 1
114extern int dma_set_mask(struct device *dev, u64 dma_mask);
115
fe7e85c6 116extern u64 __dma_get_required_mask(struct device *dev);
33ff910f 117
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118static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
119{
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120#ifdef CONFIG_SWIOTLB
121 struct dev_archdata *sd = &dev->archdata;
9a937c91 122
762afb73 123 if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr)
acdb6685 124 return false;
762afb73 125#endif
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126
127 if (!dev->dma_mask)
acdb6685 128 return false;
9a937c91 129
ac2b3e67 130 return addr + size - 1 <= *dev->dma_mask;
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131}
132
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133static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
134{
1cebd7a0 135 return paddr + get_dma_offset(dev);
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136}
137
138static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
139{
1cebd7a0 140 return daddr - get_dma_offset(dev);
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141}
142
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143#define ARCH_HAS_DMA_MMAP_COHERENT
144
d3fa72e4 145static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
78b09735 146 enum dma_data_direction direction)
1da177e4 147{
78b09735 148 BUG_ON(direction == DMA_NONE);
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149 __dma_sync(vaddr, size, (int)direction);
150}
151
88ced031 152#endif /* __KERNEL__ */
78b09735 153#endif /* _ASM_DMA_MAPPING_H */