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f046ccd1 EL |
1 | /* |
2 | * Copyright 2004 Freescale Semiconductor, Inc. | |
3 | * Liberty Eran (liberty@freescale.com) | |
4 | */ | |
5 | ||
6 | #ifndef __E300_H__ | |
7 | #define __E300_H__ | |
8 | ||
95e7ef89 SW |
9 | #define PVR_E300C1 0x80830000 |
10 | #define PVR_E300C2 0x80840000 | |
11 | #define PVR_E300C3 0x80850000 | |
8993e54b | 12 | #define PVR_E300C4 0x80860000 |
24c3aca3 | 13 | |
f046ccd1 EL |
14 | /* |
15 | * Hardware Implementation-Dependent Register 0 (HID0) | |
16 | */ | |
de1d0a69 | 17 | |
f046ccd1 | 18 | /* #define HID0 1008 already defined in processor.h */ |
53677ef1 WD |
19 | #define HID0_MASK_MACHINE_CHECK 0x00000000 |
20 | #define HID0_ENABLE_MACHINE_CHECK 0x80000000 | |
f046ccd1 | 21 | |
53677ef1 WD |
22 | #define HID0_DISABLE_CACHE_PARITY 0x00000000 |
23 | #define HID0_ENABLE_CACHE_PARITY 0x40000000 | |
f046ccd1 | 24 | |
53677ef1 WD |
25 | #define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ |
26 | #define HID0_ENABLE_ADDRESS_PARITY 0x20000000 | |
f046ccd1 | 27 | |
53677ef1 WD |
28 | #define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ |
29 | #define HID0_ENABLE_DATE_PARITY 0x10000000 | |
f046ccd1 | 30 | |
53677ef1 WD |
31 | #define HID0_CORE_CLK_OUT 0x00000000 |
32 | #define HID0_CORE_CLK_OUT_DIV_2 0x08000000 | |
f046ccd1 EL |
33 | |
34 | #define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ | |
35 | #define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 | |
36 | ||
53677ef1 WD |
37 | #define HID0_DISABLE_DOSE_MODE 0x00000000 |
38 | #define HID0_ENABLE_DOSE_MODE 0x00800000 | |
f046ccd1 | 39 | |
53677ef1 WD |
40 | #define HID0_DISABLE_NAP_MODE 0x00000000 |
41 | #define HID0_ENABLE_NAP_MODE 0x00400000 | |
f046ccd1 | 42 | |
53677ef1 WD |
43 | #define HID0_DISABLE_SLEEP_MODE 0x00000000 |
44 | #define HID0_ENABLE_SLEEP_MODE 0x00200000 | |
f046ccd1 EL |
45 | |
46 | #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 | |
47 | #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 | |
48 | ||
53677ef1 | 49 | #define HID0_SOFT_RESET 0x00010000 |
f046ccd1 | 50 | |
53677ef1 WD |
51 | #define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 |
52 | #define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 | |
f046ccd1 | 53 | |
53677ef1 WD |
54 | #define HID0_DISABLE_DATA_CACHE 0x00000000 |
55 | #define HID0_ENABLE_DATA_CACHE 0x00004000 | |
f046ccd1 | 56 | |
53677ef1 | 57 | #define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 |
f046ccd1 | 58 | |
53677ef1 | 59 | #define HID0_LOCK_DATA_CACHE 0x00001000 |
f046ccd1 EL |
60 | |
61 | #define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 | |
62 | ||
53677ef1 | 63 | #define HID0_INVALIDATE_DATA_CACHE 0x00000400 |
f046ccd1 | 64 | |
53677ef1 WD |
65 | #define HID0_DISABLE_M_BIT 0x00000000 |
66 | #define HID0_ENABLE_M_BIT 0x00000080 | |
f046ccd1 | 67 | |
53677ef1 | 68 | #define HID0_FBIOB 0x00000010 |
f046ccd1 | 69 | |
53677ef1 WD |
70 | #define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 |
71 | #define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 | |
f046ccd1 EL |
72 | |
73 | #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 | |
74 | #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 | |
75 | ||
76 | /* | |
77 | * Hardware Implementation-Dependent Register 2 (HID2) | |
78 | */ | |
79 | #define HID2 1011 | |
80 | ||
81 | #define HID2_LET 0x08000000 | |
82 | #define HID2_HBE 0x00040000 | |
83 | #define HID2_IWLCK_000 0x00000000 /* no ways locked */ | |
84 | #define HID2_IWLCK_001 0x00002000 /* way 0 locked */ | |
85 | #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */ | |
86 | #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */ | |
87 | #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */ | |
88 | #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ | |
89 | #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ | |
90 | ||
f046ccd1 | 91 | #endif /* __E300_H__ */ |