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powerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB
[people/ms/u-boot.git] / arch / powerpc / include / asm / fsl_ddr_sdram.h
CommitLineData
58e5e9af 1/*
3dbd5d7d 2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
58e5e9af
KG		 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#ifndef FSL_DDR_MEMCTL_H
10#define FSL_DDR_MEMCTL_H
11
12/*
13 * Pick a basic DDR Technology.
14 */
15#include <ddr_spd.h>
16
17#define SDRAM_TYPE_DDR1 2
18#define SDRAM_TYPE_DDR2 3
19#define SDRAM_TYPE_LPDDR1 6
20#define SDRAM_TYPE_DDR3 7
21
c360ceac
DL		 22#define DDR_BL4 4 /* burst length 4 */
23#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
24#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
25#define DDR_BL8 8 /* burst length 8 */
26
e1fd16b6 27#define DDR3_RTT_OFF 0
f8d05e5e
DL		 28#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
29#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
30#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
31#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
32#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
33
58e5e9af
KG		 34#if defined(CONFIG_FSL_DDR1)
35#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
36typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
37#ifndef CONFIG_FSL_SDRAM_TYPE
38#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
39#endif
40#elif defined(CONFIG_FSL_DDR2)
41#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
42typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
43#ifndef CONFIG_FSL_SDRAM_TYPE
44#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
45#endif
46#elif defined(CONFIG_FSL_DDR3)
47#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
48typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
22ff3d01
DL		 49#ifndef CONFIG_FSL_SDRAM_TYPE
50#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
58e5e9af 51#endif
22ff3d01 52#endif /* #if defined(CONFIG_FSL_DDR1) */
58e5e9af 53
e1fd16b6
YS		 54#define FSL_DDR_ODT_NEVER 0x0
55#define FSL_DDR_ODT_CS 0x1
56#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
57#define FSL_DDR_ODT_OTHER_DIMM 0x3
58#define FSL_DDR_ODT_ALL 0x4
59#define FSL_DDR_ODT_SAME_DIMM 0x5
60#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
61#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
62
dbbbb3ab
HW		 63/* define bank(chip select) interleaving mode */
64#define FSL_DDR_CS0_CS1 0x40
65#define FSL_DDR_CS2_CS3 0x20
66#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
67#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
68
69/* define memory controller interleaving mode */
70#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
71#define FSL_DDR_PAGE_INTERLEAVING 0x1
72#define FSL_DDR_BANK_INTERLEAVING 0x2
73#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
74
e1be0d25
P		 75/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
76 */
77#define SDRAM_CFG_MEM_EN 0x80000000
78#define SDRAM_CFG_SREN 0x40000000
79#define SDRAM_CFG_ECC_EN 0x20000000
80#define SDRAM_CFG_RD_EN 0x10000000
81#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
82#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
83#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
84#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
85#define SDRAM_CFG_DYN_PWR 0x00200000
86#define SDRAM_CFG_32_BE 0x00080000
87#define SDRAM_CFG_8_BE 0x00040000
88#define SDRAM_CFG_NCAP 0x00020000
89#define SDRAM_CFG_2T_EN 0x00008000
90#define SDRAM_CFG_BI 0x00000001
91
91671913
YS		 92#define SDRAM_CFG2_D_INIT 0x00000010
93#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
94
95#define TIMING_CFG_2_CPO_MASK 0x0F800000
96
c360ceac
DL		 97#if defined(CONFIG_P4080)
98#define RD_TO_PRE_MASK 0xf
99#define RD_TO_PRE_SHIFT 13
100#define WR_DATA_DELAY_MASK 0xf
101#define WR_DATA_DELAY_SHIFT 9
102#else
103#define RD_TO_PRE_MASK 0x7
104#define RD_TO_PRE_SHIFT 13
105#define WR_DATA_DELAY_MASK 0x7
106#define WR_DATA_DELAY_SHIFT 10
107#endif
108
fa8d23c0
YS		 109/* DDR_MD_CNTL */
110#define MD_CNTL_MD_EN 0x80000000
111#define MD_CNTL_CS_SEL_CS0 0x00000000
112#define MD_CNTL_CS_SEL_CS1 0x10000000
113#define MD_CNTL_CS_SEL_CS2 0x20000000
114#define MD_CNTL_CS_SEL_CS3 0x30000000
115#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
116#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
117#define MD_CNTL_MD_SEL_MR 0x00000000
118#define MD_CNTL_MD_SEL_EMR 0x01000000
119#define MD_CNTL_MD_SEL_EMR2 0x02000000
120#define MD_CNTL_MD_SEL_EMR3 0x03000000
121#define MD_CNTL_SET_REF 0x00800000
122#define MD_CNTL_SET_PRE 0x00400000
123#define MD_CNTL_CKE_CNTL_LOW 0x00100000
124#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
125#define MD_CNTL_WRCW 0x00080000
126#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
127
6b06d7dc
YS		 128/* DDR_CDR1 */
129#define DDR_CDR1_DHC_EN 0x80000000
130
58e5e9af
KG		 131/* Record of register values computed */
132typedef struct fsl_ddr_cfg_regs_s {
133 struct {
134 unsigned int bnds;
135 unsigned int config;
136 unsigned int config_2;
137 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
138 unsigned int timing_cfg_3;
139 unsigned int timing_cfg_0;
140 unsigned int timing_cfg_1;
141 unsigned int timing_cfg_2;
142 unsigned int ddr_sdram_cfg;
143 unsigned int ddr_sdram_cfg_2;
144 unsigned int ddr_sdram_mode;
145 unsigned int ddr_sdram_mode_2;
e1fd16b6
YS		 146 unsigned int ddr_sdram_mode_3;
147 unsigned int ddr_sdram_mode_4;
148 unsigned int ddr_sdram_mode_5;
149 unsigned int ddr_sdram_mode_6;
150 unsigned int ddr_sdram_mode_7;
151 unsigned int ddr_sdram_mode_8;
58e5e9af
KG		 152 unsigned int ddr_sdram_md_cntl;
153 unsigned int ddr_sdram_interval;
154 unsigned int ddr_data_init;
155 unsigned int ddr_sdram_clk_cntl;
156 unsigned int ddr_init_addr;
157 unsigned int ddr_init_ext_addr;
158 unsigned int timing_cfg_4;
159 unsigned int timing_cfg_5;
160 unsigned int ddr_zq_cntl;
161 unsigned int ddr_wrlvl_cntl;
58e5e9af
KG		 162 unsigned int ddr_sr_cntr;
163 unsigned int ddr_sdram_rcw_1;
164 unsigned int ddr_sdram_rcw_2;
7fd101c9 165 unsigned int ddr_eor;
d2a9568c
YS		 166 unsigned int ddr_cdr1;
167 unsigned int ddr_cdr2;
168 unsigned int err_disable;
169 unsigned int err_int_en;
170 unsigned int debug[32];
58e5e9af
KG		 171} fsl_ddr_cfg_regs_t;
172
173typedef struct memctl_options_partial_s {
174 unsigned int all_DIMMs_ECC_capable;
175 unsigned int all_DIMMs_tCKmax_ps;
176 unsigned int all_DIMMs_burst_lengths_bitmask;
177 unsigned int all_DIMMs_registered;
178 unsigned int all_DIMMs_unbuffered;
179 /* unsigned int lowest_common_SPD_caslat; */
180 unsigned int all_DIMMs_minimum_tRCD_ps;
181} memctl_options_partial_t;
182
183/*
184 * Generalized parameters for memory controller configuration,
185 * might be a little specific to the FSL memory controller
186 */
187typedef struct memctl_options_s {
188 /*
189 * Memory organization parameters
190 *
191 * if DIMM is present in the system
192 * where DIMMs are with respect to chip select
193 * where chip selects are with respect to memory boundaries
194 */
195 unsigned int registered_dimm_en; /* use registered DIMM support */
196
197 /* Options local to a Chip Select */
198 struct cs_local_opts_s {
199 unsigned int auto_precharge;
200 unsigned int odt_rd_cfg;
201 unsigned int odt_wr_cfg;
e1fd16b6
YS		 202 unsigned int odt_rtt_norm;
203 unsigned int odt_rtt_wr;
58e5e9af
KG		 204 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
205
206 /* Special configurations for chip select */
207 unsigned int memctl_interleaving;
208 unsigned int memctl_interleaving_mode;
209 unsigned int ba_intlv_ctl;
7fd101c9 210 unsigned int addr_hash;
58e5e9af
KG		 211
212 /* Operational mode parameters */
213 unsigned int ECC_mode; /* Use ECC? */
214 /* Initialize ECC using memory controller? */
215 unsigned int ECC_init_using_memctl;
216 unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
217 /* SREN - self-refresh during sleep */
218 unsigned int self_refresh_in_sleep;
219 unsigned int dynamic_power; /* DYN_PWR */
220 /* memory data width to use (16-bit, 32-bit, 64-bit) */
221 unsigned int data_bus_width;
c360ceac
DL		 222 unsigned int burst_length; /* BL4, OTF and BL8 */
223 /* On-The-Fly Burst Chop enable */
224 unsigned int OTF_burst_chop_en;
225 /* mirrior DIMMs for DDR3 */
226 unsigned int mirrored_dimm;
5800e7ab 227 unsigned int quad_rank_present;
d2a9568c 228 unsigned int ap_en; /* address parity enable for RDIMM */
58e5e9af
KG		 229
230 /* Global Timing Parameters */
231 unsigned int cas_latency_override;
232 unsigned int cas_latency_override_value;
233 unsigned int use_derated_caslat;
234 unsigned int additive_latency_override;
235 unsigned int additive_latency_override_value;
236
237 unsigned int clk_adjust; /* */
238 unsigned int cpo_override;
239 unsigned int write_data_delay; /* DQS adjust */
bdc9f7b5
DL		 240
241 unsigned int wrlvl_override;
242 unsigned int wrlvl_sample; /* Write leveling */
243 unsigned int wrlvl_start;
244
58e5e9af
KG		 245 unsigned int half_strength_driver_enable;
246 unsigned int twoT_en;
247 unsigned int threeT_en;
248 unsigned int bstopre;
249 unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
250 unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
22cca7e1 251
c360ceac
DL		 252 /* Rtt impedance */
253 unsigned int rtt_override; /* rtt_override enable */
254 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
1aa3d08a 255 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
c360ceac 256
22cca7e1
DL		 257 /* Automatic self refresh */
258 unsigned int auto_self_refresh_en;
259 unsigned int sr_it;
c360ceac
DL		 260 /* ZQ calibration */
261 unsigned int zq_en;
262 /* Write leveling */
263 unsigned int wrlvl_en;
d2a9568c
YS		 264 /* RCW override for RDIMM */
265 unsigned int rcw_override;
266 unsigned int rcw_1;
267 unsigned int rcw_2;
268 /* control register 1 */
269 unsigned int ddr_cdr1;
58e5e9af
KG		 270} memctl_options_t;
271
272extern phys_size_t fsl_ddr_sdram(void);
3dbd5d7d 273extern int fsl_use_spd(void);
f0f89943
KG		 274extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
275 unsigned int ctrl_num);
28a96671 276
38dba0c2
BB		 277/*
278 * The 85xx boards have a common prototype for fixed_sdram so put the
279 * declaration here.
280 */
281#ifdef CONFIG_MPC85xx
282extern phys_size_t fixed_sdram(void);
283#endif
284
285#if defined(CONFIG_DDR_ECC)
286extern void ddr_enable_ecc(unsigned int dram_size);
287#endif
288
289
28a96671
YS		 290typedef struct fixed_ddr_parm{
291 int min_freq;
292 int max_freq;
293 fsl_ddr_cfg_regs_t *ddr_settings;
294} fixed_ddr_parm_t;
58e5e9af 295#endif
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