[people/ms/u-boot.git] / arch / powerpc / include / asm / fsl_ddr_sdram.h

/*
 * Copyright 2008-2011 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 */

#ifndef FSL_DDR_MEMCTL_H
#define FSL_DDR_MEMCTL_H

/*
 * Pick a basic DDR Technology.
 */
#include <ddr_spd.h>

#define SDRAM_TYPE_DDR1    2
#define SDRAM_TYPE_DDR2    3
#define SDRAM_TYPE_LPDDR1  6
#define SDRAM_TYPE_DDR3    7

#define DDR_BL4		4	/* burst length 4 */
#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
#define DDR_BL8		8	/* burst length 8 */

#define DDR3_RTT_OFF		0
#define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
#define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
#define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
#define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
#define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */

#if defined(CONFIG_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
#endif
#elif defined(CONFIG_FSL_DDR2)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
#endif
#elif defined(CONFIG_FSL_DDR3)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
#endif
#endif	/* #if defined(CONFIG_FSL_DDR1) */

#define FSL_DDR_ODT_NEVER		0x0
#define FSL_DDR_ODT_CS			0x1
#define FSL_DDR_ODT_ALL_OTHER_CS	0x2
#define FSL_DDR_ODT_OTHER_DIMM		0x3
#define FSL_DDR_ODT_ALL			0x4
#define FSL_DDR_ODT_SAME_DIMM		0x5
#define FSL_DDR_ODT_CS_AND_OTHER_DIMM	0x6
#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM	0x7

/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1			0x40
#define FSL_DDR_CS2_CS3			0x20
#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)

/* define memory controller interleaving mode */
#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
#define FSL_DDR_PAGE_INTERLEAVING	0x1
#define FSL_DDR_BANK_INTERLEAVING	0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3

/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
 */
#define SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG_SREN			0x40000000
#define SDRAM_CFG_ECC_EN		0x20000000
#define SDRAM_CFG_RD_EN			0x10000000
#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
#define SDRAM_CFG_DYN_PWR		0x00200000
#define SDRAM_CFG_32_BE			0x00080000
#define SDRAM_CFG_16_BE			0x00100000
#define SDRAM_CFG_8_BE			0x00040000
#define SDRAM_CFG_NCAP			0x00020000
#define SDRAM_CFG_2T_EN			0x00008000
#define SDRAM_CFG_BI			0x00000001

#define SDRAM_CFG2_D_INIT		0x00000010
#define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
#define SDRAM_CFG2_ODT_NEVER		0
#define SDRAM_CFG2_ODT_ONLY_WRITE	1
#define SDRAM_CFG2_ODT_ONLY_READ	2
#define SDRAM_CFG2_ODT_ALWAYS		3

#define TIMING_CFG_2_CPO_MASK	0x0F800000

#if defined(CONFIG_P4080)
#define RD_TO_PRE_MASK		0xf
#define RD_TO_PRE_SHIFT		13
#define WR_DATA_DELAY_MASK	0xf
#define WR_DATA_DELAY_SHIFT	9
#else
#define RD_TO_PRE_MASK		0x7
#define RD_TO_PRE_SHIFT		13
#define WR_DATA_DELAY_MASK	0x7
#define WR_DATA_DELAY_SHIFT	10
#endif

/* DDR_MD_CNTL */
#define MD_CNTL_MD_EN		0x80000000
#define MD_CNTL_CS_SEL_CS0	0x00000000
#define MD_CNTL_CS_SEL_CS1	0x10000000
#define MD_CNTL_CS_SEL_CS2	0x20000000
#define MD_CNTL_CS_SEL_CS3	0x30000000
#define MD_CNTL_CS_SEL_CS0_CS1	0x40000000
#define MD_CNTL_CS_SEL_CS2_CS3	0x50000000
#define MD_CNTL_MD_SEL_MR	0x00000000
#define MD_CNTL_MD_SEL_EMR	0x01000000
#define MD_CNTL_MD_SEL_EMR2	0x02000000
#define MD_CNTL_MD_SEL_EMR3	0x03000000
#define MD_CNTL_SET_REF		0x00800000
#define MD_CNTL_SET_PRE		0x00400000
#define MD_CNTL_CKE_CNTL_LOW	0x00100000
#define MD_CNTL_CKE_CNTL_HIGH	0x00200000
#define MD_CNTL_WRCW		0x00080000
#define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)

/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN	0x80000000

/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
	struct {
		unsigned int bnds;
		unsigned int config;
		unsigned int config_2;
	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
	unsigned int timing_cfg_3;
	unsigned int timing_cfg_0;
	unsigned int timing_cfg_1;
	unsigned int timing_cfg_2;
	unsigned int ddr_sdram_cfg;
	unsigned int ddr_sdram_cfg_2;
	unsigned int ddr_sdram_mode;
	unsigned int ddr_sdram_mode_2;
	unsigned int ddr_sdram_mode_3;
	unsigned int ddr_sdram_mode_4;
	unsigned int ddr_sdram_mode_5;
	unsigned int ddr_sdram_mode_6;
	unsigned int ddr_sdram_mode_7;
	unsigned int ddr_sdram_mode_8;
	unsigned int ddr_sdram_md_cntl;
	unsigned int ddr_sdram_interval;
	unsigned int ddr_data_init;
	unsigned int ddr_sdram_clk_cntl;
	unsigned int ddr_init_addr;
	unsigned int ddr_init_ext_addr;
	unsigned int timing_cfg_4;
	unsigned int timing_cfg_5;
	unsigned int ddr_zq_cntl;
	unsigned int ddr_wrlvl_cntl;
	unsigned int ddr_sr_cntr;
	unsigned int ddr_sdram_rcw_1;
	unsigned int ddr_sdram_rcw_2;
	unsigned int ddr_eor;
	unsigned int ddr_cdr1;
	unsigned int ddr_cdr2;
	unsigned int err_disable;
	unsigned int err_int_en;
	unsigned int debug[32];
} fsl_ddr_cfg_regs_t;

typedef struct memctl_options_partial_s {
	unsigned int all_DIMMs_ECC_capable;
	unsigned int all_DIMMs_tCKmax_ps;
	unsigned int all_DIMMs_burst_lengths_bitmask;
	unsigned int all_DIMMs_registered;
	unsigned int all_DIMMs_unbuffered;
	/*	unsigned int lowest_common_SPD_caslat; */
	unsigned int all_DIMMs_minimum_tRCD_ps;
} memctl_options_partial_t;

#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
/*
 * Generalized parameters for memory controller configuration,
 * might be a little specific to the FSL memory controller
 */
typedef struct memctl_options_s {
	/*
	 * Memory organization parameters
	 *
	 * if DIMM is present in the system
	 * where DIMMs are with respect to chip select
	 * where chip selects are with respect to memory boundaries
	 */
	unsigned int registered_dimm_en;    /* use registered DIMM support */

	/* Options local to a Chip Select */
	struct cs_local_opts_s {
		unsigned int auto_precharge;
		unsigned int odt_rd_cfg;
		unsigned int odt_wr_cfg;
		unsigned int odt_rtt_norm;
		unsigned int odt_rtt_wr;
	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];

	/* Special configurations for chip select */
	unsigned int memctl_interleaving;
	unsigned int memctl_interleaving_mode;
	unsigned int ba_intlv_ctl;
	unsigned int addr_hash;

	/* Operational mode parameters */
	unsigned int ECC_mode;	 /* Use ECC? */
	/* Initialize ECC using memory controller? */
	unsigned int ECC_init_using_memctl;
	unsigned int DQS_config;	/* Use DQS? maybe only with DDR2? */
	/* SREN - self-refresh during sleep */
	unsigned int self_refresh_in_sleep;
	unsigned int dynamic_power;	/* DYN_PWR */
	/* memory data width to use (16-bit, 32-bit, 64-bit) */
	unsigned int data_bus_width;
	unsigned int burst_length;	/* BL4, OTF and BL8 */
	/* On-The-Fly Burst Chop enable */
	unsigned int OTF_burst_chop_en;
	/* mirrior DIMMs for DDR3 */
	unsigned int mirrored_dimm;
	unsigned int quad_rank_present;
	unsigned int ap_en;	/* address parity enable for RDIMM */

	/* Global Timing Parameters */
	unsigned int cas_latency_override;
	unsigned int cas_latency_override_value;
	unsigned int use_derated_caslat;
	unsigned int additive_latency_override;
	unsigned int additive_latency_override_value;

	unsigned int clk_adjust;		/* */
	unsigned int cpo_override;
	unsigned int write_data_delay;		/* DQS adjust */

	unsigned int wrlvl_override;
	unsigned int wrlvl_sample;		/* Write leveling */
	unsigned int wrlvl_start;

	unsigned int half_strength_driver_enable;
	unsigned int twoT_en;
	unsigned int threeT_en;
	unsigned int bstopre;
	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
	unsigned int tFAW_window_four_activates_ps;	/* tFAW --  FOUR_ACT */

	/* Rtt impedance */
	unsigned int rtt_override;		/* rtt_override enable */
	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
	unsigned int rtt_wr_override_value;	/* this is Rtt_WR for DDR3 */

	/* Automatic self refresh */
	unsigned int auto_self_refresh_en;
	unsigned int sr_it;
	/* ZQ calibration */
	unsigned int zq_en;
	/* Write leveling */
	unsigned int wrlvl_en;
	/* RCW override for RDIMM */
	unsigned int rcw_override;
	unsigned int rcw_1;
	unsigned int rcw_2;
	/* control register 1 */
	unsigned int ddr_cdr1;

	unsigned int trwt_override;
	unsigned int trwt;			/* read-to-write turnaround */
} memctl_options_t;

extern phys_size_t fsl_ddr_sdram(void);
extern phys_size_t fsl_ddr_sdram_size(void);
extern int fsl_use_spd(void);
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
					unsigned int ctrl_num);

/*
 * The 85xx boards have a common prototype for fixed_sdram so put the
 * declaration here.
 */
#ifdef CONFIG_MPC85xx
extern phys_size_t fixed_sdram(void);
#endif

#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif


typedef struct fixed_ddr_parm{
	int min_freq;
	int max_freq;
	fsl_ddr_cfg_regs_t *ddr_settings;
} fixed_ddr_parm_t;
#endif
Commit	Line	Data
58e5e9af	1	/*
3dbd5d7d	2	* Copyright 2008-2011 Freescale Semiconductor, Inc.
58e5e9af KG	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* Version 2 as published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef FSL_DDR_MEMCTL_H
	10	#define FSL_DDR_MEMCTL_H
	11
	12	/*
	13	* Pick a basic DDR Technology.
	14	*/
	15	#include <ddr_spd.h>
	16
	17	#define SDRAM_TYPE_DDR1 2
	18	#define SDRAM_TYPE_DDR2 3
	19	#define SDRAM_TYPE_LPDDR1 6
	20	#define SDRAM_TYPE_DDR3 7
	21
c360ceac DL	22	#define DDR_BL4 4 /* burst length 4 */
	23	#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
	24	#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
	25	#define DDR_BL8 8 /* burst length 8 */
	26
e1fd16b6	27	#define DDR3_RTT_OFF 0
f8d05e5e DL	28	#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
	29	#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
	30	#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
	31	#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
	32	#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
	33
58e5e9af KG	34	#if defined(CONFIG_FSL_DDR1)
	35	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
	36	typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
	37	#ifndef CONFIG_FSL_SDRAM_TYPE
	38	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
	39	#endif
	40	#elif defined(CONFIG_FSL_DDR2)
	41	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
	42	typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
	43	#ifndef CONFIG_FSL_SDRAM_TYPE
	44	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
	45	#endif
	46	#elif defined(CONFIG_FSL_DDR3)
	47	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
	48	typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
22ff3d01 DL	49	#ifndef CONFIG_FSL_SDRAM_TYPE
22ff3d01 DL	50	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
58e5e9af	51	#endif
22ff3d01	52	#endif /* #if defined(CONFIG_FSL_DDR1) */
58e5e9af	53
e1fd16b6 YS	54	#define FSL_DDR_ODT_NEVER 0x0
	55	#define FSL_DDR_ODT_CS 0x1
	56	#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
	57	#define FSL_DDR_ODT_OTHER_DIMM 0x3
	58	#define FSL_DDR_ODT_ALL 0x4
	59	#define FSL_DDR_ODT_SAME_DIMM 0x5
	60	#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
	61	#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
	62
dbbbb3ab HW	63	/* define bank(chip select) interleaving mode */
	64	#define FSL_DDR_CS0_CS1 0x40
	65	#define FSL_DDR_CS2_CS3 0x20
	66	#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 \| FSL_DDR_CS2_CS3)
	67	#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 \| 0x04)
	68
	69	/* define memory controller interleaving mode */
	70	#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
	71	#define FSL_DDR_PAGE_INTERLEAVING 0x1
	72	#define FSL_DDR_BANK_INTERLEAVING 0x2
	73	#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
	74
e1be0d25 P	75	/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
	76	*/
	77	#define SDRAM_CFG_MEM_EN 0x80000000
	78	#define SDRAM_CFG_SREN 0x40000000
	79	#define SDRAM_CFG_ECC_EN 0x20000000
	80	#define SDRAM_CFG_RD_EN 0x10000000
	81	#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
	82	#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
	83	#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
	84	#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
	85	#define SDRAM_CFG_DYN_PWR 0x00200000
	86	#define SDRAM_CFG_32_BE 0x00080000
0b3b1766	87	#define SDRAM_CFG_16_BE 0x00100000
e1be0d25 P	88	#define SDRAM_CFG_8_BE 0x00040000
	89	#define SDRAM_CFG_NCAP 0x00020000
	90	#define SDRAM_CFG_2T_EN 0x00008000
	91	#define SDRAM_CFG_BI 0x00000001
	92
91671913 YS	93	#define SDRAM_CFG2_D_INIT 0x00000010
91671913 YS	94	#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
cae7c1b5 YS	95	#define SDRAM_CFG2_ODT_NEVER 0
	96	#define SDRAM_CFG2_ODT_ONLY_WRITE 1
	97	#define SDRAM_CFG2_ODT_ONLY_READ 2
	98	#define SDRAM_CFG2_ODT_ALWAYS 3
91671913 YS	99
	100	#define TIMING_CFG_2_CPO_MASK 0x0F800000
	101
c360ceac DL	102	#if defined(CONFIG_P4080)
	103	#define RD_TO_PRE_MASK 0xf
	104	#define RD_TO_PRE_SHIFT 13
	105	#define WR_DATA_DELAY_MASK 0xf
	106	#define WR_DATA_DELAY_SHIFT 9
	107	#else
	108	#define RD_TO_PRE_MASK 0x7
	109	#define RD_TO_PRE_SHIFT 13
	110	#define WR_DATA_DELAY_MASK 0x7
	111	#define WR_DATA_DELAY_SHIFT 10
	112	#endif
	113
fa8d23c0 YS	114	/* DDR_MD_CNTL */
	115	#define MD_CNTL_MD_EN 0x80000000
	116	#define MD_CNTL_CS_SEL_CS0 0x00000000
	117	#define MD_CNTL_CS_SEL_CS1 0x10000000
	118	#define MD_CNTL_CS_SEL_CS2 0x20000000
	119	#define MD_CNTL_CS_SEL_CS3 0x30000000
	120	#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
	121	#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
	122	#define MD_CNTL_MD_SEL_MR 0x00000000
	123	#define MD_CNTL_MD_SEL_EMR 0x01000000
	124	#define MD_CNTL_MD_SEL_EMR2 0x02000000
	125	#define MD_CNTL_MD_SEL_EMR3 0x03000000
	126	#define MD_CNTL_SET_REF 0x00800000
	127	#define MD_CNTL_SET_PRE 0x00400000
	128	#define MD_CNTL_CKE_CNTL_LOW 0x00100000
	129	#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
	130	#define MD_CNTL_WRCW 0x00080000
	131	#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
	132
6b06d7dc YS	133	/* DDR_CDR1 */
	134	#define DDR_CDR1_DHC_EN 0x80000000
	135
58e5e9af KG	136	/* Record of register values computed */
	137	typedef struct fsl_ddr_cfg_regs_s {
	138	struct {
	139	unsigned int bnds;
	140	unsigned int config;
	141	unsigned int config_2;
	142	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
	143	unsigned int timing_cfg_3;
	144	unsigned int timing_cfg_0;
	145	unsigned int timing_cfg_1;
	146	unsigned int timing_cfg_2;
	147	unsigned int ddr_sdram_cfg;
	148	unsigned int ddr_sdram_cfg_2;
	149	unsigned int ddr_sdram_mode;
	150	unsigned int ddr_sdram_mode_2;
e1fd16b6 YS	151	unsigned int ddr_sdram_mode_3;
	152	unsigned int ddr_sdram_mode_4;
	153	unsigned int ddr_sdram_mode_5;
	154	unsigned int ddr_sdram_mode_6;
	155	unsigned int ddr_sdram_mode_7;
	156	unsigned int ddr_sdram_mode_8;
58e5e9af KG	157	unsigned int ddr_sdram_md_cntl;
	158	unsigned int ddr_sdram_interval;
	159	unsigned int ddr_data_init;
	160	unsigned int ddr_sdram_clk_cntl;
	161	unsigned int ddr_init_addr;
	162	unsigned int ddr_init_ext_addr;
	163	unsigned int timing_cfg_4;
	164	unsigned int timing_cfg_5;
	165	unsigned int ddr_zq_cntl;
	166	unsigned int ddr_wrlvl_cntl;
58e5e9af KG	167	unsigned int ddr_sr_cntr;
	168	unsigned int ddr_sdram_rcw_1;
	169	unsigned int ddr_sdram_rcw_2;
7fd101c9	170	unsigned int ddr_eor;
d2a9568c YS	171	unsigned int ddr_cdr1;
	172	unsigned int ddr_cdr2;
	173	unsigned int err_disable;
	174	unsigned int err_int_en;
	175	unsigned int debug[32];
58e5e9af KG	176	} fsl_ddr_cfg_regs_t;
	177
	178	typedef struct memctl_options_partial_s {
	179	unsigned int all_DIMMs_ECC_capable;
	180	unsigned int all_DIMMs_tCKmax_ps;
	181	unsigned int all_DIMMs_burst_lengths_bitmask;
	182	unsigned int all_DIMMs_registered;
	183	unsigned int all_DIMMs_unbuffered;
	184	/* unsigned int lowest_common_SPD_caslat; */
	185	unsigned int all_DIMMs_minimum_tRCD_ps;
	186	} memctl_options_partial_t;
	187
51d498f1 YS	188	#define DDR_DATA_BUS_WIDTH_64 0
	189	#define DDR_DATA_BUS_WIDTH_32 1
	190	#define DDR_DATA_BUS_WIDTH_16 2
58e5e9af KG	191	/*
	192	* Generalized parameters for memory controller configuration,
	193	* might be a little specific to the FSL memory controller
	194	*/
	195	typedef struct memctl_options_s {
	196	/*
	197	* Memory organization parameters
	198	*
	199	* if DIMM is present in the system
	200	* where DIMMs are with respect to chip select
	201	* where chip selects are with respect to memory boundaries
	202	*/
	203	unsigned int registered_dimm_en; /* use registered DIMM support */
	204
	205	/* Options local to a Chip Select */
	206	struct cs_local_opts_s {
	207	unsigned int auto_precharge;
	208	unsigned int odt_rd_cfg;
	209	unsigned int odt_wr_cfg;
e1fd16b6 YS	210	unsigned int odt_rtt_norm;
e1fd16b6 YS	211	unsigned int odt_rtt_wr;
58e5e9af KG	212	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
	213
	214	/* Special configurations for chip select */
	215	unsigned int memctl_interleaving;
	216	unsigned int memctl_interleaving_mode;
	217	unsigned int ba_intlv_ctl;
7fd101c9	218	unsigned int addr_hash;
58e5e9af KG	219
	220	/* Operational mode parameters */
	221	unsigned int ECC_mode; /* Use ECC? */
	222	/* Initialize ECC using memory controller? */
	223	unsigned int ECC_init_using_memctl;
	224	unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
	225	/* SREN - self-refresh during sleep */
	226	unsigned int self_refresh_in_sleep;
	227	unsigned int dynamic_power; /* DYN_PWR */
	228	/* memory data width to use (16-bit, 32-bit, 64-bit) */
	229	unsigned int data_bus_width;
c360ceac DL	230	unsigned int burst_length; /* BL4, OTF and BL8 */
	231	/* On-The-Fly Burst Chop enable */
	232	unsigned int OTF_burst_chop_en;
	233	/* mirrior DIMMs for DDR3 */
	234	unsigned int mirrored_dimm;
5800e7ab	235	unsigned int quad_rank_present;
d2a9568c	236	unsigned int ap_en; /* address parity enable for RDIMM */
58e5e9af KG	237
	238	/* Global Timing Parameters */
	239	unsigned int cas_latency_override;
	240	unsigned int cas_latency_override_value;
	241	unsigned int use_derated_caslat;
	242	unsigned int additive_latency_override;
	243	unsigned int additive_latency_override_value;
	244
	245	unsigned int clk_adjust; /* */
	246	unsigned int cpo_override;
	247	unsigned int write_data_delay; /* DQS adjust */
bdc9f7b5 DL	248
	249	unsigned int wrlvl_override;
	250	unsigned int wrlvl_sample; /* Write leveling */
	251	unsigned int wrlvl_start;
	252
58e5e9af KG	253	unsigned int half_strength_driver_enable;
	254	unsigned int twoT_en;
	255	unsigned int threeT_en;
	256	unsigned int bstopre;
	257	unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
	258	unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
22cca7e1	259
c360ceac DL	260	/* Rtt impedance */
	261	unsigned int rtt_override; /* rtt_override enable */
	262	unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
1aa3d08a	263	unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
c360ceac	264
22cca7e1 DL	265	/* Automatic self refresh */
	266	unsigned int auto_self_refresh_en;
	267	unsigned int sr_it;
c360ceac DL	268	/* ZQ calibration */
	269	unsigned int zq_en;
	270	/* Write leveling */
	271	unsigned int wrlvl_en;
d2a9568c YS	272	/* RCW override for RDIMM */
	273	unsigned int rcw_override;
	274	unsigned int rcw_1;
	275	unsigned int rcw_2;
	276	/* control register 1 */
	277	unsigned int ddr_cdr1;
23f9670f YS	278
	279	unsigned int trwt_override;
	280	unsigned int trwt; /* read-to-write turnaround */
58e5e9af KG	281	} memctl_options_t;
	282
	283	extern phys_size_t fsl_ddr_sdram(void);
c1fc2d4f	284	extern phys_size_t fsl_ddr_sdram_size(void);
3dbd5d7d	285	extern int fsl_use_spd(void);
f0f89943 KG	286	extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
f0f89943 KG	287	unsigned int ctrl_num);
28a96671	288
38dba0c2 BB	289	/*
	290	* The 85xx boards have a common prototype for fixed_sdram so put the
	291	* declaration here.
	292	*/
	293	#ifdef CONFIG_MPC85xx
	294	extern phys_size_t fixed_sdram(void);
	295	#endif
	296
	297	#if defined(CONFIG_DDR_ECC)
	298	extern void ddr_enable_ecc(unsigned int dram_size);
	299	#endif
	300
	301
28a96671 YS	302	typedef struct fixed_ddr_parm{
	303	int min_freq;
	304	int max_freq;
	305	fsl_ddr_cfg_regs_t *ddr_settings;
	306	} fixed_ddr_parm_t;
58e5e9af	307	#endif