[people/ms/u-boot.git] / arch / powerpc / include / asm / fsl_ddr_sdram.h

/*
 * Copyright 2008-2011 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 */

#ifndef FSL_DDR_MEMCTL_H
#define FSL_DDR_MEMCTL_H

/*
 * Pick a basic DDR Technology.
 */
#include <ddr_spd.h>

#define SDRAM_TYPE_DDR1    2
#define SDRAM_TYPE_DDR2    3
#define SDRAM_TYPE_LPDDR1  6
#define SDRAM_TYPE_DDR3    7

#define DDR_BL4		4	/* burst length 4 */
#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
#define DDR_BL8		8	/* burst length 8 */

#define DDR3_RTT_OFF		0
#define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
#define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
#define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
#define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
#define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */

#define DDR2_RTT_OFF		0
#define DDR2_RTT_75_OHM		1
#define DDR2_RTT_150_OHM	2
#define DDR2_RTT_50_OHM		3

#if defined(CONFIG_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
#endif
#elif defined(CONFIG_FSL_DDR2)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
#endif
#elif defined(CONFIG_FSL_DDR3)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
#endif
#endif	/* #if defined(CONFIG_FSL_DDR1) */

#define FSL_DDR_ODT_NEVER		0x0
#define FSL_DDR_ODT_CS			0x1
#define FSL_DDR_ODT_ALL_OTHER_CS	0x2
#define FSL_DDR_ODT_OTHER_DIMM		0x3
#define FSL_DDR_ODT_ALL			0x4
#define FSL_DDR_ODT_SAME_DIMM		0x5
#define FSL_DDR_ODT_CS_AND_OTHER_DIMM	0x6
#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM	0x7

/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1			0x40
#define FSL_DDR_CS2_CS3			0x20
#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)

/* define memory controller interleaving mode */
#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
#define FSL_DDR_PAGE_INTERLEAVING	0x1
#define FSL_DDR_BANK_INTERLEAVING	0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
#define FSL_DDR_3WAY_1KB_INTERLEAVING	0xA
#define FSL_DDR_3WAY_4KB_INTERLEAVING	0xC
#define FSL_DDR_3WAY_8KB_INTERLEAVING	0xD
/* placeholder for 4-way interleaving */
#define FSL_DDR_4WAY_1KB_INTERLEAVING	0x1A
#define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
#define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D

#define SDRAM_CS_CONFIG_EN		0x80000000

/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
 */
#define SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG_SREN			0x40000000
#define SDRAM_CFG_ECC_EN		0x20000000
#define SDRAM_CFG_RD_EN			0x10000000
#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
#define SDRAM_CFG_DYN_PWR		0x00200000
#define SDRAM_CFG_DBW_MASK		0x00180000
#define SDRAM_CFG_DBW_SHIFT		19
#define SDRAM_CFG_32_BE			0x00080000
#define SDRAM_CFG_16_BE			0x00100000
#define SDRAM_CFG_8_BE			0x00040000
#define SDRAM_CFG_NCAP			0x00020000
#define SDRAM_CFG_2T_EN			0x00008000
#define SDRAM_CFG_BI			0x00000001

#define SDRAM_CFG2_D_INIT		0x00000010
#define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
#define SDRAM_CFG2_ODT_NEVER		0
#define SDRAM_CFG2_ODT_ONLY_WRITE	1
#define SDRAM_CFG2_ODT_ONLY_READ	2
#define SDRAM_CFG2_ODT_ALWAYS		3

#define TIMING_CFG_2_CPO_MASK	0x0F800000

#if defined(CONFIG_P4080)
#define RD_TO_PRE_MASK		0xf
#define RD_TO_PRE_SHIFT		13
#define WR_DATA_DELAY_MASK	0xf
#define WR_DATA_DELAY_SHIFT	9
#else
#define RD_TO_PRE_MASK		0x7
#define RD_TO_PRE_SHIFT		13
#define WR_DATA_DELAY_MASK	0x7
#define WR_DATA_DELAY_SHIFT	10
#endif

/* DDR_MD_CNTL */
#define MD_CNTL_MD_EN		0x80000000
#define MD_CNTL_CS_SEL_CS0	0x00000000
#define MD_CNTL_CS_SEL_CS1	0x10000000
#define MD_CNTL_CS_SEL_CS2	0x20000000
#define MD_CNTL_CS_SEL_CS3	0x30000000
#define MD_CNTL_CS_SEL_CS0_CS1	0x40000000
#define MD_CNTL_CS_SEL_CS2_CS3	0x50000000
#define MD_CNTL_MD_SEL_MR	0x00000000
#define MD_CNTL_MD_SEL_EMR	0x01000000
#define MD_CNTL_MD_SEL_EMR2	0x02000000
#define MD_CNTL_MD_SEL_EMR3	0x03000000
#define MD_CNTL_SET_REF		0x00800000
#define MD_CNTL_SET_PRE		0x00400000
#define MD_CNTL_CKE_CNTL_LOW	0x00100000
#define MD_CNTL_CKE_CNTL_HIGH	0x00200000
#define MD_CNTL_WRCW		0x00080000
#define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)

/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN	0x80000000
#define DDR_CDR1_ODT_SHIFT	17
#define DDR_CDR1_ODT_MASK	0x6
#define DDR_CDR2_ODT_MASK	0x1
#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)

#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
#define DDR_CDR_ODT_OFF		0x0
#define DDR_CDR_ODT_120ohm	0x1
#define DDR_CDR_ODT_180ohm	0x2
#define DDR_CDR_ODT_75ohm	0x3
#define DDR_CDR_ODT_110ohm	0x4
#define DDR_CDR_ODT_60hm	0x5
#define DDR_CDR_ODT_70ohm	0x6
#define DDR_CDR_ODT_47ohm	0x7
#else
#define DDR_CDR_ODT_75ohm	0x0
#define DDR_CDR_ODT_55ohm	0x1
#define DDR_CDR_ODT_60ohm	0x2
#define DDR_CDR_ODT_50ohm	0x3
#define DDR_CDR_ODT_150ohm	0x4
#define DDR_CDR_ODT_43ohm	0x5
#define DDR_CDR_ODT_120ohm	0x6
#endif

/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
	struct {
		unsigned int bnds;
		unsigned int config;
		unsigned int config_2;
	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
	unsigned int timing_cfg_3;
	unsigned int timing_cfg_0;
	unsigned int timing_cfg_1;
	unsigned int timing_cfg_2;
	unsigned int ddr_sdram_cfg;
	unsigned int ddr_sdram_cfg_2;
	unsigned int ddr_sdram_mode;
	unsigned int ddr_sdram_mode_2;
	unsigned int ddr_sdram_mode_3;
	unsigned int ddr_sdram_mode_4;
	unsigned int ddr_sdram_mode_5;
	unsigned int ddr_sdram_mode_6;
	unsigned int ddr_sdram_mode_7;
	unsigned int ddr_sdram_mode_8;
	unsigned int ddr_sdram_md_cntl;
	unsigned int ddr_sdram_interval;
	unsigned int ddr_data_init;
	unsigned int ddr_sdram_clk_cntl;
	unsigned int ddr_init_addr;
	unsigned int ddr_init_ext_addr;
	unsigned int timing_cfg_4;
	unsigned int timing_cfg_5;
	unsigned int ddr_zq_cntl;
	unsigned int ddr_wrlvl_cntl;
	unsigned int ddr_wrlvl_cntl_2;
	unsigned int ddr_wrlvl_cntl_3;
	unsigned int ddr_sr_cntr;
	unsigned int ddr_sdram_rcw_1;
	unsigned int ddr_sdram_rcw_2;
	unsigned int ddr_eor;
	unsigned int ddr_cdr1;
	unsigned int ddr_cdr2;
	unsigned int err_disable;
	unsigned int err_int_en;
	unsigned int debug[32];
} fsl_ddr_cfg_regs_t;

typedef struct memctl_options_partial_s {
	unsigned int all_dimms_ecc_capable;
	unsigned int all_dimms_tckmax_ps;
	unsigned int all_dimms_burst_lengths_bitmask;
	unsigned int all_dimms_registered;
	unsigned int all_dimms_unbuffered;
	/*	unsigned int lowest_common_SPD_caslat; */
	unsigned int all_dimms_minimum_trcd_ps;
} memctl_options_partial_t;

#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
/*
 * Generalized parameters for memory controller configuration,
 * might be a little specific to the FSL memory controller
 */
typedef struct memctl_options_s {
	/*
	 * Memory organization parameters
	 *
	 * if DIMM is present in the system
	 * where DIMMs are with respect to chip select
	 * where chip selects are with respect to memory boundaries
	 */
	unsigned int registered_dimm_en;    /* use registered DIMM support */

	/* Options local to a Chip Select */
	struct cs_local_opts_s {
		unsigned int auto_precharge;
		unsigned int odt_rd_cfg;
		unsigned int odt_wr_cfg;
		unsigned int odt_rtt_norm;
		unsigned int odt_rtt_wr;
	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];

	/* Special configurations for chip select */
	unsigned int memctl_interleaving;
	unsigned int memctl_interleaving_mode;
	unsigned int ba_intlv_ctl;
	unsigned int addr_hash;

	/* Operational mode parameters */
	unsigned int ecc_mode;	 /* Use ECC? */
	/* Initialize ECC using memory controller? */
	unsigned int ecc_init_using_memctl;
	unsigned int dqs_config;	/* Use DQS? maybe only with DDR2? */
	/* SREN - self-refresh during sleep */
	unsigned int self_refresh_in_sleep;
	unsigned int dynamic_power;	/* DYN_PWR */
	/* memory data width to use (16-bit, 32-bit, 64-bit) */
	unsigned int data_bus_width;
	unsigned int burst_length;	/* BL4, OTF and BL8 */
	/* On-The-Fly Burst Chop enable */
	unsigned int otf_burst_chop_en;
	/* mirrior DIMMs for DDR3 */
	unsigned int mirrored_dimm;
	unsigned int quad_rank_present;
	unsigned int ap_en;	/* address parity enable for RDIMM */
	unsigned int x4_en;	/* enable x4 devices */

	/* Global Timing Parameters */
	unsigned int cas_latency_override;
	unsigned int cas_latency_override_value;
	unsigned int use_derated_caslat;
	unsigned int additive_latency_override;
	unsigned int additive_latency_override_value;

	unsigned int clk_adjust;		/* */
	unsigned int cpo_override;
	unsigned int write_data_delay;		/* DQS adjust */

	unsigned int wrlvl_override;
	unsigned int wrlvl_sample;		/* Write leveling */
	unsigned int wrlvl_start;
	unsigned int wrlvl_ctl_2;
	unsigned int wrlvl_ctl_3;

	unsigned int half_strength_driver_enable;
	unsigned int twot_en;
	unsigned int threet_en;
	unsigned int bstopre;
	unsigned int tcke_clock_pulse_width_ps;	/* tCKE */
	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */

	/* Rtt impedance */
	unsigned int rtt_override;		/* rtt_override enable */
	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
	unsigned int rtt_wr_override_value;	/* this is Rtt_WR for DDR3 */

	/* Automatic self refresh */
	unsigned int auto_self_refresh_en;
	unsigned int sr_it;
	/* ZQ calibration */
	unsigned int zq_en;
	/* Write leveling */
	unsigned int wrlvl_en;
	/* RCW override for RDIMM */
	unsigned int rcw_override;
	unsigned int rcw_1;
	unsigned int rcw_2;
	/* control register 1 */
	unsigned int ddr_cdr1;
	unsigned int ddr_cdr2;

	unsigned int trwt_override;
	unsigned int trwt;			/* read-to-write turnaround */
} memctl_options_t;

extern phys_size_t fsl_ddr_sdram(void);
extern phys_size_t fsl_ddr_sdram_size(void);
extern int fsl_use_spd(void);
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
					unsigned int ctrl_num, int step);
u32 fsl_ddr_get_intl3r(void);

static void __board_assert_mem_reset(void)
{
}

static void __board_deassert_mem_reset(void)
{
}

void board_assert_mem_reset(void)
	__attribute__((weak, alias("__board_assert_mem_reset")));

void board_deassert_mem_reset(void)
	__attribute__((weak, alias("__board_deassert_mem_reset")));

static int __board_need_mem_reset(void)
{
	return 0;
}

int board_need_mem_reset(void)
	__attribute__((weak, alias("__board_need_mem_reset")));

/*
 * The 85xx boards have a common prototype for fixed_sdram so put the
 * declaration here.
 */
#ifdef CONFIG_MPC85xx
extern phys_size_t fixed_sdram(void);
#endif

#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif


typedef struct fixed_ddr_parm{
	int min_freq;
	int max_freq;
	fsl_ddr_cfg_regs_t *ddr_settings;
} fixed_ddr_parm_t;
#endif
Commit	Line	Data
58e5e9af	1	/*
3dbd5d7d	2	* Copyright 2008-2011 Freescale Semiconductor, Inc.
58e5e9af KG	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* Version 2 as published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef FSL_DDR_MEMCTL_H
	10	#define FSL_DDR_MEMCTL_H
	11
	12	/*
	13	* Pick a basic DDR Technology.
	14	*/
	15	#include <ddr_spd.h>
	16
	17	#define SDRAM_TYPE_DDR1 2
	18	#define SDRAM_TYPE_DDR2 3
	19	#define SDRAM_TYPE_LPDDR1 6
	20	#define SDRAM_TYPE_DDR3 7
	21
c360ceac DL	22	#define DDR_BL4 4 /* burst length 4 */
	23	#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
	24	#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
	25	#define DDR_BL8 8 /* burst length 8 */
	26
e1fd16b6	27	#define DDR3_RTT_OFF 0
f8d05e5e DL	28	#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
	29	#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
	30	#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
	31	#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
	32	#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
	33
4e57382f YS	34	#define DDR2_RTT_OFF 0
	35	#define DDR2_RTT_75_OHM 1
	36	#define DDR2_RTT_150_OHM 2
	37	#define DDR2_RTT_50_OHM 3
	38
58e5e9af KG	39	#if defined(CONFIG_FSL_DDR1)
	40	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
	41	typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
	42	#ifndef CONFIG_FSL_SDRAM_TYPE
	43	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
	44	#endif
	45	#elif defined(CONFIG_FSL_DDR2)
	46	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
	47	typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
	48	#ifndef CONFIG_FSL_SDRAM_TYPE
	49	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
	50	#endif
	51	#elif defined(CONFIG_FSL_DDR3)
	52	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
	53	typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
22ff3d01 DL	54	#ifndef CONFIG_FSL_SDRAM_TYPE
22ff3d01 DL	55	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
58e5e9af	56	#endif
22ff3d01	57	#endif /* #if defined(CONFIG_FSL_DDR1) */
58e5e9af	58
e1fd16b6 YS	59	#define FSL_DDR_ODT_NEVER 0x0
	60	#define FSL_DDR_ODT_CS 0x1
	61	#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
	62	#define FSL_DDR_ODT_OTHER_DIMM 0x3
	63	#define FSL_DDR_ODT_ALL 0x4
	64	#define FSL_DDR_ODT_SAME_DIMM 0x5
	65	#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
	66	#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
	67
dbbbb3ab HW	68	/* define bank(chip select) interleaving mode */
	69	#define FSL_DDR_CS0_CS1 0x40
	70	#define FSL_DDR_CS2_CS3 0x20
	71	#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 \| FSL_DDR_CS2_CS3)
	72	#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 \| 0x04)
	73
	74	/* define memory controller interleaving mode */
	75	#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
	76	#define FSL_DDR_PAGE_INTERLEAVING 0x1
	77	#define FSL_DDR_BANK_INTERLEAVING 0x2
	78	#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
a4c66509 YS	79	#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
	80	#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
	81	#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
	82	/* placeholder for 4-way interleaving */
	83	#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
	84	#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
	85	#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
dbbbb3ab	86
123922b1 YS	87	#define SDRAM_CS_CONFIG_EN 0x80000000
123922b1 YS	88
e1be0d25 P	89	/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
	90	*/
	91	#define SDRAM_CFG_MEM_EN 0x80000000
	92	#define SDRAM_CFG_SREN 0x40000000
	93	#define SDRAM_CFG_ECC_EN 0x20000000
	94	#define SDRAM_CFG_RD_EN 0x10000000
	95	#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
	96	#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
	97	#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
	98	#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
	99	#define SDRAM_CFG_DYN_PWR 0x00200000
9c6b47d5	100	#define SDRAM_CFG_DBW_MASK 0x00180000
f31cfd19	101	#define SDRAM_CFG_DBW_SHIFT 19
e1be0d25	102	#define SDRAM_CFG_32_BE 0x00080000
0b3b1766	103	#define SDRAM_CFG_16_BE 0x00100000
e1be0d25 P	104	#define SDRAM_CFG_8_BE 0x00040000
	105	#define SDRAM_CFG_NCAP 0x00020000
	106	#define SDRAM_CFG_2T_EN 0x00008000
	107	#define SDRAM_CFG_BI 0x00000001
	108
91671913 YS	109	#define SDRAM_CFG2_D_INIT 0x00000010
91671913 YS	110	#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
cae7c1b5 YS	111	#define SDRAM_CFG2_ODT_NEVER 0
	112	#define SDRAM_CFG2_ODT_ONLY_WRITE 1
	113	#define SDRAM_CFG2_ODT_ONLY_READ 2
	114	#define SDRAM_CFG2_ODT_ALWAYS 3
91671913 YS	115
	116	#define TIMING_CFG_2_CPO_MASK 0x0F800000
	117
c360ceac DL	118	#if defined(CONFIG_P4080)
	119	#define RD_TO_PRE_MASK 0xf
	120	#define RD_TO_PRE_SHIFT 13
	121	#define WR_DATA_DELAY_MASK 0xf
	122	#define WR_DATA_DELAY_SHIFT 9
	123	#else
	124	#define RD_TO_PRE_MASK 0x7
	125	#define RD_TO_PRE_SHIFT 13
	126	#define WR_DATA_DELAY_MASK 0x7
	127	#define WR_DATA_DELAY_SHIFT 10
	128	#endif
	129
fa8d23c0 YS	130	/* DDR_MD_CNTL */
	131	#define MD_CNTL_MD_EN 0x80000000
	132	#define MD_CNTL_CS_SEL_CS0 0x00000000
	133	#define MD_CNTL_CS_SEL_CS1 0x10000000
	134	#define MD_CNTL_CS_SEL_CS2 0x20000000
	135	#define MD_CNTL_CS_SEL_CS3 0x30000000
	136	#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
	137	#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
	138	#define MD_CNTL_MD_SEL_MR 0x00000000
	139	#define MD_CNTL_MD_SEL_EMR 0x01000000
	140	#define MD_CNTL_MD_SEL_EMR2 0x02000000
	141	#define MD_CNTL_MD_SEL_EMR3 0x03000000
	142	#define MD_CNTL_SET_REF 0x00800000
	143	#define MD_CNTL_SET_PRE 0x00400000
	144	#define MD_CNTL_CKE_CNTL_LOW 0x00100000
	145	#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
	146	#define MD_CNTL_WRCW 0x00080000
	147	#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
	148
6b06d7dc YS	149	/* DDR_CDR1 */
6b06d7dc YS	150	#define DDR_CDR1_DHC_EN 0x80000000
57495e4e YS	151	#define DDR_CDR1_ODT_SHIFT 17
	152	#define DDR_CDR1_ODT_MASK 0x6
	153	#define DDR_CDR2_ODT_MASK 0x1
	154	#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
	155	#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
	156
	157	#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
	158	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
	159	#define DDR_CDR_ODT_OFF 0x0
	160	#define DDR_CDR_ODT_120ohm 0x1
	161	#define DDR_CDR_ODT_180ohm 0x2
	162	#define DDR_CDR_ODT_75ohm 0x3
	163	#define DDR_CDR_ODT_110ohm 0x4
	164	#define DDR_CDR_ODT_60hm 0x5
	165	#define DDR_CDR_ODT_70ohm 0x6
	166	#define DDR_CDR_ODT_47ohm 0x7
	167	#else
	168	#define DDR_CDR_ODT_75ohm 0x0
	169	#define DDR_CDR_ODT_55ohm 0x1
	170	#define DDR_CDR_ODT_60ohm 0x2
	171	#define DDR_CDR_ODT_50ohm 0x3
	172	#define DDR_CDR_ODT_150ohm 0x4
	173	#define DDR_CDR_ODT_43ohm 0x5
	174	#define DDR_CDR_ODT_120ohm 0x6
	175	#endif
6b06d7dc	176
58e5e9af KG	177	/* Record of register values computed */
	178	typedef struct fsl_ddr_cfg_regs_s {
	179	struct {
	180	unsigned int bnds;
	181	unsigned int config;
	182	unsigned int config_2;
	183	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
	184	unsigned int timing_cfg_3;
	185	unsigned int timing_cfg_0;
	186	unsigned int timing_cfg_1;
	187	unsigned int timing_cfg_2;
	188	unsigned int ddr_sdram_cfg;
	189	unsigned int ddr_sdram_cfg_2;
	190	unsigned int ddr_sdram_mode;
	191	unsigned int ddr_sdram_mode_2;
e1fd16b6 YS	192	unsigned int ddr_sdram_mode_3;
	193	unsigned int ddr_sdram_mode_4;
	194	unsigned int ddr_sdram_mode_5;
	195	unsigned int ddr_sdram_mode_6;
	196	unsigned int ddr_sdram_mode_7;
	197	unsigned int ddr_sdram_mode_8;
58e5e9af KG	198	unsigned int ddr_sdram_md_cntl;
	199	unsigned int ddr_sdram_interval;
	200	unsigned int ddr_data_init;
	201	unsigned int ddr_sdram_clk_cntl;
	202	unsigned int ddr_init_addr;
	203	unsigned int ddr_init_ext_addr;
	204	unsigned int timing_cfg_4;
	205	unsigned int timing_cfg_5;
	206	unsigned int ddr_zq_cntl;
	207	unsigned int ddr_wrlvl_cntl;
57495e4e YS	208	unsigned int ddr_wrlvl_cntl_2;
57495e4e YS	209	unsigned int ddr_wrlvl_cntl_3;
58e5e9af KG	210	unsigned int ddr_sr_cntr;
	211	unsigned int ddr_sdram_rcw_1;
	212	unsigned int ddr_sdram_rcw_2;
7fd101c9	213	unsigned int ddr_eor;
d2a9568c YS	214	unsigned int ddr_cdr1;
	215	unsigned int ddr_cdr2;
	216	unsigned int err_disable;
	217	unsigned int err_int_en;
	218	unsigned int debug[32];
58e5e9af KG	219	} fsl_ddr_cfg_regs_t;
	220
	221	typedef struct memctl_options_partial_s {
0dd38a35 PJ	222	unsigned int all_dimms_ecc_capable;
	223	unsigned int all_dimms_tckmax_ps;
	224	unsigned int all_dimms_burst_lengths_bitmask;
	225	unsigned int all_dimms_registered;
	226	unsigned int all_dimms_unbuffered;
58e5e9af	227	/* unsigned int lowest_common_SPD_caslat; */
0dd38a35	228	unsigned int all_dimms_minimum_trcd_ps;
58e5e9af KG	229	} memctl_options_partial_t;
58e5e9af KG	230
51d498f1 YS	231	#define DDR_DATA_BUS_WIDTH_64 0
	232	#define DDR_DATA_BUS_WIDTH_32 1
	233	#define DDR_DATA_BUS_WIDTH_16 2
58e5e9af KG	234	/*
	235	* Generalized parameters for memory controller configuration,
	236	* might be a little specific to the FSL memory controller
	237	*/
	238	typedef struct memctl_options_s {
	239	/*
	240	* Memory organization parameters
	241	*
	242	* if DIMM is present in the system
	243	* where DIMMs are with respect to chip select
	244	* where chip selects are with respect to memory boundaries
	245	*/
	246	unsigned int registered_dimm_en; /* use registered DIMM support */
	247
	248	/* Options local to a Chip Select */
	249	struct cs_local_opts_s {
	250	unsigned int auto_precharge;
	251	unsigned int odt_rd_cfg;
	252	unsigned int odt_wr_cfg;
e1fd16b6 YS	253	unsigned int odt_rtt_norm;
e1fd16b6 YS	254	unsigned int odt_rtt_wr;
58e5e9af KG	255	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
	256
	257	/* Special configurations for chip select */
	258	unsigned int memctl_interleaving;
	259	unsigned int memctl_interleaving_mode;
	260	unsigned int ba_intlv_ctl;
7fd101c9	261	unsigned int addr_hash;
58e5e9af KG	262
58e5e9af KG	263	/* Operational mode parameters */
0dd38a35	264	unsigned int ecc_mode; /* Use ECC? */
58e5e9af	265	/* Initialize ECC using memory controller? */
0dd38a35 PJ	266	unsigned int ecc_init_using_memctl;
0dd38a35 PJ	267	unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
58e5e9af KG	268	/* SREN - self-refresh during sleep */
	269	unsigned int self_refresh_in_sleep;
	270	unsigned int dynamic_power; /* DYN_PWR */
	271	/* memory data width to use (16-bit, 32-bit, 64-bit) */
	272	unsigned int data_bus_width;
c360ceac DL	273	unsigned int burst_length; /* BL4, OTF and BL8 */
c360ceac DL	274	/* On-The-Fly Burst Chop enable */
0dd38a35	275	unsigned int otf_burst_chop_en;
c360ceac DL	276	/* mirrior DIMMs for DDR3 */
c360ceac DL	277	unsigned int mirrored_dimm;
5800e7ab	278	unsigned int quad_rank_present;
d2a9568c	279	unsigned int ap_en; /* address parity enable for RDIMM */
b61e0615	280	unsigned int x4_en; /* enable x4 devices */
58e5e9af KG	281
	282	/* Global Timing Parameters */
	283	unsigned int cas_latency_override;
	284	unsigned int cas_latency_override_value;
	285	unsigned int use_derated_caslat;
	286	unsigned int additive_latency_override;
	287	unsigned int additive_latency_override_value;
	288
	289	unsigned int clk_adjust; /* */
	290	unsigned int cpo_override;
	291	unsigned int write_data_delay; /* DQS adjust */
bdc9f7b5 DL	292
	293	unsigned int wrlvl_override;
	294	unsigned int wrlvl_sample; /* Write leveling */
	295	unsigned int wrlvl_start;
57495e4e YS	296	unsigned int wrlvl_ctl_2;
57495e4e YS	297	unsigned int wrlvl_ctl_3;
bdc9f7b5	298
58e5e9af	299	unsigned int half_strength_driver_enable;
0dd38a35 PJ	300	unsigned int twot_en;
0dd38a35 PJ	301	unsigned int threet_en;
58e5e9af	302	unsigned int bstopre;
0dd38a35 PJ	303	unsigned int tcke_clock_pulse_width_ps; /* tCKE */
0dd38a35 PJ	304	unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
22cca7e1	305
c360ceac DL	306	/* Rtt impedance */
	307	unsigned int rtt_override; /* rtt_override enable */
	308	unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
1aa3d08a	309	unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
c360ceac	310
22cca7e1 DL	311	/* Automatic self refresh */
	312	unsigned int auto_self_refresh_en;
	313	unsigned int sr_it;
c360ceac DL	314	/* ZQ calibration */
	315	unsigned int zq_en;
	316	/* Write leveling */
	317	unsigned int wrlvl_en;
d2a9568c YS	318	/* RCW override for RDIMM */
	319	unsigned int rcw_override;
	320	unsigned int rcw_1;
	321	unsigned int rcw_2;
	322	/* control register 1 */
	323	unsigned int ddr_cdr1;
57495e4e	324	unsigned int ddr_cdr2;
23f9670f YS	325
	326	unsigned int trwt_override;
	327	unsigned int trwt; /* read-to-write turnaround */
58e5e9af KG	328	} memctl_options_t;
	329
	330	extern phys_size_t fsl_ddr_sdram(void);
c1fc2d4f	331	extern phys_size_t fsl_ddr_sdram_size(void);
3dbd5d7d	332	extern int fsl_use_spd(void);
f0f89943	333	extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
c63e1370	334	unsigned int ctrl_num, int step);
f31cfd19	335	u32 fsl_ddr_get_intl3r(void);
28a96671	336
c63e1370 YS	337	static void __board_assert_mem_reset(void)
	338	{
	339	}
	340
	341	static void __board_deassert_mem_reset(void)
	342	{
	343	}
	344
	345	void board_assert_mem_reset(void)
	346	__attribute__((weak, alias("__board_assert_mem_reset")));
	347
	348	void board_deassert_mem_reset(void)
	349	__attribute__((weak, alias("__board_deassert_mem_reset")));
	350
	351	static int __board_need_mem_reset(void)
	352	{
	353	return 0;
	354	}
	355
	356	int board_need_mem_reset(void)
	357	__attribute__((weak, alias("__board_need_mem_reset")));
	358
38dba0c2 BB	359	/*
	360	* The 85xx boards have a common prototype for fixed_sdram so put the
	361	* declaration here.
	362	*/
	363	#ifdef CONFIG_MPC85xx
	364	extern phys_size_t fixed_sdram(void);
	365	#endif
	366
	367	#if defined(CONFIG_DDR_ECC)
	368	extern void ddr_enable_ecc(unsigned int dram_size);
	369	#endif
	370
	371
28a96671 YS	372	typedef struct fixed_ddr_parm{
	373	int min_freq;
	374	int max_freq;
	375	fsl_ddr_cfg_regs_t *ddr_settings;
	376	} fixed_ddr_parm_t;
58e5e9af	377	#endif